KR20160097919A - Solar cell - Google Patents

Abstract

According to an embodiment of the present invention, a solar cell includes: a semiconductor substrate; a first middle layer located on one surface of the semiconductor substrate; a second middle layer located on the other surface of the semiconductor substrate; a first conductive area located on the first middle layer; a second conductive area located on the second middle layer; a first electrode connected to the first conductive area; and a second electrode connected to the second conductive area. A degree of crystallization of the first conductive area is higher than that of the second conductive area.

Description

Solar cell {SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a solar cell having an improved structure.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize the solar cell, it is necessary to overcome the low efficiency and to have a solar cell capable of maximizing the efficiency of the solar cell. There is also a need for a method of manufacturing a solar cell that can simplify the manufacturing method of the solar cell having excellent efficiency.

The present invention provides a solar cell that can be manufactured by a simple manufacturing process and can improve efficiency.

A solar cell according to this embodiment includes: a semiconductor substrate; A first intermediate layer located on one surface of the semiconductor substrate; A second intermediate layer located on the other surface of the semiconductor substrate; A first conductive type region located above the first intermediate layer; A second conductive type region located above the second intermediate layer; A first electrode coupled to the first conductive type region; And a second electrode connected to the second conductive type region, wherein the crystallinity of the first conductive type region is larger than the crystallinity of the second conductive type region.

According to this embodiment, considering the conductivity type of the dopant in the first and second conductivity type regions, the positions of the first and second conductivity type regions, and the like, the crystallinity, the electric conductivity, the thickness , Hydrogen concentration, and the like. In addition, the first and second intermediate layers connected to the first and second conductivity type regions have different electrical conductivities, materials, thicknesses, and the like. As a result, the open circuit voltage and the filling density of the solar cell can be improved to improve the efficiency of the solar cell.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a plan view of the solar cell shown in Fig.
FIG. 3 is a graph showing resistivity according to a firing time at each firing temperature in a firing process of an electrode of a solar cell.
4 is a graph showing an example of a Raman spectrum of a first conductivity type region including p-type silicon including an amorphous portion and a crystalline portion.
5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
6 is a cross-sectional view of a solar cell according to a modification of the present invention.
7A to 7I are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

 FIG. 1 is a cross-sectional view of a solar cell according to an embodiment of the present invention, and FIG. 2 is a plan view of the solar cell shown in FIG. In FIG. 2, the semiconductor substrate and the metal electrode layer are mainly shown.

1, a solar cell 100 according to the present embodiment includes a semiconductor substrate 110, a first intermediate layer 22 and a first conductive type region 20 located on one surface of the semiconductor substrate 110, A second intermediate layer 24 and a second conductive type region 30 located on the other surface of the semiconductor substrate 110 and first and second conductive type regions 30 and 30 connected to the first and second conductive type regions 20 and 30, And two electrodes 42 and 44. For example, one surface of the semiconductor substrate 110 may be the rear surface of the semiconductor substrate 110, and the other surface of the semiconductor substrate 110 may be the front surface of the semiconductor substrate 110. The crystallinity of the first conductive type region 20 is lower than that of the second conductive type region 30 and the crystallinity of the first conductive type region 20 is lower than that of the second conductive type region 30, can be different. This will be explained in more detail.

The semiconductor substrate 110 may be formed of a crystalline semiconductor. In one example, the semiconductor substrate 110 may be composed of a single crystal or polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon). In particular, the semiconductor substrate 110 may be composed of a single crystal semiconductor (for example, a single crystal semiconductor wafer, more specifically, a single crystal silicon wafer). When the semiconductor substrate 110 is made of a single crystal semiconductor (for example, single crystal silicon), the solar cell 100 is based on a semiconductor substrate 110 composed of a crystalline semiconductor having a high crystallinity and having few defects . Accordingly, the solar cell 100 can have excellent electrical characteristics.

In this embodiment, the semiconductor substrate 110 may be formed only of the base region 10 doped with a low doping concentration of the first or second conductivity type dopant. That is, in a conventional solar cell, a doping region having a conductivity type different from that of the semiconductor substrate 110 or a doping region having the same conductivity type as the semiconductor substrate 110 and having a high doping concentration is formed on the semiconductor substrate 110 In this embodiment, the semiconductor substrate 110 includes only the base region 10 and does not have a separate doping region. At this time, the base region 10 of the semiconductor substrate 110 may include a first conductivity type dopant at a lower doping concentration than the first conductivity type region 20, or a second conductivity type dopant at a second conductivity type region 30). ≪ / RTI >

For example, the base region 10 may include a second conductivity type dopant that is different from the first conductivity type region 20 located on the backside of the semiconductor substrate 110. Then, the second conductive type region 30 functions as an emitter region, being located on the rear surface of the semiconductor substrate 110. Then, the second conductivity type region 30, which is an emitter region, is located on the rear surface of the semiconductor substrate 110, which is relatively less incident on the semiconductor substrate 110. As a result, the second conductivity type region 30, which is the emitter region, can be formed with a sufficient thickness, and the photoelectric conversion efficiency can be further improved. This will be described in more detail later.

The dopant of the base region 10 may be an n-type or a p-type dopant. That is, when the dopant of the base region 10 is n-type, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) When the dopant of the base region 10 is p-type, a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used.

As described above, in this embodiment, the semiconductor substrate 110 is formed only as a base region and does not have a separate doped region. For example, the highest doping concentration difference for the lowest doping concentration in the semiconductor substrate 110 may be less than 10%. At this time, the content of 10% or less is only one example for defining the degree of doping for forming a separate dopant region, but the present invention is not limited thereto. Accordingly, the present invention includes all cases where the semiconductor substrate 110 does not have a separate doped region.

In this embodiment, since a separate doping region is not formed in the semiconductor substrate 110, the open-circuit voltage can be improved. This is because it is possible to prevent surface recombination which may occur by forming a doped region in the semiconductor substrate 110. [

The front surface and / or the rear surface of the semiconductor substrate 110 may be textured to have irregularities. For example, the irregularities may have a pyramid shape having an irregular size, the outer surface of which is composed of the (111) surface of the semiconductor substrate 110. The surface roughness of the front surface of the semiconductor substrate 110 may be larger than the surface roughness of the semiconductor substrate 110 because the irregularities are formed only on the front surface of the semiconductor substrate 110 and not on the semiconductor substrate 110. [ For example, the rear surface of the semiconductor substrate 110 may be a flat surface formed by mirror polishing.

When the surface roughness of the front surface of the semiconductor substrate 110 is increased by texturing, the reflectance of light incident through the front surface of the semiconductor substrate 110 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 10 and the first conductivity type region 20 can be increased, so that the optical loss can be minimized. In addition, the rear surface of the semiconductor substrate 110 has a surface roughness smaller than that of the semiconductor substrate 110, so that the reflectance can be improved. Then, the light that is incident on the front surface of the semiconductor substrate 110 and reaches the rear surface of the semiconductor substrate 110 can be reflected toward the front surface of the semiconductor substrate 110 and reused. And the rear surface of the semiconductor substrate 110 has a relatively small surface roughness and can have excellent passivation characteristics. However, the present invention is not limited thereto. Therefore, irregularities due to texturing may not be formed on the front and rear surfaces of the semiconductor substrate 110, and irregularities due to texturing may be formed on the front and rear surfaces of the semiconductor substrate 110, respectively.

The first intermediate layer 22 may be formed on the rear surface of the semiconductor substrate 110. In one example, the first intermediate layer 22 may contact the rear surface of the semiconductor substrate 110. At this time, the first intermediate layer 22 may be formed entirely on the rear surface of the semiconductor substrate 110. Here, the term " entirely formed " includes not only a complete formation but also a partial formation of an unavoidable region. Accordingly, the second intermediate layer 24 can be easily formed without requiring a separate patterning process. In this embodiment, it is exemplified that the back surface of the semiconductor substrate 110 is not entirely formed by texturing irregularities, but the present invention is not limited thereto. The back surface of the semiconductor substrate 110 may be provided with concavities and convexities by texturing as a whole.

The first intermediate layer 22 may be a tunneling layer. That is, the first intermediate layer 22 functions as a kind of barrier for electrons and holes, prevents the minority carriers from passing through the first intermediate layer 22, and after accumulating in the portion adjacent to the first intermediate layer 22, So that only the majority carrier having the second intermediate layer 22 can pass through the first intermediate layer 22. At this time, the majority carriers having energy higher than a certain level can easily pass through the first intermediate layer 22 by the tunneling effect. In addition, the first intermediate layer 22 may serve as a diffusion barrier for preventing the dopant of the first conductivity type region 20 from diffusing into the semiconductor substrate 110. The first intermediate layer 22 may include various materials through which a plurality of carriers can be tunneled. For example, the first intermediate layer 22 may include an insulating material such as an oxide, a nitride, or the like. For example, the first intermediate layer 22 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. In particular, the first intermediate layer 22 may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier.

The first conductive type region 20 may be located on the first intermediate layer 22. As an example, the first conductive type region 20 may be located in contact with the first intermediate layer 22. The first conductive type region 20 may include a semiconductor (e.g., silicon) including a first conductive type dopant. Then, it is possible to prevent a problem that may occur when the semiconductor substrate 110 including the silicon has characteristics similar to those of the semiconductor substrate 110 and includes different semiconductor materials.

In this embodiment, the first conductive type region 20 is formed separately from the semiconductor substrate 110 on the semiconductor substrate 110 (more specifically, on the first intermediate layer 22) and the first conductive type dopant Doped semiconductor layer. The first conductive type region 20 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 110 so that the first conductive type region 20 can be easily formed on the semiconductor substrate 110. For example, in this embodiment, the first conductive type region 20 may be composed of a semiconductor layer doped with a first conductive type dopant and including an amorphous portion and a crystalline portion together. This will be described in more detail later.

At this time, the first conductive type dopant may have a p-type and the first conductive type region 20 may have a p-type region. A Group 3 element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used as the first conductive type dopant. The first conductive type dopant may be included in the semiconductor layer in the step of forming the semiconductor layer constituting the first conductivity type region 20. [ Alternatively, after the semiconductor layer constituting the first conductivity type region 20 is formed, the first conductivity type dopant may be doped by various doping methods such as a thermal diffusion method and an ion implantation method.

The first conductivity type region 20 may be formed separately from the semiconductor substrate 110 to prevent a defect or a decrease in open-circuit voltage that may occur during formation of a doped region in the semiconductor substrate 110 . Thus, the open-circuit voltage of the solar cell 100 can be improved. have.

The first electrode 42 connected to the first conductive type region 20 may be positioned thereon. For example, the first electrode 42 may include a transparent electrode layer 421 and a metal electrode layer 422 which are sequentially stacked on the first conductive type region 20. When the first intermediate layer 22 is formed on the front surface of the semiconductor substrate 110 and the first conductive type region 20 is formed on the first intermediate layer 22 as described above, The characteristics can be greatly improved and the cost can be reduced by reducing the thickness of the expensive semiconductor substrate 110 and the solar cell 100 can be manufactured at a low process temperature. However, the crystallinity of the first conductivity type region 20 is relatively low and the mobility of the carrier may be relatively small. Accordingly, in this embodiment, the first electrode 42 includes the transparent electrode layer 421 and the metal electrode layer 422 to reduce the resistance when the carrier moves in the horizontal direction.

Here, the transparent electrode layer 421 may be formed entirely on the first conductive type region 20 (for example, in contact with the first conductive type region 20). The formation of the whole may include not only covering the entire first conductive region 20 without voids or voids, but also inevitably a case where some portions are not formed. When the transparent electrode layer 421 is formed entirely on the first conductive type region 20, the carrier can easily reach the metal electrode layer 422 through the transparent electrode layer 421, thereby reducing the resistance in the horizontal direction have.

The transparent electrode layer 421 is made of a transparent conductive material so that the carrier can be easily moved. For example, the transparent electrode layer 421 may include indium tin oxide (ITO), carbon nano tube (CNT), or the like. However, the present invention is not limited thereto, and the transparent electrode layer 421 may include various other materials.

In this embodiment, the transparent electrode layer 421 can function as a reflective layer for reflecting light. For this, the refractive index of the transparent electrode layer 421 may be smaller than that of the first conductivity type region 20. For example, the refractive index of the transparent electrode layer 421 may be 1.9 to 2.1, and the refractive index of the first conductivity type region 20 may be 3.0 to 5.0. At this time, the wavelength of light which is a reference of the refractive index is not limited to a specific value, but, for example, the refractive index can be measured based on light having a wavelength of 550 nm. This can be applied to the refractive indices described below.

When the transparent electrode layer 421 having a refractive index lower than that of the first conductive type region 20 is disposed on the first conductive type region 20 as described above, the transparent electrode layer 421 passing through the first conductive type region 20, The light can be easily reflected to the front due to the refractive index difference between the first conductive type region 20 and the transparent electrode layer 421. Thus, in this embodiment, since the transparent electrode layer 421 functions as a reflective layer (i.e., has a reflective layer composed of a transparent conductive material), the optical characteristics can be improved by a simple structure while minimizing the loss of light. However, the present invention is not limited thereto, and various modifications such as providing a reflective layer separately on the transparent electrode layer 421 are possible.

A metal electrode layer 422 may be formed on the transparent electrode layer 421. For example, the metal electrode layer 422 may be formed in contact with the transparent electrode layer 421 to simplify the structure of the first electrode 42. However, the present invention is not limited thereto, and various modifications such as the existence of a separate layer between the transparent electrode layer 421 and the metal electrode layer 422 are possible.

The metal electrode layer 422 located on the transparent electrode layer 421 may be formed of a material having a higher electric conductivity than the transparent electrode layer 421. As a result, characteristics such as carrier collection efficiency and resistance reduction by the metal electrode layer 422 can be further improved. For example, the metal electrode layer 422 may be composed of an opaque material having excellent electric conductivity or a metal having a lower transparency than the transparent electrode layer 421. The planar shape of the metal electrode layer 422 will be described later in more detail with reference to FIG.

A second intermediate layer 24 may be formed on the front surface of the semiconductor substrate 110. For example, the second intermediate layer 24 may be formed in contact with the front surface of the semiconductor substrate 110. At this time, the second intermediate layer 24 may be formed entirely on the front surface of the semiconductor substrate 110. Here, the term " entirely formed " includes not only a complete formation but also a partial formation of an unavoidable region. Accordingly, the second intermediate layer 24 can be easily formed without requiring a separate patterning process. In the present embodiment, the entire surface of the semiconductor substrate 110 is formed with concave and convex portions by texturing, but the present invention is not limited thereto. The surface of the semiconductor substrate 110 may not be provided with irregularities due to texturing.

The second intermediate layer 24 may be a passivation layer. More specifically, the second intermediate layer 24 may comprise an intrinsic amorphous semiconductor (e. G., Intrinsic amorphous silicon) comprising hydrogen. If the second intermediate layer 24 includes an intrinsic amorphous semiconductor (for example, intrinsic amorphous silicon), the second intermediate layer 24 has characteristics similar to those of the semiconductor substrate 110, The passivation can be effectively performed. Since the second intermediate layer 24 has a semiconductor material and is superior in electrical conductivity to the first intermediate layer 22 having an insulating material, the electrical connection property between the semiconductor substrate 110 and the second conductivity type region 30 is improved . Thus, the carrier can be stably transferred to the second conductivity type region 30.

A second conductive type region 30 is formed on the second intermediate layer 24. As an example, the second conductive type region 30 may be formed in contact with the second intermediate layer 24. The second conductive type region 30 may include a semiconductor including a second conductive type dopant. In this embodiment, the second conductivity type region 30 is formed separately from the semiconductor substrate 110 on the semiconductor substrate 110 (more specifically, on the second intermediate layer 24) and the second conductivity type dopant Doped semiconductor layer. The second conductivity type region 30 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 110 so that the second conductivity type region 30 can be easily formed on the semiconductor substrate 110. For example, in the present embodiment, the second conductivity type region 30 may be doped with a second conductivity type dopant and be composed of an amorphous portion. This will be described in more detail later.

The semiconductor material of the second conductivity type region 30 may include silicon (Si). Thus, it is possible to prevent a problem that may occur when the semiconductor substrate 110 has characteristics similar to those of the semiconductor substrate 110 and includes different semiconductor materials.

Alternatively, the semiconductor material of the second conductivity type region 30 may include silicon, that is, silicon carbide or silicon nitride, containing carbon or oxygen. Thus, if the second conductive type region 30 includes silicon carbide or silicon nitride, the photocurrent loss can be minimized by a large energy band gap. At this time, the formula of the silicon carbide is SiCx, and x? 0.1. If x is 0.1 or less, carbon can be contained in a small amount so that it can sufficiently function as a semiconductor by silicon. For example, 0.01? X? 0.1. If x is less than 0.01, the effect of improving the energy band gap may not be large. The chemical formula of the silicon nitride is SiOy, and y? 1. As described above, when y is 0.1 or less, oxygen can be included as an enemy content, and the silicon can sufficiently serve as a semiconductor. For example, 0.01? Y? 0.2. When y is less than 0.01, the effect of improving the energy band gap may not be large, and when y is 0.2 or less, the electric conductivity may be further improved.

At this time, the second conductivity type dopant may have an n-type and the second conductivity type region 30 may have an n-type region. For example, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used as the second conductivity type dopant. The second conductive type dopant may be included in the semiconductor layer in the step of forming the semiconductor layer constituting the second conductivity type region 30. [ Alternatively, after the semiconductor layer constituting the second conductivity type region 30 is formed, the second conductivity type dopant may be doped by various doping methods such as a thermal diffusion method and an ion implantation method.

As described above, when the second conductivity type region 30 includes an amorphous semiconductor, the second conductivity type region 30 is formed of a material selected from the group consisting of na-Si, na-SiCx (x? 0.1) ). ≪ / RTI >

The second conductivity type region 30 may be formed separately from the semiconductor substrate 110 to prevent a defect or a decrease in open-circuit voltage that may occur during the formation of a doped region in the semiconductor substrate 110 . Thus, the open-circuit voltage of the solar cell 100 can be improved. have.

A second electrode 44 connected thereto may be located on the second conductivity type region 30. For example, the second electrode 44 may include a transparent electrode layer 441 and a metal electrode layer 442 that are sequentially stacked on the second conductive type region 20. The description of the transparent electrode layer 421 and the metal electrode layer 422 of the first electrode 42 can be applied as it is without the substrate opposite to the transparent electrode layer 441 and the metal electrode layer 442 of the second electrode 44 Therefore, a description thereof will be omitted.

In this embodiment, the transparent electrode layer 441 can function as an antireflection layer. For this, the refractive index of the transparent electrode layer 441 may be smaller than that of the second conductivity type region 30. If a layer having a smaller refractive index than that of the second conductivity type region 30 and reducing the refractive index to the outside is disposed in the portion where the light is incident, the reflection of light can be prevented. For example, the refractive index of the transparent electrode layer 441 may be 1.9 to 2.1, and the refractive index of the second conductivity type region 30 may be 3.0 to 4.0. As described above, since the transparent electrode layer 441 functions as an antireflection layer (that is, the antireflection layer is made of a transparent conductive material), the optical characteristics can be improved by a simple structure while minimizing the loss of light. However, the present invention is not limited thereto, and various modifications such as the provision of an anti-reflection layer are possible.

Planar shapes of the metal electrode layers 422 and 442 of the first electrode 42 and the second electrode 44 will be described in more detail with reference to FIG.

Referring to FIG. 2, the metal electrode layers 422 and 442 of the first and second electrodes 42 and 44 may include a plurality of finger electrodes 422a and 442a spaced apart from each other with a predetermined pitch. Although the finger electrodes 422a and 442a are parallel to each other and parallel to one edge of the semiconductor substrate 110, the present invention is not limited thereto. The metal electrode layers 442 and 442 of the first and second electrodes 42 and 44 are formed in a direction intersecting with the plurality of finger electrodes 422a and 442a and are connected to the bus bars 422a and 442a, Electrodes 422b and 442b. Only one bus bar electrode 422b or 442b may be provided or a plurality of bus bar electrodes 422b and 442b may be provided with a pitch larger than the pitch of the finger electrodes 422a and 442a as shown in FIG. At this time, the width of the bus bar electrodes 422b and 442b may be larger than the width of the finger electrodes 422a and 442a, but the present invention is not limited thereto. Therefore, the bus bar electrodes 422b and 442b may not be provided, or the width of the bus bar electrodes 422b and 442b may be equal to or smaller than the width of the finger electrodes 422a and 442a.

According to the present embodiment, the first electrode 42 includes a plurality of finger electrodes 422a and 442a to improve current collection efficiency. In addition, the first electrode 42 may be formed with a pattern so that light can be incident on a region other than the first conductivity type region 20 well.

In the drawing, the metal electrode layers 422 and 442 of the first electrode 42 and the second electrode 44 have the same planar shape for the sake of simplicity. The width and pitch of the finger electrode 422a and the bus bar electrode 422b of the first electrode 42 are not limited to the finger electrode 442a and the bus bar electrode 422a of the second electrode 44, A width, a pitch, and the like of the first electrode 442b. Particularly, the finger electrode 442a of the second electrode 44 and / or the bus bar electrode 442b of the second electrode 44 are arranged so that the area of the second electrode 44, which receives more sunlight, is smaller than the area of the first electrode 42 Or the bus bar electrode 422b of the first electrode 42 or the width of the finger electrode 442a and / or the bus bar electrode 422b of the second electrode 44 may be made smaller than the width of the finger electrode 422a and / 442b may be made larger than the pitch of the finger electrode 422a and / or the bus bar electrode 422b of the first electrode 42. [ The planar shape of the metal electrode layer 422 of the first electrode 42 and the metal electrode layer 442 of the second electrode 44 may be different from each other and various other modifications are possible.

As described above, in this embodiment, since the first and second electrodes 42 and 44 of the solar cell 100 have a predetermined pattern, and the solar cell 100 can be incident on the front and rear surfaces of the semiconductor substrate 110 It has a bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited thereto, and it is also possible that the metal electrode layer 442 of the second electrode 44 is formed entirely on the rear side of the semiconductor substrate 110. Various other variations are possible.

As described above, in the present embodiment, the first conductive type region 20 having a p-type has a crystalline portion and the amorphous portion, and the second conductive type region 30 having the n-type may have substantially only an amorphous portion . The crystallinity of the first conductivity type region 20 having p-type conductivity may be greater than the crystallinity of the second conductivity type region 30 having n-type conductivity. The first intermediate layer 22 positioned between the semiconductor substrate 110 and the first conductive type region 20 and the second intermediate layer 24 positioned between the semiconductor substrate 110 and the second conductive type region 30 ) Differ in at least one of thickness, material, and electrical conductivity. This will be explained in more detail.

The p-type first conductivity type region 20 includes both a crystalline portion and an amorphous portion. Here, the crystalline portion may be a portion composed of a polycrystalline or microcrystalline semiconductor (polycrystalline or microcrystalline silicon), and the amorphous portion may be a portion composed of an amorphous semiconductor (e.g., amorphous silicon). As described above, the p-type first conductivity type region 20 includes both the crystalline portion and the amorphous portion, and can be manufactured at a relatively low temperature and can prevent deterioration that may occur during temperature rise while improving various characteristics .

To describe this in more detail, when the conductive type region is made of an amorphous semiconductor, a high hydrogen content in the conductive type region is required to have excellent passivation characteristics. However, in such a conductive region made of an amorphous semiconductor, hydrogen easily escapes to the outside at a high temperature, so that the passivation characteristic is deteriorated, thereby deteriorating the characteristics of the conductive region. In particular, a p-type conductivity type region made of an amorphous semiconductor can be easily deteriorated even at a lower temperature than an n-type conductivity type region made of an amorphous semiconductor. For example, the p-type conductivity type region made of an amorphous semiconductor can easily deteriorate at a relatively low temperature of about 200 캜.

Accordingly, in a solar cell having a p-type conductivity type region made of an amorphous semiconductor, even if the electrode is formed using a paste, it is required to be baked at a temperature of 200 ° C or less. Referring to FIG. 3, when the firing temperature is low, the resistivity is greatly increased when the firing time is short. Therefore, the electrode should have high resistivity or increase the firing time. This may degrade solar cell characteristics or increase the manufacturing process time. Or if the electrode is formed by a method other than paste, the manufacturing cost and the like may be increased. In addition, a tabbing process or the like for attaching ribbons, wires or the like to the other solar cells must be performed at a temperature of 200 ° C or higher. At this time, the p-type conductivity type region may be deteriorated.

On the other hand, according to this embodiment, the p-type first conductivity type region 20 includes a crystalline portion composed of a crystalline semiconductor. Thus, the p-type first conductivity type region 20 including the crystalline portion can be prevented from easily deteriorating even at a temperature of about 200 캜. And the conductivity improves by the crystalline portion and the doping efficiency by the first conductivity type dopant can be improved. This is because the crystalline portion has higher mobility than the amorphous portion and can exhibit a lower resistivity even when doping the same amount of dopant. In addition, the p-type first conductivity type region 20 includes an amorphous portion having an energy band gap higher than that of the crystalline portion, so that the energy band bending at the junction with the semiconductor substrate 110 ) Can be increased. Thereby, the solar cell 100 can have a larger open-circuit voltage.

That is, in the present embodiment, the p-type first conductivity type region 20 includes the amorphous portion and the crystalline portion together to improve the electric conductivity, the doping efficiency, and the energy band bending effect, .

As an example, in the first conductivity type region 20, the crystalline portion may be equal to or more than the amorphous portion or may have a larger volume than the amorphous portion. Thus, sufficient electric conductivity, excellent doping efficiency, and large energy band bending effect can be stably realized. The ratio of the crystalline portion of the first conductive type region 20 can be controlled by controlling process conditions and the like at the time of forming the first conductive type region 20.

For example, the degree of crystallinity (i.e., the proportion of the crystalline portion) of the first conductivity type region 20 can be from 50% to 90%, and more specifically, from 60% to 90%. If the crystallinity of the first conductivity type region 20 is less than 50%, deterioration at low temperature may occur without excellent electrical conductivity and doping efficiency. The crystallinity of the first conductivity type region 20 may be 60% or more in order to improve the electric conductivity and the doping efficiency and further improve the deterioration phenomenon at low temperatures. If the crystallinity of the first conductivity type region 20 exceeds 90%, the energy band deflection effect is not sufficient and the open-circuit voltage may be lowered. However, the present invention is not limited thereto.

And the second conductivity type region 30 can be made substantially of only an amorphous portion. The second conductivity type region 30 formed of the n-type amorphous portion may be disposed on the entire surface of the semiconductor substrate 110 where light is relatively heavily incident, thereby preventing light loss. When the crystalline portion is located on the entire surface of the semiconductor substrate 110, light may be absorbed and lost in the crystalline portion. In consideration of this, the second conductivity type region 30 may include more amorphous portions. In this case, the second conductivity type region 30 may be an n-type silicon carbide (na-SiCx) (here, x? 0.1, for example, n-type amorphous silicon, (0.01? X? 0.1) or silicon nitride (na-SiOy) where y? 1, for example, 0.01? X? 0.2, the photocurrent loss can be minimized by having a larger energy bandgap.

For example, the degree of crystallization of the second conductivity type region 30 may be approximately zero, and the degree of crystallinity of the second conductivity type region 30 may be less than the degree of crystallinity of the first conductivity type region 20. However, due to process errors and the like, it is inevitable that some crystalline portions are included in the second conductivity type region 30. Thus, even when the second conductivity type region 30 includes a crystalline portion, the amorphous portion in the second conductivity type region 30 may be equal to or more than the crystalline portion or have a larger volume than the crystalline portion have. For example, the crystallinity of the second conductivity type region 30 may be 10% or less.

By way of reference, the crystallinity can be measured by various methods. In one example, the crystallinity can be measured by Raman spectrum. When the Raman spectrum of the first conductivity type region 20 including the p-type silicon including the amorphous portion and the crystalline portion as in this embodiment is obtained, the spectrum as shown by the solid line in Fig. 4 is obtained. The spectrum shown in Fig. 4 is divided into a spectrum of crystalline silicon (c-Si), a spectrum of grain boundaries g.b, and a spectrum of amorphous silicon (a-Si), as shown by the dotted line in Fig. The sum of the lower area of the spectrum by crystalline silicon and the lower area of the spectrum by grain boundaries is referred to as the crystalline portion and the lower area of the spectrum by the amorphous silicon can be regarded as the amorphous portion. The ratio of the area corresponding to the crystalline portion to the total bottom area can be regarded as the degree of crystallization. However, since the present invention is an example of measuring the degree of crystallinity, the degree of crystallization can be measured by various other methods.

The hydrogen concentration in the first conductivity type region 20 may be less than the hydrogen concentration in the second conductivity type region 30. This is because the first conductivity type region 20 has a high degree of crystallinity and the fraction of the grain boundary is high, so that the second conductivity type region 30 hardly contains more hydrogen than the second conductivity type region 30. As an example, the hydrogen concentration in the first or second conductivity type region 30 can be measured by secondary ion mass spectroscopy (SIMS). However, the present invention is not limited thereto.

The first conductivity type region 20 may be located on the rear surface of the semiconductor substrate 110 and the second conductivity type region 30 may be located on the front surface of the semiconductor substrate 110. [ If the second conductivity type region 30 having a relatively high hydrogen concentration is located on the front surface of the semiconductor substrate 110, the photocurrent loss due to the recombination of electrons and holes can be reduced. On the contrary, when the first conductivity type region 20 having a low hydrogen concentration is located on the front surface of the semiconductor substrate 110, the electron-holes generated by the light can be quickly recombined and lost before being collected into the electrodes. Thus, the photocurrent can be greatly reduced.

In this embodiment, the thickness of the first conductive region 20 located on the rear surface of the semiconductor substrate 110 may be greater than the thickness of the second conductive region 30 located on the front surface of the semiconductor substrate 110 . The thickness of the second conductivity type region 30 located on the front surface of the semiconductor substrate 110 where most of the light is incident can be reduced to minimize the optical loss due to the second conductivity type region 30. The first conductivity type region 20 located on the rear surface of the semiconductor substrate 110 may be formed to have a sufficient thickness to improve electrical characteristics.

As described above, in this embodiment, the first conductivity type region 20 having a conductivity type opposite to that of the semiconductor substrate 110 and functioning as an emitter region is located on the rear surface of the semiconductor substrate 110, The second conductive type region 30 having the same conductivity type as the first conductive type semiconductor layer 110 and functioning as a front electric field region may be located on the front surface of the semiconductor substrate 110. [ Accordingly, the first conductivity type region 20, which is an emitter region forming a pn junction (for example, a pn tunnel junction) directly involved in photoelectric conversion with the semiconductor substrate 110, is formed to a sufficient thickness to improve the photoelectric conversion efficiency can do.

For example, the thickness of the first conductivity type region 20 may be between 10 nm and 500 nm, and the thickness of the second conductivity type region 30 may be between 5 nm and 10 nm. If the thickness of the first conductivity type region 20 is less than 10 nm, it may be difficult to stably perform the role of the first conductivity type region 20. If the thickness exceeds 500 nm of the first conductivity type region 20, the manufacturing process time may become longer. In this case, when the first electrode 42 includes the transparent electrode layer 421 as in the present embodiment, the thickness of the first conductivity type region 20 can be reduced, so that the thickness of the first conductivity type region 20 May be between 10 nm and 100 nm. The thickness of the second conductivity type region 30 is limited so as to effectively perform its role as the second conductivity type region 30.

The first intermediate layer 22 positioned between the semiconductor substrate 110 and the first conductive type region 20 and the second intermediate layer 24 positioned between the semiconductor substrate 110 and the second conductive type region 30 At least one of thickness, material, and electrical conductivity is different.

More specifically, as described above, the first intermediate layer 22 connected to the first conductive type region 20 including an amorphous portion and a crystalline portion may include an insulating material to serve as a tunneling layer, The second intermediate layer 24, which is connected to the second conductive type region 30, may comprise a semiconductor material. That is, the first and second intermediate layers 22 and 24 may be formed of a material suitable for the first and second conductivity type regions 20 and 30, thereby improving carrier transfer characteristics.

That is, since the electrical conductivity of the first conductive type region 20 is low, the first intermediate layer 22 connecting the semiconductor substrate 110 and the first conductive type region 20 has a higher electric conductivity than the second intermediate layer 24, . Since the electrical conductivity of the second conductivity type region 30 is high, the second intermediate layer 24 connecting the semiconductor substrate 110 and the second conductivity type region 30 is formed of an insulating material so as to exhibit a tunneling effect. And can have low electrical conductivity.

At this time, the thickness of the first intermediate layer 22 may be equal to or less than the thickness of the second intermediate layer 24. The first intermediate layer 22 may have a relatively small thickness to exhibit a tunneling effect and the second intermediate layer 24 may have a relatively large thickness to have excellent passivation characteristics. For example, the thickness of the first intermediate layer 22 may be 1 nm to 2 nm, and the thickness of the second intermediate layer 24 may be 1 nm to 5 nm. If the thickness of the first and second intermediate layers 22 and 24 is less than 1 nm, it may be difficult for the first and second intermediate layers 22 and 24 to be uniformly formed as a whole, The effect may not be sufficient. If the thickness of the first intermediate layer 22 exceeds 2 nm, tunneling may not occur well. If the thickness of the second intermediate layer 24 exceeds 5 nm, the transfer characteristics of the carrier by the second intermediate layer 24 may be deteriorated. However, the present invention is not limited thereto, and the first and second intermediate layers 22 and 24 may have various thicknesses.

According to the present embodiment, considering the conductivity type of the dopant of the first and second conductivity type regions 20 and 30, the positions of the first and second conductivity type regions 20 and 30, and the like, The conductivity, the thickness, and the hydrogen concentration of the two-conductivity-type regions 20 and 30 are controlled. In addition, the first and second intermediate layers 22 and 24 connected to the first and second conductive regions 20 and 30 have different electrical conductivities, materials, thicknesses, and the like. As a result, the open circuit voltage, filling density, etc. of the solar cell 100 can be improved and the efficiency of the solar cell 100 can be improved.

In particular, the p-type first conductivity type region 20 includes an amorphous portion and a crystalline portion so that the deterioration phenomenon of the first conductivity type region 20 does not occur even at a temperature of 400 ° C or higher. That is, the temperature stability can be improved. Accordingly, a printing process using a paste can be applied in forming the first and second electrodes 42 and 44, and the first and second electrodes 42 and 44 can be fired at a relatively high temperature. As shown in Fig. 3, when the firing temperature in the firing process is increased, the resistivity of the first and second electrodes 42 and 44 can be lowered, and the time required for the firing process can be reduced. And the problem of deterioration of the characteristics of the p-type first conductivity type region 20 when attaching ribbons, wires, or the like to form the solar cell module can be prevented.

And the electric conductivity and doping efficiency of the first conductivity type region 20 can be improved. And the first intermediate layer 22 may include a tunneling layer including an insulating material to improve carrier transfer characteristics to the first conductivity type region 20. [

The second conductive type region 30 located on the front surface of the semiconductor substrate 110 is formed of an amorphous portion and has a higher hydrogen concentration and a thinner thickness than the first conductive type region 20, The optical loss, the photocurrent loss, and the like can be minimized.

In the above-described embodiment, the semiconductor substrate 110 has the first conductivity type, and the first conductive type region 20 located on the rear side constitutes the emitter region. The second conductive type region 30, As shown in FIG. However, the present invention is not limited thereto. The semiconductor substrate 110 may have a second conductive type region, and a first conductive type region 20 located on the rear side may form a rear electric field region, and a second conductive type region 30 ) May constitute the emitter region. Other variations are possible.

Hereinafter, a solar cell according to another embodiment of the present invention will be described in detail with reference to FIG. The same or similar portions as those described in the above-mentioned portions will not be described in detail, and the different portions will be described in detail. It is to be understood that both the foregoing description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Referring to FIG. 5, a rear reflective layer 26 having a refractive index lower than that of the first conductive type region 20 is disposed on a first conductive type region 20 located on the rear surface of the semiconductor substrate 110 . The rear reflective layer 26 may be formed entirely in a region other than the opening 26a formed in the portion corresponding to the metal electrode layer 422 of the first electrode 42. [ Accordingly, the light incident on the front surface of the semiconductor substrate 110 and reaching the rear surface of the semiconductor substrate 110 can be reflected and reused. Thus, the amount of light used can be increased. In one example, the backside reflective layer 26 may comprise a dielectric material such as silicon nitride, silicon carbide, silicon oxide, and the like. The backside reflective layer 26 may have a lower refractive index than the first conductive type region 20. For example, the refractive index of the back reflection layer 26 may be 1.3 to 3.5, and the refractive index of the first conductivity type region 20 may be 3.0 to 5.0. More specifically, when the back reflection layer 26 includes silicon nitride, the back reflection layer 26 may have a refractive index of 1.9 to 2.1. When the back reflection layer 26 includes silicon carbide, the back reflection layer 26 may have a refractive index of 1.7 to 3.5 depending on the carbon content, density, and the like. When the back reflection layer 26 includes silicon oxide, the back reflection layer 26 may have a refractive index of 1.3 to 1.8. However, the present invention is not limited thereto and various materials can be used.

In this embodiment, the first conductive type region 20 includes a crystalline portion and has excellent electrical conductivity. Therefore, the first electrode 42 may include only the metal electrode layer 422 without the transparent electrode layer 421 . In this case, the thickness of the first conductivity type region 20 may be 10 nm to 500 nm (particularly, 50 nm to 500 nm) in consideration of the resistance of the first conductivity type region 20. The resistance of the first conductivity type region 20 in this thickness range may have a low value.

In the present embodiment, it is illustrated that the rear reflective layer 26 is provided without the transparent electrode layer 421. However, the present invention is not limited thereto. Accordingly, the transparent electrode layer 421 and the rear reflective layer 26 may be formed on the first conductive type region 20 as shown in FIG. In this case, the transparent electrode layer 421 may contact the first conductive region 20 to improve the resistance characteristic, and the rear reflective layer 26 may be located on the transparent electrode layer 421. At this time, the back reflection layer 26 has a refractive index smaller than that of the transparent electrode layer 421, so that the reflection effect can be improved. Various other variations are possible.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described in detail with reference to FIGS. 7A to 7I. At this time, a method of manufacturing a solar cell according to the embodiment shown in FIG. 5 is shown as an example, but the present invention is not limited thereto. Hereinafter, the same or similar parts to those in the above description will be omitted from the detailed description and only different parts will be provided.

7A to 7I are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in FIG. 7A, a semiconductor substrate 110 composed of a base region 10 having a first or a second conductivity type dopant is prepared. At this time, the front surface and the rear surface of the semiconductor substrate 110 may be each mirror-polished to be a flat surface having a small surface roughness.

Next, as shown in FIG. 7B, the first intermediate layer 22 is formed on both surfaces of the semiconductor substrate 110. Next, as shown in FIG. At this time, the first intermediate layer 22 may be formed entirely on the front surface and the rear surface of the semiconductor substrate 110, respectively.

Here, the first intermediate layer 22 may be formed by, for example, thermal growth, vapor deposition (for example, chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like). In particular, the first intermediate layer 22 may be an amorphous silicon oxide layer having an amorphous structure formed by chemical vapor deposition. However, the present invention is not limited thereto, and the first intermediate layer 22 may be formed by various methods.

Next, as shown in FIG. 7C, a first conductive region 20 including an amorphous portion and a crystalline portion is formed on the rear surface of the semiconductor substrate 110.

For example, an amorphous semiconductor (e.g., amorphous silicon) layer is formed on the rear surface of the semiconductor substrate 110 and then a heat treatment is performed to form a first conductive type region 20 including crystalline silicon and amorphous silicon together can do. Various methods can be used for forming the amorphous semiconductor layer. For example, the amorphous semiconductor layer may be formed by a deposition method (for example, chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), or the like). Thereafter, the first conductive type region 20 including the amorphous portion and the crystalline portion can be formed by crystallizing the crystalline portion while partially leaving the amorphous portion by heat treatment.

As another example, the first conductivity type region 20 may be formed by forming a semiconductor layer on the rear surface of the semiconductor substrate 110 so as to have an amorphous portion and a crystalline portion. Various methods can be used for forming the semiconductor layer so as to have the amorphous portion and the crystalline portion. For example, a deposition method (for example, PECVD, APCVD, LPCVD) or the like can be used. At this time, an additional heat treatment may be performed so as to improve the fraction of the crystalline portion or to improve the stability of the first conductivity type region 20.

As an example, PECVD may be performed at a temperature of 100 ° C to 400 ° C, and APCVD or LPCVD may be performed at a temperature of 400 ° C to 900 ° C. When the heat treatment is performed, a general furnace or rapid thermal annealing (RTA) may be used. For example, the heat treatment may be performed at a temperature of 800 ° C to 900 ° C.

The first conductivity type dopant may be included in the first conductivity type region 20 by additionally supplying a dopant gas comprising the first conductivity type dopant during the deposition process. Alternatively, the first conductive type dopant may be included in the first conductive type region 20 by supplying a dopant gas or the like during the heat treatment process after the semiconductor layer or the first conductive type region 20 is formed. Alternatively, the first conductive type dopant may be included in the first conductive type region 20 by performing a separate doping process after the semiconductor layer is formed and heat-treated. The method of forming the first conductive type region 20 is not limited, and the first conductive type region 20 may be formed by various methods.

7D, a passivation layer 200 is formed on the first conductive region 20 located on the rear surface of the semiconductor substrate 110. [ The passivation layer 200 may include a variety of materials that protect the first conductive region 20 from being etched in a subsequent texturing process. For example, the protective layer 200 may include silicon nitride, silicon carbide, or the like which is insoluble in an alkali solution or the like.

Next, as shown in FIG. 7E, irregularities due to texturing can be formed on the entire surface of the semiconductor substrate 110. At this time, it is possible to form the irregularities by texturing by using an etching method capable of forming irregularities by texturing or by an additional process. For example, the entire surface of the semiconductor substrate 110 can be textured by using an alkali solution (for example, potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH)). However, the present invention is not limited thereto, and textured irregularities may be formed by dry texturing, reactive ion etching (RIE), or the like.

After the texturing, the protective layer 200 located on the rear side of the semiconductor substrate 110 can be removed. As a method of removing the protective layer 200, various methods can be used. For example, in consideration of the material of the protective layer 200, the protective layer 200 may be removed using an appropriate etching solution or paste.

Next, as shown in FIG. 7F, a second intermediate layer 24 and a second conductive type region 30 are formed on the entire surface of the semiconductor substrate 110.

The second intermediate layer 24 and the second conductivity type region 30 may be formed of an amorphous semiconductor (for example, amorphous silicon). At this time, the second intermediate layer 24 may exhibit intrinsic characteristics, and the second conductive type region 30 may include p-type or n-type including the second conductive type dopant. The second intermediate layer 24 and the second conductive type region 30 may be formed by an in-situ process which is performed continuously in the same equipment. More specifically, a raw material gas capable of forming an intrinsic amorphous semiconductor (for example, intrinsic amorphous silicon) is supplied to form a second intermediate layer 24, and a dopant gas containing a second conductivity type dopant in the same equipment The second conductivity type region 30 can be formed by additional implantation. The second intermediate layer 24 and the second conductive type region 30 may be formed as separate layers having specific boundaries. Alternatively, the second intermediate layer 24 and the second conductive type region 30 may be composed of a single layer that does not have a specific boundary and includes portions having different conductivity types. In this case, the portion having the intrinsic nature of the single layer can be regarded as the second intermediate layer 24, and the portion having the second conductivity type of the portion constituting the single layer is referred to as the second conductive type region 30 can see.

The second intermediate layer 24 and the second conductivity type region 30 may be formed by, for example, a vapor deposition method (for example, chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like). However, the present invention is not limited thereto, and the second intermediate layer 24 and the second conductivity type region 30 may be formed by various methods.

7G, the transparent electrode layer 441 of the second electrode 44 is formed on the second conductive type region 30 of the semiconductor substrate 110, and the transparent electrode layer 441 of the second electrode 44 is formed on the first conductive type region 20 A rear reflective layer 26 is formed.

The transparent electrode layer 441 of the second electrode 44 can be formed by, for example, a vapor deposition method (for example, chemical vapor deposition (PECVD)), a coating method, or the like. However, the present invention is not limited thereto, and the transparent electrode layer 441 of the second electrode 44 may be formed by various methods.

The rear reflective layer 26 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, spray coating, and the like. However, the present invention is not limited thereto, and the rear reflective layer 26 may be formed by various methods.

Since the solar cell 100 shown in FIG. 5 is illustrated, the transparent electrode layer 441 of the second electrode 44 is formed on the front surface and the rear surface reflection layer 26 is formed on the rear surface. The transparent electrode layer 421 of the first electrode 42 is formed together with the transparent electrode layer 441 of the second electrode 44 to form the rear reflective layer 26 It may not. Then, the solar cell 100 as shown in FIG. 1 can be manufactured.

7H, the metal electrode layer 442 of the paste-like second electrode 44 is placed on the transparent electrode layer 441 of the second electrode 44, and the metal electrode layer 442 of the paste- The metal electrode layer 422 of the first electrode 42 is positioned. At this time, the first and second electrodes 42 and 44 may be applied by printing.

 Then, as shown in Fig. 7I, the first and second electrodes 42 and 44 are fired. At this time, the metal electrode layer 442 of the second electrode 44 is connected to the first conductive type region 20 through the rear reflective layer 26 by fire through, laser firing contact, or the like . In this case, it is not necessary to add a step for forming the opening 26a separately in the rear reflection layer 26. [

At this time, the first and second electrodes 42 and 44 can be fired at a temperature of 350 to 400 ° C. Accordingly, the first and second electrodes 42 and 44 can be fired at a relatively high temperature, so that the first and second electrodes 42 and 44 can have a low resistivity and the firing time can be reduced.

However, the present invention is not limited to this. The metal electrode layers 422 and 442 of the first and second electrodes 42 and 44 may be formed by plating, vapor deposition, or the like after the opening 26a is formed in the rear reflective layer 26 .

According to this embodiment, the solar cell 100 having the above-described structure can be manufactured by a simple method.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
110: semiconductor substrate
22: First intermediate layer
24: second intermediate layer
20: first conductivity type region
30: second conductivity type region
42: first electrode
44: Second electrode

Claims (20)

A semiconductor substrate;
A first intermediate layer located on one surface of the semiconductor substrate;
A second intermediate layer located on the other surface of the semiconductor substrate;
A first conductive type region located above the first intermediate layer;
A second conductive type region located above the second intermediate layer;
A first electrode coupled to the first conductive type region; And
And a second electrode connected to the second conductivity type region
/ RTI >
Wherein the crystallinity of the first conductivity type region is larger than the crystallinity of the second conductivity type region. The method according to claim 1,
The first conductivity type region is a p-type region,
And the second conductivity type region is an n-type region. 3. The method according to claim 1 or 2,
Wherein the first conductivity type region comprises a crystalline portion and an amorphous portion,
Wherein the second conductivity type region comprises an amorphous portion. The method of claim 3,
Wherein the crystalline portion in the first conductivity type region comprises the same or more than the amorphous portion. 3. The method according to claim 1 or 2,
And the crystallinity of the first conductivity type region is 50% to 90%. 3. The method according to claim 1 or 2,
Wherein a hydrogen concentration of the first conductivity type region is smaller than a hydrogen concentration of the second conductivity type region. 3. The method according to claim 1 or 2,
Wherein the first electrode comprises a metal electrode layer,
Wherein the second electrode includes a transparent electrode layer entirely disposed on the second conductive type region, and a metal electrode layer formed with a pattern on the transparent electrode layer. 8. The method of claim 7,
Wherein the first electrode further comprises a transparent electrode layer located between the first conductive type region and the metal electrode layer and located entirely over the first conductive type region. 3. The method according to claim 1 or 2,
Wherein a thickness of the first conductive type region is larger than a thickness of the second conductive type region. 10. The method of claim 9,
Wherein the thickness of the first conductivity type region is 10 nm to 500 nm,
And the thickness of the second conductivity type region is 5 nm to 10 nm. The method according to claim 1,
Wherein the first intermediate layer and the second intermediate layer are different in thickness, material, and electrical conductivity from each other. 3. The method according to claim 1 or 2,
Wherein the thickness of the first intermediate layer is equal to or less than the thickness of the second intermediate layer. 12. The method of claim 11,
Wherein the thickness of the first intermediate layer is 1 nm to 2 nm,
And the thickness of the second intermediate layer is 1 nm to 5 nm. 3. The method according to claim 1 or 2,
Wherein the first intermediate layer comprises an oxide,
Wherein the second intermediate layer comprises intrinsic amorphous silicon. 3. The method according to claim 1 or 2,
The first conductivity type region is located on the rear surface of the semiconductor substrate,
And the second conductivity type region is located on a front surface of the semiconductor substrate. 16. The method of claim 15,
Wherein the semiconductor substrate comprises n-type,
Wherein the first conductive type region located on the rear surface of the semiconductor substrate is an emitter region,
Wherein the second conductive type region located on the front surface of the semiconductor substrate is a front electric field region. 3. The method according to claim 1 or 2,
A concavo-convex structure formed by texturing is formed on the front surface of the semiconductor substrate,
Wherein a back surface of the semiconductor substrate has a surface roughness smaller than that of the front surface of the semiconductor substrate. 3. The method according to claim 1 or 2,
The first conductivity type region is located on the rear surface of the semiconductor substrate,
The second conductivity type region is located on the front surface of the semiconductor substrate,
And a backside reflective layer having a refractive index smaller than that of the first conductive type region on the first conductive type region,
Wherein the rear reflective layer comprises silicon nitride, silicon carbide, or silicon oxide. 3. The method according to claim 1 or 2,
Wherein the first conductive type region comprises Si as a semiconductor material,
Wherein the second conductivity type region comprises Si, SiCx (x? 0.1), or SiOy (y? 0.2) as a semiconductor material. 3. The method according to claim 1 or 2,
Wherein the semiconductor substrate includes a first conductive type dopant or a second conductive type dopant in a doping concentration lower than that of the first conductive type region or the second conductive type region.

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