KR20160092535A - Organic light emitting display device - Google Patents

Abstract

An embodiment of the present invention provides an organic light emitting display device capable of making the brightness of picture elements uniform by compensating a threshold voltage of a driving transistor. The organic light emitting display device according to the embodiment of the present invention includes a display panel with picture elements connected to scan lines, data lines, and driving voltage lines; a scan driving unit providing scan signals to the scan lines; a data driving unit providing data voltages to the data lines; and a driving voltage supplying unit supplying driving voltages swing between a first level voltage and a second level voltage lower than the first level voltage to the driving voltage lines. The display panel is divided into q blocks (The q is a positive integer equal to two or higher). Each of the q blocks includes the picture elements connected to the first to p^th driving voltage lines (The p is a positive integer equal to two or higher). The durations for supplying the driving voltage equal to the second level voltage to each of the q blocks are different from each other depending on each of the first to the q^th driving voltage lines.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

An embodiment of the present invention relates to an organic light emitting display.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

Of these, the organic light emitting display device can be driven at a low voltage, is thin, has excellent viewing angle, and has a high response speed. The organic light emitting display includes a display panel having data lines, scan lines, a plurality of pixels formed at intersections of the data lines and the scan lines, a scan driver for supplying scan signals to the scan lines, And a data driver for supplying data voltages. Each of the pixels includes an organic light emitting diode, a driving transistor for controlling the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, And supplies a voltage to the gate electrode of the driving transistor.

However, there is a problem that the threshold voltage of the driving transistor varies from pixel to pixel due to the non-uniformity of the manufacturing process. In this case, even if the same data voltage is applied to each of the pixels, the luminance at which the organic light emitting diode emits light is different for each pixel due to the threshold voltage difference of the driving transistor between the pixels. To solve this problem, a compensation method for compensating the threshold voltage of the driving transistor has been proposed.

An embodiment of the present invention provides an organic light emitting display in which luminance of pixels can be made uniform by compensating a threshold voltage of a driving transistor.

An organic light emitting display according to an embodiment of the present invention includes a display panel having pixels connected to scan lines, data lines, and driving voltage lines, a scan driver for supplying scan signals to the scan lines, And a driving voltage supply unit for supplying driving voltage lines swinging between a first level voltage and a second level voltage lower than the first level voltage to the driving voltage lines. The display panel is divided into q (q is a positive integer equal to or greater than two) blocks, and each of the q blocks is divided into a plurality of pixels, each of which is connected to one of the first to p (p is a positive integer of 2 or more) . The length of a period during which the driving voltage of the second level voltage is supplied to each of the q blocks is different from each other for each of the first to p driving voltage lines.

The embodiment of the present invention senses the threshold voltage of the driving transistor to the source electrode of the driving transistor for a predetermined period. As a result, the embodiment of the present invention can emit the organic light emitting diode according to the current of the driving transistor whose threshold voltage is compensated.

In addition, the embodiment of the present invention divides the display panel into a plurality of blocks, sequentially drives the blocks, and drives the blocks sequentially. As a result, the embodiment of the present invention can simultaneously perform threshold voltage sensing of the driving transistor for each block, and sequentially supply the data voltages to the pixels. Therefore, the embodiment of the present invention has an advantage that a data voltage supply period can be sufficiently secured even when high-speed driving is performed at 120 Hz or more.

Further, the embodiment of the present invention supplies the data voltage to the gate electrode of the driving transistor and raises the voltage (Vs) of the source electrode by "? &Quot;. At this time, "? &Quot;, which is an increase amount of the voltage (Vs) of the source electrode, varies depending on the electron mobility of the driving transistor. As a result, in the embodiment of the present invention, the voltage difference between the gate electrode and the source electrode can be adjusted according to the electron mobility of the driving transistor, so that the electron mobility of the driving transistor can be compensated.

In addition, the embodiment of the present invention supplies the driving voltage of the second level voltage to the driving voltage line during the period in which the driving transistor is turned off. As a result, the embodiment of the present invention can minimize the source voltage rise of the driving transistor due to the leakage current of the driving transistor.

Furthermore, embodiments of the present invention supply a voltage control signal having a gate off voltage for a period of turning off the driving transistor. As a result, since the connection between the drain electrode of the driving transistor and the driving voltage line can be cut off during the period in which the driving transistor is turned off, the rise of the source voltage of the driving transistor due to the leakage current of the driving transistor can be minimized .

1 is a block diagram showing an organic light emitting display according to an embodiment of the present invention;
FIG. 2 is an exemplary view showing the blocks of the display panel of FIG. 1; FIG.
3 is a circuit diagram showing an example of the pixel of FIG.
FIG. 4 is a waveform diagram showing an example of scan signals, initialization signals, and driving voltages supplied to the display panel of FIG. 2. FIG.
5 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data voltage, a k-th driving voltage, and a gate voltage and a source voltage of the driving transistor.
6 is a flow chart showing a method of driving a pixel during the first to sixth periods.
7A to 7F are circuit diagrams showing the operation of the pixel of FIG. 3 during the first to sixth periods.
8 is a block diagram illustrating an OLED display according to another embodiment of the present invention.
9 is an exemplary view showing the blocks of the display panel of Fig.
10 is a circuit diagram showing another example of the pixel of Fig.
FIG. 11 is a waveform diagram showing an example of scan signals, initialization signals, and voltage control signals supplied to the display panel of FIG. 9; FIG.
12 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data voltage, a k-th voltage control signal, and a gate voltage and a source voltage of the driving transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

1 is a block diagram illustrating an organic light emitting display according to an exemplary embodiment of the present invention. Referring to FIG. 1, an OLED display includes a display panel 10, a data driver 20, a scan driver 30, an initialization driver 40, a driving voltage supplier 50, A timing control section 60, and a reference voltage supply section 70.

Data lines (D1 to Dm, m is a positive integer of 2 or more), scan lines (S1 to Sn, n are positive integers of 2 or more), initialization lines (SEN1 to SENn), and Driving voltage lines VDL1 to VDLn are provided. The data lines D1 to Dm may be formed to cross the scan lines S1 to Sn, the initialization lines SEN1 to SENn, and the drive voltage lines VDL1 to VDLn. The scan lines S1 to Sn, the initialization lines SEN1 to SENn, and the drive voltage lines VDL1 to VDLn may be formed in parallel with each other.

The pixels P connected to the data lines D1 to Dm, the scan lines S1 to Sn, the initialization lines SEN1 to SENn and the drive voltage lines VDL1 to VDLn are connected to the display panel 10, . Each of the pixels P includes one of the data lines D1 to Dm, one of the scan lines S1 to Sn, one of the initialization lines SEN1 to SENn, and one of the drive voltage lines VDL1 To VDLn. Each of the pixels P includes a driving transistor, first and second transistors controlled by a scan signal of the scan line and an initialization signal of the initialization line, an organic light emitting diode, and a capacitor ). The pixel P will be described later in detail with reference to FIG.

The display panel 10 may be divided into a plurality of blocks as shown in FIG. 2, for convenience of explanation, the scan lines S1 to S3p, the initialization lines SEN1 to SEN3p, the drive voltage lines VDL1 to VDL3p, the pixels P, (30), the initialization driver (40), and the drive voltage supplier (50). In FIG. 2, the display panel 10 is divided into three blocks BL1, BL2, and BL3 for convenience of explanation. However, the present invention is not limited thereto.

Referring to FIG. 2, each of the blocks BL1, BL2, and BL3 may include the same number of pixels. Specifically, when the display panel 10 is divided into q (q is a positive integer of 2 or more) blocks, each of q blocks is connected to p (p is a positive integer of 2 or more) scan lines And may include pixels (P). Here, "p" may be a value obtained by dividing "n" (the total number of scan lines) by "q" (the number of blocks).

For example, when the display panel 10 is divided into three blocks BL1, BL2, and BL3 as shown in FIG. 2, each of the blocks BL1, BL2, and BL3 includes p scan lines Or driving voltage lines). As shown in FIG. 2, the first block BL1 includes pixels P connected to the first through pth scan lines S1 through Sp, and the second block BL2 includes p + And the pixels P connected to the lines Sp + 1 to S2p and the third block BL3 includes pixels P connected to the second p + 1 th to the third p scan lines S2p + 1 to S3p ). On the other hand, the pixels P connected to the p scan lines are substantially the same as the pixels P connected to the p drive voltage lines, and the pixels P connected to the p scan lines are p And are substantially the same as the pixels P connected to the initialization lines.

The data driver 20 includes at least one source driver IC (hereinafter referred to as "IC"). The source drive IC is connected to the data lines D1 to Dm to supply the data voltages. Specifically, the source drive IC receives the digital video data (DATA) and the source timing control signal (DCS) from the timing control unit 60. The source driver IC converts the digital video data (DATA) into data voltages according to the source timing control signal (DCS) and supplies the data voltages to the data lines (D1 to Dm). In addition, the source drive IC may supply a compensation voltage and a turn-off voltage to the data lines D1 to Dm in addition to the data voltages. A detailed description of the compensation voltage, the turn-off voltage, and the data voltage supply of the source drive IC will be given later with reference to FIG.

The scan driver 30 is connected to the scan lines S1 to Sn to supply scan signals. The scan driver 30 supplies scan signals to the scan lines S1 to Sn in accordance with a scan timing control signal SCS input from the timing controller 60. [ The scan signals swing between the gate-on voltage and the gate-off voltage as shown in Figs. A detailed description of the supply of the scan signal to the scan driver 30 will be given later with reference to FIGS. 4 and 5. FIG.

The initialization driver 40 is connected to the initialization lines SEN1 to SENn to supply initialization signals. Specifically, the initialization driver 40 supplies initialization signals to the initialization lines SEN1 to SENn according to the initialization control signal SENCS input from the timing controller 60. [ The initialization signals swing between the gate-on voltage and the gate-off voltage as shown in Figs. The initialization signal supply of the initialization driver 40 will be described later in detail with reference to FIGS. 4 and 5. FIG.

The driving voltage supply unit 50 is connected to driving voltage lines VDL1 to VDLn to supply driving voltages. The driving voltage supplier 50 supplies driving voltages to the driving voltage lines VDL1 to VDLn in accordance with the voltage timing control signal VDDCS input to the timing controller 60. [ The driving voltages swing between the first level voltage and the second level voltage as shown in Figs. 4 and 5. The driving voltage supply of the driving voltage supply unit 50 will be described later in detail with reference to FIGS. 4 and 5. FIG.

The timing controller 60 receives digital video data DATA from outside. The timing controller 60 generates timing control signals for controlling the operation timings of the data driver 20, the scan driver 30, the initialization driver 40, and the driving voltage supplier 50. The timing control signals include a data timing control signal DCS for controlling the operation timing of the data driver 20, a scan timing control signal SCS for controlling the operation timing of the scan driver 30, An initialization timing control signal SENCS for controlling the operation timing, and a voltage timing control signal VDDCS for controlling the operation timing of the drive voltage supplier 50. [

The timing controller 60 outputs the digital video data DATA and the data timing control signal DCS to the data driver 20. The timing controller 60 outputs the scan timing control signal SCS to the scan driver 30. The timing controller 60 outputs the initialization timing control signal SENCS to the initialization driver 40. The timing control unit 60 outputs the voltage timing control signal VDDCS to the driving voltage supply unit 50.

The reference voltage supply unit 70 is connected to a reference voltage line VRL connected to the pixels P to supply a DC reference voltage.

3 is a circuit diagram showing an example of the pixel of FIG. In FIG. 3, for convenience of explanation, the scan line Sk, the kth initializing line SENk, the k th driving voltage line VDLk, the jth scanning line Sk, (j is a positive integer satisfying 1? j? m) data line Dj, and a pixel P connected to the reference voltage line VRL. Referring to FIG. 3, the pixel P includes an organic light emitting diode OLED and a pixel driver PD for supplying a driving current to the organic light emitting diode OLED. The pixel driver PD may include a driving transistor DT, first and second transistors ST1 and ST2, and a capacitor C.

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT and the cathode electrode is connected to the low potential voltage line EVSSL to which a low potential voltage lower than the driving voltage of the first level voltage is supplied .

The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

The driving transistor DT is connected to the k th driving voltage line VDLk and the organic light emitting diode OLED. The driving transistor DT controls the current flowing from the k th driving voltage line VDLk to the organic light emitting diode OLED according to the voltage of the gate electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1, the source electrode of the driving transistor DT is connected to the anode electrode of the organic light emitting diode OLED, k drive voltage line VDLk.

The first transistor ST1 is turned on when the kth scan signal of the gate-on voltage is supplied to the kth scan line Sk so that the voltage of the jth data line Dj is applied to the gate electrode of the driving transistor DT Supply. The gate electrode of the first transistor T1 is connected to the kth scan line Sk and the first electrode thereof is connected to the gate electrode of the driving transistor DT and the second electrode thereof is connected to the jth data line Dj .

The second transistor ST2 is turned on when the k-th initialization signal of the gate-on voltage is supplied to the k-th initialization line SENk, so that the reference voltage of the reference voltage line VRL is applied to the source electrode of the driving transistor DT Supply. The gate electrode of the second transistor ST2 is connected to the kth initialization line SENk and the first electrode thereof is connected to the reference voltage line VRL and the second electrode thereof is connected to the source electrode of the driving transistor DT .

The capacitor C is provided between the gate electrode and the source electrode of the driving transistor DT. One electrode of the capacitor C may be connected to the gate electrode of the driving transistor DT and the other electrode may be connected to the source electrode of the driving transistor DT. The capacitor C maintains a constant voltage difference between the gate electrode and the source electrode of the driving transistor DT.

In FIG. 3, the first electrode of the first and second transistors ST1 and ST2 may be a source electrode or a drain electrode, and the second electrode may be a different electrode from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

3, the driving transistor DT and the first and second transistors ST1 and ST2 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, it should be noted that the driving transistor DT and the first and second transistors ST1 and ST2 are not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the waveform diagrams of FIGS. 4 and 5 may be modified as appropriate to the characteristics of the P- .

As described above, the pixel P according to the embodiment of the present invention includes the first transistor ST1 connected to the gate electrode of the jth data line Dj and the driving transistor DT, And a second transistor ST2 connected to the source electrode of the driving transistor DT. As a result, in the embodiment of the present invention, by adjusting the turn-on of the first and second transistors ST1 and ST2 and the voltage supplied to the jth data line Dj, the threshold voltage of the driving transistor DT Sensing can be performed. A detailed description of the threshold voltage compensation of the driving transistor DT of the pixel P shown in Fig. 3 will be described later in conjunction with Fig. 5, Fig. 6 and Figs. 7A to 7D.

FIG. 4 is a waveform diagram showing an example of scan signals, initialization signals, and driving voltages supplied to the display panel of FIG. 2. Referring to FIG. 4, the first through third p scan signals SCAN1 through SCAN3p, the first through third p drive voltage lines VDL1 through VDL3p, and the first through third p scan lines S1 through S3p shown in FIG. And first to third p initializing signals SENS1 to SENS3p supplied to the first to third p initializing lines S1 to S3p are supplied to the first to third p driving voltages VDD1 to VDD3p,

Referring to FIG. 4, one frame period includes q sub frame periods. For example, when the display panel 10 is divided into three blocks BL1, BL2, and BL3 as shown in FIG. 2, one frame period includes three subframe periods SF1, SF2, and SF3 .

Each of the q subframe periods includes a threshold voltage sensing period ST and a data voltage supply period DP as shown in FIG. The threshold voltage sensing period ST is a period for sensing the threshold voltage of the driving transistor DT of each of the pixels P in the block. The data voltage supply period DP is a period of supplying data voltages to the pixels P of the block. The threshold voltage sensing period ST indicates the first to third periods t1 to t3 in FIG. 5 and the data voltage supply period DP is the fourth to sixth periods t4 to t6 in FIG. . A detailed description of the first to sixth periods t1 to t6 will be given later with reference to FIG.

The scan driver 30 and the initialization driver 40 apply the scan signals to the scan lines S1 to Sp connected to the pixels P of the first block BL1 and the initialization lines SEN1 to SENp, The initialization signals SENS1 to SENSp of the scan-on signals SCAN1 to SCANp and the gate-on voltage Von of the gate-on voltage Von are supplied at the same time during the threshold voltage sensing period SP of the sub- And sequentially supplies the scan signals SCAN1 to SCANp of the gate-on voltage Von during the supply period DP. As a result, the threshold voltages of the driving transistors DT of the pixels P of the first block BL1 are sensed during the threshold voltage sensing period ST of the first sub frame period SF1, The pixels P of the first block BL1 emit light because the data voltages are supplied to the pixels P of the first block BL1 during the period DP.

The scan driver 30 and the initialization driver 40 are connected to the scan lines Sp + 1 to S2p and the initialization lines SENp + 1 to SEN2p connected to the pixels P of the second block BL2. The initialization signals SENSp + 1 to SENS2p (SCANp + 1 to SCAN2p) of the gate-on voltage Von and the gate-on voltage Von during the threshold voltage sensing period SP of the sub- And sequentially supplies the scan signals SCANp + 1 to SCAN2p of the gate-on voltage Von during the data voltage supply period DP. As a result, the threshold voltages of the driving transistors DT of the pixels P of the second block BL2 are sensed during the threshold voltage sensing period ST of the second sub frame period SF2, The pixels P of the second block BL2 emit light because the data voltages are supplied to the pixels P of the second block BL2 during the period DP.

The scan driver 30 and the initialization driver 40 are connected to the scan lines S2p + 1 to S3p and the initialization lines SEN2p + 1 to SEN3p connected to the pixels P of the third block BL3. The scan signals SCAN2p + 1 to SCAN3p of the gate-on voltage Von and the initialization signals SENS2p + 1 to SENS3p of the gate-on voltage Von during the threshold voltage sensing period SP of the sub- And simultaneously supplies the scan signals SCAN2p + 1 to SCAN3p of the gate-on voltage Von during the data voltage supply period DP. As a result, the threshold voltages of the driving transistors DT of the pixels P of the third block BL3 are sensed during the threshold voltage sensing period ST of the third sub-frame period SF3, The pixels P of the third block BL3 emit light because the data voltages are supplied to the pixels P of the third block BL3 during the period DP.

As described above, according to the embodiment of the present invention, the display panel 10 is divided into the plurality of blocks BL1, BL2, and BL3, the blocks BL1, BL2, and BL3 are sequentially driven, It works by itself. As a result, the embodiment of the present invention can simultaneously perform threshold voltage sensing of the driving transistor DT for each block, and sequentially supply the data voltages to the pixels P. Therefore, the embodiment of the present invention has an advantage that the data voltage supply period DP can be sufficiently secured even when high-speed driving is performed at 120 Hz or more.

On the other hand, a period between the periods in which the scan signals of the gate-on voltage Von are supplied during the threshold voltage sensing period SP and the data voltage supply period DP in the sub-frame periods SF1, SF2, and SF3, And a voltage holding period t4 for holding the gate-source voltage of the data signal DT. Since the scan signals of the gate-on voltage Von are sequentially supplied to the scan lines during the data voltage supply period DP, the length of the voltage sustain period t4 is shorter than the length of the first scan line S1 to the p- (Sp + 1) to the second p scan line (S2p), and the second p + 1 scan line (S2p + 1) to the third p scan line (S3p) .

Further, the embodiment of the present invention supplies the driving voltages to the second level voltage V2 in order to minimize the voltage rise of the source electrode of the driving transistor DT during the voltage sustain period t4. Thus, the length of the period during which the driving voltage of the second level voltage is supplied differs from one driving voltage line to another. That is, the length of the period during which the driving voltage of the second level voltage V2 is supplied becomes longer from the first driving voltage line VDL1 to the p driving voltage line VDLp as the p + 1 driving voltage line VDLp + 1 1 to the second p drive voltage line VDL2p from the second p + 1 drive voltage line VDLp + 1 to the third p drive voltage line VDL2p.

In order to supply the driving voltages to the second level voltage V2 during the voltage sustain period t4, since the voltage sustain period t4 varies depending on the scan lines, the scan lines S1 to Sn, The sustain electrodes SEN1 to SENn and the driving voltage lines VDL1 to VDLn are preferably formed in parallel with each other.

5 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data voltage, a k-th driving voltage, and a gate voltage and a source voltage of the driving transistor. 5 shows the k th driving voltage VDDk supplied to the k th driving voltage line VDLk connected to the pixel P of Fig. 3, the k th scanning signal SCANk supplied to the k th scanning line Sk, A voltage DVj supplied to the jth data line Dj, a gate voltage Vg and a source voltage Vs of the driving transistor DT supplied to the kth initializing line SENk, .

Referring to FIG. 5, a subframe period may be divided into first through sixth periods t1 through t6. The first period t1 is a period in which the source electrode of the driving transistor DT is initialized to the reference voltage Vref and the gate electrode is initialized to the compensation voltage Vcomp. The second period t2 is a period for sensing the threshold voltage of the driving transistor DT. The third period t3 is a period for supplying the turn-off voltage Vt to the gate electrode of the driving transistor DT. The fourth period t4 is a period for maintaining the gate-source voltage Vgs of the driving transistor DT. The fifth period t5 is a period for supplying the data voltage Vdata to the gate electrode of the driving transistor DT. The sixth period t6 is a period during which the organic light emitting diode OLED emits light according to the current of the driving transistor DT.

The second period t2 is preferably longer than the first, third and fifth periods t1, t3 and t5, respectively. Since the scan signals of the gate-on voltage Von are sequentially supplied to the scan lines during the data voltage supply period DP of each of the sub-frame periods SF1, SF2 and SF3 as shown in FIG. 4, The length of the second p + 1 scan line Sp from the first scan line S1 to the pth scan line Sp, and from the p + 1 scan line Sp + 1 to the second p scan line S2p, (S2p + 1) to the third p scan line (S3p).

The data driver 20 supplies the compensation voltage Vcomp to the j data line Dj during the first and second periods t1 and t2. The compensation voltage Vcomp is a voltage for compensating the threshold voltage of the driving transistor DT. When the driving transistor DT is formed of an N-type MOSFET, the compensation voltage Vcomp may be a voltage higher than the reference voltage Vref as shown in FIG.

The data driver 20 supplies the turn-off voltage Vt to the j-th data line Dj during the third and fourth periods t3 and t4. The turn-off voltage Vt is a voltage capable of turning off the driving transistor DT. The turn-off voltage Vt may be lower than the compensation voltage Vcomp when the driving transistor DT is formed of the N-type MOSFET and the turn-off voltage Vt may be lower than the reference voltage Vref ). ≪ / RTI > Specifically, during the third period t3, the turn-off voltage Vt is applied to turn off the driving transistor DT during the third and fourth periods t3 and t4, Must be set lower than the threshold voltage of the driving transistor DT.

The data driver 20 supplies the data voltage Vdata to the j-th data line Dj during the fifth period t5. The data voltage Vdata is a voltage supplied to the gate electrode of the driving transistor DT to emit the organic light emitting diode OLED at a predetermined luminance. For example, when the digital video data DATA supplied to the data driver 20 is 8 bits, the data voltage Vdata may be supplied in any one of 256 voltages. When the driving transistor DT is formed of an N-type MOSFET, the data voltage Vdata may be higher than the compensation voltage Vcomp as shown in FIG.

5, the scan driver 30 applies the k-th scan signal SCANk of the gate-on voltage Von to the k-th scan line Sk during the first to third and fifth periods t1 to t3 and t5, . The scan driver 30 supplies the kth scan signal SCANk of the gate off voltage Voff to the kth scan line Sk during the fourth and sixth periods t4 and t6.

The initialization driver 40 supplies the k-th initialization signal SENSk of the gate-on voltage Von to the k-th initialization line SENk during the first period t1 as shown in Fig. The initialization driver 40 supplies the k-th initialization signal SENSk of the gate-off voltage Voff to the k-th initialization line SENk during the second to sixth periods t2 to t6.

The driving voltage supplier 50 supplies the kth driving voltage line VDLk of the first level voltage during the first, second, fifth and sixth periods t1, t2, t5 and t6, And supplies the driving voltage VDDk. The driving voltage supplier 50 supplies the k th driving voltage VDDk of the first level voltage to the k th driving voltage line VDLk during the third and fourth periods t3 and t4.

6 is a flowchart showing a method of driving pixels during the first to sixth periods. 7A to 7F are circuit diagrams showing the operation of the pixel of FIG. 3 during the first to sixth periods.

The compensation method for compensating the threshold voltage of the driving transistor DT of the pixel P is classified into an internal compensation method and an external compensation method. The internal compensation method is a method of sensing and compensating the threshold voltage of the driving transistor DT in the pixel P. The external compensation method supplies a preset voltage to the pixel P and senses the voltage of the source electrode of the driving transistor DT of the pixel P through a predetermined sensing line according to the preset voltage, And compensates digital video data to be supplied to the pixel P using a voltage. The embodiment of the present invention compensates the threshold voltage of the driving transistor DT by an internal compensation method.

Hereinafter, a driving method of the pixel P according to an embodiment of the present invention will be described in detail with reference to FIGS. 5, 6, and 7A to 7F. The transistors turned off in Figures 7A-7F are shown in phantom.

First, during the first period t1, the source electrode of the driving transistor DT is initialized to the reference voltage Vref, and the gate electrode is initialized to the compensation voltage Vcomp.

During the first period t1, the kth scan signal SCANk having the gate-on voltage Von is supplied to the kth scan line Sk. During the first period t1, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-on voltage Von. During the first period t1, the compensation voltage Vcomp is supplied to the j-th data line Dj. During the first period t1, the k th driving voltage line VDLk is supplied with the k th driving voltage VDDk of the first level voltage V1.

During the first period t1, the first transistor ST1 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the compensation voltage Vcomp of the jth data line Dj is supplied to the gate electrode of the driving transistor DT as shown in Figs. 5 and 7A. During the first period t1, the second transistor ST2 is turned on by the k-th initialization signal SENk having the gate-on voltage Von. Due to the turn-on of the second transistor ST2, the reference voltage Vref of the reference voltage line VRL is supplied to the source electrode of the driving transistor DT as shown in Figs. 5 and 7A. (S101 in Fig. 6)

Secondly, the threshold voltage of the driving transistor DT is sensed during the second period t2.

During the second period t2, the kth scan signal SCANk having the gate-on voltage Von is supplied to the kth scan line Sk. During the second period t2, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. And the compensation voltage Vcomp is supplied to the j-th data line Dj during the second period t2. During the second period t2, the k th driving voltage line VDLk is supplied with the k th driving voltage VDDk of the first level voltage V1.

During the second period t2, the first transistor ST1 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the compensation voltage Vcomp of the jth data line Dj is supplied to the gate electrode of the driving transistor DT as shown in Figs. 5 and 7B. During the second period t2, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

Since the voltage difference (Vgs = Vcomp-Vref) between the gate electrode and the source electrode of the driving transistor DT is larger than the threshold voltage Vth of the driving transistor DT during the second period t2, DT flows a current until the voltage difference Vgs between the gate electrode and the source electrode reaches the threshold voltage Vth. As a result, the source voltage Vs of the driving transistor DT rises to "Vcomp-Vth" as shown in Figs. 5 and 7B. Therefore, the threshold voltage of the driving transistor DT is sensed to the source electrode of the driving transistor DT during the second period t2. (S102 in Fig. 6)

Thirdly, the turn-off voltage Vt is supplied to the gate electrode of the driving transistor DT during the third period t3.

During the third period t3, the kth scan line SC is supplied with the kth scan signal SCANk having the gate-on voltage Von. During the third period t3, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the third period t3, the turn-off voltage Vt is supplied to the j-th data line Dj. During the third period t3, the k th driving voltage line VDLk is supplied with the k th driving voltage VDDk of the second level voltage V2.

During the third period t3, the first transistor ST1 is turned on by the kth scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the turn-off voltage Vt is supplied to the gate electrode of the driving transistor DT as shown in Figs. 5 and 7C. During the third period t3, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

5 and 7C, the gate voltage Vg of the driving transistor DT is the turn-off voltage Vt during the third period t3, and the driving transistor DT is driven by the capacitor C, The source voltage Vs is lowered to "Vcomp-Vth-beta ". At this time,? Can be defined as shown in Equation (1).

CCc is the capacitance of the capacitor C and CCcp is the capacitance of the parasitic capacitor formed in the anode electrode of the organic light emitting diode OLED. ≪ / RTI > (S103 in Fig. 6)

Fourth, the voltage Vs of the source electrode of the driving transistor DT is maintained during the fourth period t4.

During the fourth period t4, the kth scan signal SCANk having the gate off voltage Voff is supplied to the kth scan line Sk. During the fourth period t4, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. The turn-off voltage Vt is supplied to the j-th data line Dj during the fourth period t4. During the fourth period t4, the k th driving voltage line VDLk is supplied with the k th driving voltage VDDk of the second level voltage V2.

During the fourth period t4, the first transistor ST1 is turned off by the kth scan signal SCANk having the gate-off voltage Voff. During the fourth period t4, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

The voltage Vg of the gate electrode of the driving transistor DT during the fourth period t4 maintains the turn-off voltage Vt supplied during the third period t3 as shown in Figs. 5 and 7D. Therefore, during the fourth period t4, the driving transistor DT remains in the turned-off state following the third period t3.

5, since the gate-source voltage Vgs of the driving transistor DT is smaller than the threshold voltage of the driving transistor DT during the third and fourth periods t3 and t4, Is turned off. However, even if the driving transistor DT is turned off, a leakage current can flow finely. As a result, the source voltage Vs of the driving transistor DT can be slightly increased. 4, the length of the fourth period t4 may vary depending on which scan line the pixel P is connected to, so that the source voltage Vs of the driving transistor DT is set to the pixel P, May be different depending on which scan line is connected.

Therefore, the embodiment of the present invention is applicable to the kth driving voltage line VDLk during the third and fourth periods t3 and t4, which turn off the driving transistor DT, And supplies the driving voltage VDDk. As a result, the embodiment of the present invention can minimize the rise of the source voltage Vs of the driving transistor DT due to the leakage current of the driving transistor DT. On the other hand, the smaller the difference between the second level voltage V2 and the source voltage Vs of the driving transistor DT during the third and fourth periods t3 and t4, the smaller the leakage current of the driving transistor DT . Therefore, it is preferable that the second level voltage V2 is set so as to minimize the difference from the source voltage Vs of the driving transistor DT during the third and fourth periods t3 and t4. (S104 in Fig. 6)

Fifth, the data voltage is supplied to the gate electrode of the driving transistor DT during the fifth period t5.

During the fifth period t5, the kth scan signal SCANk having the gate-on voltage Von is supplied to the kth scan line Sk. During the fifth period t5, the k-th initialization line SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the fifth period (t5), the data voltage (Vdata) is supplied to the j-th data line (Dj). During the fifth period t5, the k th driving voltage line VDLk is supplied with the k th driving voltage VDDk of the first level voltage V1.

During the fifth period t5, the first transistor ST1 is turned on by the k-th scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the data voltage Vdata is supplied to the gate electrode of the driving transistor DT. During the fifth period t5, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

Meanwhile, the embodiment of the present invention can compensate for the electron mobility () of the driving transistor DT during the fifth period (t5). During the fifth period t5, the driving transistor DT has a voltage difference (Vgs = Vdata- (Vcomp-Vth-beta)) between the gate electrode and the source electrode is larger than the threshold voltage Vth, The current is allowed to flow until the voltage difference between the gate electrode and the source electrode reaches the threshold voltage. However, the fifth period t5 is shorter than the second period t2, so that the fifth period t5 ends before the source voltage Vs of the driving transistor DT reaches "Vdata-Vth" do.

The rising amount of the source voltage Vs of the driving transistor DT during the fifth period t5 is proportional to the electron mobility K of the driving transistor DT, And is proportional to the electron mobility K of the driving transistor DT. That is, the greater the electron mobility of the driving transistor DT, the greater the amount of rise of the source voltage Vs of the driving transistor DT during the fifth period t5.

As a result, the amount of rise of the source voltage Vs varies depending on the electron mobility K of the driving transistor DT during the fifth period t5. As a result, the voltage difference between the gate electrode and the source electrode of the driving transistor DT (Vgs). That is, in the embodiment of the present invention, the voltage difference Vgs between the gate electrode and the source electrode can be adjusted according to the electron mobility K of the driving transistor DT during the fifth period t5, Can be compensated for.

On the other hand, during the fifth period t5, the gate voltage Vg of the driving transistor is "Vdata ", and the source voltage Vs rises to" Vcomp-Vth-beta + alpha " At this time, "alpha" may be defined as the amount of increase of the source voltage Vs during the fifth period t5. Therefore, during the fifth period t5, the capacitor C stores "Vdata- (Vcomp-Vth-beta + alpha) ", which is the voltage difference Vgs between the gate electrode and the source electrode of the driving transistor DT. (S105 in Fig. 6)

Sixth, during the sixth period t6, the organic light emitting diode OLED emits light according to the current of the driving transistor DT.

During the sixth period t6, the k-th scan line SC is supplied with the k-th scan signal SCANk having the gate-off voltage Voff. During the sixth period t6, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the sixth period t6, the k th driving voltage line VDLk is supplied with the k th driving voltage VDDk of the first level voltage V1.

During the sixth period t6, the first transistor ST1 is turned off by the kth scan signal SCANk having the gate-off voltage Voff. During the sixth period t6, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff.

The voltage difference (Vgs = Vdata- (Vcomp-Vth-beta + alpha)) between the gate electrode and the source electrode of the driving transistor DT can be kept constant by the capacitor C during the sixth period t6. As a result, the current Ids of the driving transistor DT flowing into the organic light emitting diode OLED can be defined as shown in Equation (2).

Summarizing the expression (2), the expression (3) is derived.

As a result, the current Ids of the driving transistor DT does not depend on the threshold voltage Vth of the driving transistor DT as shown in Equation (3). That is, the threshold voltage Vth of the driving transistor DT is compensated. As a result, the organic light emitting diode OLED emits light according to the current Ids of the driving transistor DT whose threshold voltage Vth of the driving transistor DT is compensated, as shown in FIG. 7F. (S106 in Fig. 6)

As described above, in the embodiment of the present invention, the source electrode of the driving transistor DT is initialized to the reference voltage Vref during the first period t1, and the source electrode of the driving transistor DT during the second period t2. And the threshold voltage of the driving transistor DT is sensed to the source electrode. As a result, the embodiment of the present invention can emit the organic light emitting diode OLED according to the current Ids of the driving transistor whose threshold voltage is compensated as shown in Equation (3).

Further, the embodiment of the present invention supplies the data voltage to the gate electrode of the driving transistor DT during the fifth period t5, and raises the voltage Vs of the source electrode by "?". At this time, "? &Quot;, which is an amount of rise of the voltage Vs of the source electrode, varies depending on the electron mobility of the driving transistor DT. As a result, the embodiment of the present invention can adjust the voltage difference Vgs between the gate electrode and the source electrode in accordance with the electron mobility K of the driving transistor DT during the fifth period t5, The electron mobility K of the electron beam can be compensated.

Furthermore, the embodiment of the present invention is also applicable to the kth driving voltage line VDLk during the third and fourth periods t3 and t4, which turn off the driving transistor DT, And supplies the driving voltage VDDk. As a result, the embodiment of the present invention can minimize the rise of the source voltage Vs of the driving transistor DT due to the leakage current of the driving transistor DT.

8 is a block diagram illustrating an OLED display according to another embodiment of the present invention. Referring to FIG. 8, the OLED display includes a display panel 10, a data driver 20, a scan driver 30, an initialization driver 40, a timing controller 60, A control signal driver 80, and a voltage supplier 90.

The data driver 20, the scan driver 30, the initialization driver 40, and the timing controller 60 of FIG. 8 are substantially the same as those described with reference to FIG. Therefore, the detailed description of the data driver 20, the scan driver 30, the initialization driver 40, and the timing controller 60 of FIG. 8 will be omitted.

8, data lines (D1 to Dm, m is a positive integer of 2 or more), scan lines (S1 to Sn, n are positive integers of 2 or more), initialization lines ( SEN1 to SENn, and voltage control signal lines VCL1 to VCLn. The data lines D1 to Dm may be formed to intersect the scan lines S1 to Sn, the initialization lines SEN1 to SENn, and the voltage control signal lines VCL1 to VCLn. The scan lines S1 to Sn, the initialization lines SEN1 to SENn, and the voltage control signal lines VCL1 to VCLn may be formed in parallel with each other.

The display panel 10 is provided with a pixel P connected to the data lines D1 to Dm, the scan lines S1 to Sn, the initialization lines SEN1 to SENn and the voltage control signal lines VCL1 to VCLn, . Each of the pixels P may be any one of the data lines D1 to Dm and any of the scan lines S1 to Sn and any of the initialization lines SEN1 to SENn and the voltage control signal lines VCL1 to VCLn. Each of the pixels P includes first through third transistors controlled by a driving transistor, a scan signal of a scan line, an initialization signal of an initialization line, and a voltage control signal of a voltage control signal line, an organic light emitting diode an organic light emitting diode, and a capacitor. The pixel P will be described later in detail with reference to FIG.

The display panel 10 may be divided into a plurality of blocks as shown in FIG. 9, the scan lines S1 to S3p of the display panel 10, the initialization lines SEN1 to SEN3p, the drive control signal lines VDL1 to VDL3p, the drive voltage lines VDL, Only the pixels P, the scan driver 30, the initialization driver 40, the driving control signal driver 80, and the voltage supplier 90 are illustrated. In FIG. 9, the display panel 10 is divided into three blocks BL1, BL2, and BL3 for convenience of explanation. However, it should be noted that the present invention is not limited thereto.

Referring to FIG. 9, each of the blocks BL1, BL2, and BL3 may include the same number of pixels. Specifically, when the display panel 10 is divided into q blocks, each of q blocks may include pixels P connected to p scan lines. Here, "p" may be a value obtained by dividing "n" (the total number of scan lines) by "q" (the number of blocks).

For example, when the display panel 10 is divided into three blocks BL1, BL2, and BL3 as shown in FIG. 9, each of the blocks BL1, BL2, and BL3 includes p scan lines Or driving voltage lines). As shown in FIG. 9, the first block BL1 includes pixels P connected to the first through pth scan lines S1 through Sp, the second block BL2 includes p + And the pixels P connected to the lines Sp + 1 to S2p and the third block BL3 includes pixels P connected to the second p + 1 th to the third p scan lines S2p + 1 to S3p ). On the other hand, the pixels P connected to the p scan lines are substantially the same as the pixels P connected to the p drive voltage lines. In addition, the pixels P connected to the p scan lines are substantially the same as the pixels P connected to the p initialization lines.

The voltage control signal driver 80 is connected to the voltage control signal lines VCL1 to VCLn to supply voltage control signals. The voltage control signal driver 80 supplies the voltage control signals to the voltage control signal lines VCL1 to VCLn according to the voltage timing control signal VDDCS input to the timing controller 60. [ The voltage control signals swing between the gate-on voltage and the gate-off voltage as shown in Figs. The supply of the voltage control signal of the voltage control signal driver 80 will be described in detail later with reference to FIGS. 11 and 12. FIG.

The voltage supply unit 90 is connected to the driving voltage line VDL connected to the pixels P to supply the DC driving voltage. The driving voltage line VDL may intersect the scan lines S1 to Sn, the initialization lines SEN1 to SENn, and the voltage control signal lines VCL1 to VCLn as shown in FIG. The voltage supply unit 90 is connected to a reference voltage line VRL connected to the pixels P to supply a DC reference voltage.

10 is a circuit diagram showing another example of the pixel of Fig. In FIG. 10, for convenience of description, the kth scan line Sk, the k th initialization line SENk, the k th voltage control signal line VCLk, the j th data line Dj, and the reference voltage line VRL The connected pixel P is exemplified. Referring to FIG. 10, the pixel P includes an organic light emitting diode OLED and a pixel driver PD for supplying a driving current to the organic light emitting diode OLED. The pixel driving part PD may include a driving transistor DT, first through third transistors ST1, ST2, ST3, and a capacitor C. [

The organic light emitting diode OLED, the driving transistor DT, the first and second transistors ST1 and ST2, and the capacitor C shown in Fig. 10 are substantially the same as those described with reference to Fig. Therefore, detailed description of the organic light emitting diode OLED, the driving transistor DT, the first and second transistors ST1 and ST2, and the capacitor C of FIG. 10 will be omitted.

The third transistor ST3 is turned on when the k-th voltage control signal of the gate-on voltage is supplied to the k-th voltage control signal line VCLk to turn on the driving voltage of the driving voltage line VDL Drain electrode. The gate electrode of the third transistor ST3 is connected to the kth voltage control signal line VCLk and the first electrode thereof is connected to the drain electrode of the driving transistor DT and the second electrode thereof is connected to the driving voltage line VDL Can be connected.

In FIG. 10, the first electrode of the third transistor ST3 may be a source electrode or a drain electrode, and the second electrode may be a different electrode from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

10, the driving transistor DT and the first to third transistors ST1, ST2, and ST3 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, do. The driving transistor DT and the first to third transistors ST1, ST2, and ST3 may be formed of a P-type MOSFET. In this case, the waveforms of FIGS. 11 and 12 are appropriately matched to the characteristics of the P- Can be modified.

As described above, the pixel P according to the embodiment of the present invention includes the first transistor ST1 connected to the gate electrode of the jth data line Dj and the driving transistor DT, the first transistor ST1 connected to the reference voltage line VRL A second transistor ST2 connected to the source electrode of the driving transistor DT and a third transistor ST3 connected to the driving voltage line VDL and the drain electrode of the driving transistor DT. As a result, in the embodiment of the present invention, by adjusting the turn-on of the first to third transistors ST1, ST2, and ST3 and the voltage supplied to the jth data line Dj, Voltage can be sensed. A detailed description of the threshold voltage compensation of the driving transistor DT of the pixel P shown in Fig. 10 will be described later in conjunction with Fig. 6 and Fig.

11 is a waveform diagram showing an example of scan signals, initialization signals, and voltage control signals supplied to the display panel of FIG. 11, the first to third p scan signals SCAN1 to SCAN3p, the first to third p voltage control signal lines VCL1 to VCL3p (shown in FIG. 9) supplied to the first to third p scan lines S1 to S3p, The first to third p voltage control signals VCS1 to VCS3p and the first to third p initialization signals S1 to S3p supplied to the first to third p initialization lines S1 to S3p have.

Referring to FIG. 11, one frame period includes q subframe periods. For example, when the display panel 10 is divided into three blocks BL1, BL2, and BL3 as shown in FIG. 9, one frame period includes three subframe periods SF1, SF2, and SF3 .

Each of the q subframe periods includes a threshold voltage sensing period ST and a data voltage supply period DP as shown in FIG. The threshold voltage sensing period ST is a period for sensing the threshold voltage of the driving transistor DT of each of the pixels P in the block. The data voltage supply period DP is a period of supplying data voltages to the pixels P of the block.

The supply of the first to third p scan signals SCAN1 to SCAN3p of the scan driver 30 of FIG. 11 and the supply of the first to third p initialization signals SENS1 to SENS3p of the initialization driver 40 are shown in FIG. Are substantially the same as those described above. Therefore, a detailed description of the supply of the first to third p-scan signals SCAN1 to SCAN3p of the scan driver 30 of FIG. 11 and the supply of the first to third p initialization signals SENS1 to SENS3p of the initialization driver 40 Is omitted.

The embodiment of the present invention divides the display panel 10 into a plurality of blocks BL1, BL2, and BL3, sequentially drives the blocks BL1, BL2, and BL3, and simultaneously drives the blocks BL1, BL2, and BL3. As a result, the embodiment of the present invention can simultaneously perform threshold voltage sensing of the driving transistor DT for each block, and sequentially supply the data voltages to the pixels P. Therefore, the embodiment of the present invention has an advantage that the data voltage supply period DP can be sufficiently secured even when high-speed driving is performed at 120 Hz or more.

On the other hand, a period between the periods in which the scan signals of the gate-on voltage Von are supplied during the threshold voltage sensing period SP and the data voltage supply period DP in the sub-frame periods SF1, SF2, and SF3, And a voltage holding period t4 for holding the gate-source voltage of the data signal DT. Since the scan signals of the gate-on voltage Von are sequentially supplied to the scan lines during the data voltage supply period DP, the length of the voltage sustain period t4 is shorter than the length of the first scan line S1 to the p- (Sp + 1) to the second p scan line (S2p), and the second p + 1 scan line (S2p + 1) to the third p scan line (S3p) .

The embodiment of the present invention also provides the voltage control signals VCS1 to VCS3p to the gate-off voltage Voff in order to minimize the voltage rise of the source electrode of the driving transistor DT during the voltage sustain period t4 Thereby preventing the driving voltage of the driving voltage line VDDL from being supplied to the pixel. Therefore, the length of the period during which the voltage control signal of the gate-off voltage Voff is supplied differs from one driving voltage line to another. That is, the length of the period during which the voltage control signal of the gate-off voltage Voff is supplied becomes longer from the first voltage control signal line VCL1 to the p-th voltage control signal line VCLp, 1 voltage control signal line VCLp + 1 to the second p voltage control signal line VCL2p from the second p + 1 voltage control signal line VCLp + 1 to the third p voltage control signal line VCL2p.

The threshold voltage sensing period ST indicates the first to third periods t1 to t3 in FIG. 12, and the data voltage supply period DP is the fourth to sixth periods t4- t6. A detailed description of the first to sixth periods t1 to t6 will be given later with reference to FIG.

12 is a waveform diagram showing a k-th scan signal, a k-th initialization signal, a j-th data voltage, a k-th voltage control signal, and a gate voltage and a source voltage of the driving transistor. 12 shows the kth voltage control signal VCSk supplied to the k th voltage control signal line VCLk connected to the pixel P of Fig. 10, the k th scan signal SCANk supplied to the kth scan line Sk, A voltage DVj supplied to the jth data line Dj, a gate voltage Vg of the driving transistor DT, and a source voltage Vg supplied to the kth initialization line SENk, Vs).

The voltage supply of the data driver 20, the supply of the scan signal of the scan driver 30, and the initialization of the scan driver 30 during the first to sixth periods t1 to t6, the first to sixth periods t1 to t6, The initialization signal supply of the driving unit 40 is substantially the same as that described with reference to Fig. Therefore, during the first to sixth periods t1 to t6, the first to sixth periods t1 to t6, the voltage of the data driver 20, the scan signal of the scan driver 30, And the initialization signal supply of the initialization driver 40 will not be described in detail.

The voltage control signal driver 80 applies the gate on voltage Von to the k th voltage control signal line VCLk during the first, second, fifth and sixth periods t1, t2, t5 and t6, K < / RTI > voltage control signal VCSk. The voltage control signal driver 80 supplies the k th voltage control signal VCSk of the gate off voltage Voff to the k th voltage control signal line VCLk during the third and fourth periods t3 and t4.

Hereinafter, a driving method of the pixel P according to another embodiment of the present invention will be described in detail with reference to FIGS. 6, 10, and 12. FIG.

First, the source electrode of the driving transistor DT is initialized to the reference voltage Vref during the first period t1. During the first period t1, the k th voltage control signal line VCLk is supplied with the k th voltage control signal VCSk of the gate on voltage Von, thereby turning on the third transistor ST3. As a result, the operation of the pixel P in Fig. 10 during the first period t1 is substantially the same as that described with reference to Figs. 5, 6, and 7A, and therefore will not be described. (S101 in Fig. 6)

Secondly, the threshold voltage of the driving transistor DT is sensed during the second period t2. During the second period t2, the k th voltage control signal line VCLk is supplied with the k th voltage control signal VCSk of the gate on voltage Von, thereby turning on the third transistor ST3. As a result, the operation of the pixel P in Fig. 10 during the second period t2 is substantially the same as that described with reference to Figs. 5, 6, and 7B, and therefore will not be described. (S102 in Fig. 6)

Thirdly, the turn-off voltage Vt is supplied to the gate electrode of the driving transistor DT during the third period t3.

During the third period t3, the kth scan line SC is supplied with the kth scan signal SCANk having the gate-on voltage Von. During the third period t3, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. During the third period t3, the turn-off voltage Vt is supplied to the j-th data line Dj. During the third period t3, the k th voltage control signal line VCLk is supplied with the k th voltage control signal VCSk of the gate off voltage Voff.

During the third period t3, the first transistor ST1 is turned on by the kth scan signal SCANk having the gate-on voltage Von. Due to the turn-on of the first transistor ST1, the turn-off voltage Vt is supplied to the gate electrode of the driving transistor DT as shown in Figs. 5 and 7C. During the third period t3, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff. During the third period t3, the third transistor ST3 is turned off by the k-th voltage control signal VCSk having the gate-off voltage Voff.

During the third period t3, the gate voltage Vg of the driving transistor DT is the turn-off voltage Vt as shown in FIG. 12, The source voltage Vs falls to "Vcomp-Vth-beta ". At this time,? Can be defined as shown in Equation (1). (S103 in Fig. 6)

Fourth, the voltage Vs of the source electrode of the driving transistor DT is maintained during the fourth period t4.

During the fourth period t4, the kth scan signal SCANk having the gate off voltage Voff is supplied to the kth scan line Sk. During the fourth period t4, the k-th initialization signal SENk is supplied with the k-th initialization signal SENSk having the gate-off voltage Voff. The turn-off voltage Vt is supplied to the j-th data line Dj during the fourth period t4. During the third period t3, the k th voltage control signal line VCLk is supplied with the k th voltage control signal VCSk of the gate off voltage Voff.

During the fourth period t4, the first transistor ST1 is turned off by the kth scan signal SCANk having the gate-off voltage Voff. During the fourth period t4, the second transistor ST2 is turned off by the k-th initialization signal SENk having the gate-off voltage Voff. During the fourth period t4, the third transistor ST3 is turned off by the k-th voltage control signal VCSk having the gate-off voltage Voff.

The voltage Vg of the gate electrode of the driving transistor DT during the fourth period t4 maintains the turn-off voltage Vt supplied during the third period t3 as shown in Fig. Therefore, during the fourth period t4, the driving transistor DT remains in the turned-off state following the third period t3.

12, since the gate-source voltage Vgs of the driving transistor DT is smaller than the threshold voltage of the driving transistor DT during the third and fourth periods t3 and t4, Is turned off. However, even if the driving transistor DT is turned off, a leakage current can flow finely. As a result, the source voltage Vs of the driving transistor DT can be slightly increased. 4, the length of the fourth period t4 may vary depending on which scan line the pixel P is connected to, so that the source voltage Vs of the driving transistor DT is set to the pixel P, May be different depending on which scan line is connected.

Therefore, the embodiment of the present invention supplies the k-th voltage control signal VCSk having the gate-off voltage Voff during the third and fourth periods t3 and t4 that turn off the driving transistor DT . As a result, the embodiment of the present invention can cut off the connection between the drain electrode of the driving transistor DT and the driving voltage line VDL during the third and fourth periods t3 and t4, The rise of the source voltage Vs of the driving transistor DT due to the leakage current can be minimized. (S104 in Fig. 6)

Fifth, the data voltage is supplied to the gate electrode of the driving transistor DT during the fifth period t5. During the fifth period t5, the k th voltage control signal line VCLk is supplied with the k th voltage control signal VCSk of the gate on voltage Von, whereby the third transistor ST3 is turned on. As a result, during the fifth period t5, the operation of the pixel P in Fig. 10 is substantially the same as that described with reference to Figs. 5, 6, and 7E, and therefore will not be described. (S105 in Fig. 6)

Sixth, during the sixth period t6, the organic light emitting diode OLED emits light according to the current of the driving transistor DT. During the sixth period t6, the k th voltage control signal line VCLk is supplied with the k th voltage control signal VCSk of the gate on voltage Von, thereby turning on the third transistor ST3. As a result, during the sixth period t6, the operation of the pixel P in Fig. 10 is substantially the same as that described with reference to Figs. 5, 6 and 7F, and thus will not be described. (S106 in Fig. 6)

As described above, in the embodiment of the present invention, the source electrode of the driving transistor DT is initialized to the reference voltage Vref during the first period t1, and the source electrode of the driving transistor DT during the second period t2. And the threshold voltage of the driving transistor DT is sensed to the source electrode. As a result, the embodiment of the present invention can emit the organic light emitting diode OLED according to the current Ids of the driving transistor whose threshold voltage is compensated as shown in Equation (3).

Further, the embodiment of the present invention supplies the data voltage to the gate electrode of the driving transistor DT during the fifth period t5, and raises the voltage Vs of the source electrode by "?". At this time, "? &Quot;, which is an amount of rise of the voltage Vs of the source electrode, varies depending on the electron mobility of the driving transistor DT. As a result, the embodiment of the present invention can adjust the voltage difference Vgs between the gate electrode and the source electrode in accordance with the electron mobility K of the driving transistor DT during the fifth period t5, The electron mobility K of the electron beam can be compensated.

Further, the embodiment of the present invention supplies the k-th voltage control signal VCSk having the gate-off voltage Voff during the third and fourth periods t3 and t4 for turning off the driving transistor DT . As a result, the embodiment of the present invention can cut off the connection between the drain electrode of the driving transistor DT and the driving voltage line VDL during the third and fourth periods t3 and t4, The rise of the source voltage Vs of the driving transistor DT due to the leakage current can be minimized.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: data driver
30: scan driver 40: initialization driver
50: driving voltage supply unit 60: timing control unit
70: reference voltage supply unit 80: voltage control signal driver
90: voltage supply unit P: pixel
DT: driving transistor ST1: first transistor
ST2: second transistor ST3: third transistor
OLED: Organic Light Emitting Diode C: Capacitor
VRL: reference voltage line VDL: drive voltage line
Sk: kth scan line VCLk: kth voltage control signal line
SENk: kth initialization line Dj: jth data line
SCANk: kth scan signal SENSk: kth initialization signal
VCSk: kth voltage control signal Vg: gate voltage
Vs: source voltage Vref: reference voltage
Vcomp: compensation voltage Vt: turn-off voltage
Vdata: data voltage Von: gate-on voltage
Voff: gate-off voltage

Claims (16)

A display panel having pixels connected to scan lines, data lines, and drive voltage lines;
A scan driver for supplying scan signals to the scan lines;
A data driver for supplying data voltages to the data lines; And
And a driving voltage supply unit for supplying driving voltages swinging between a first level voltage and a second level voltage lower than the first level voltage to the driving voltage lines,
The display panel is divided into q (q is a positive integer equal to or greater than 2) blocks, and each of the q blocks is divided into a plurality of pixels, each of which is connected to the first to the p / RTI >
Wherein a length of a period during which the driving voltage of the second level voltage is supplied to each of the q blocks is different for each of the first to p driving voltage lines. The method according to claim 1,
Wherein a length of a period during which the driving voltage of the second level voltage is supplied to each of the q blocks becomes longer from the first driving voltage line to the p driving voltage line. The method according to claim 1,
The pixel includes:
Organic light emitting diodes;
A driving transistor connected to the organic light emitting diode and the driving voltage line to which a driving voltage is supplied;
A first transistor connected to the data line and a gate electrode of the driving transistor;
A second transistor connected to the reference voltage line and a source electrode of the driving transistor; And
And a capacitor connected between the gate electrode and the source electrode of the driving transistor. The method of claim 3,
The driving voltage supply unit includes:
Supplying a driving voltage of the first level voltage to the driving voltage line during a first period for initializing a source electrode of the driving transistor and a second period for sensing a threshold voltage of the driving transistor, And supplying a driving voltage of the second level voltage to the driving voltage line during a fourth period for maintaining the gate-source voltage of the driving transistor, and supplying a data voltage to the gate electrode of the driving transistor And supplies the driving voltage of the first level voltage to the driving voltage line during a sixth period during which the organic light emitting diode emits light by the fifth period and the current of the driving transistor. 5. The method of claim 4,
The first and second transistors are turned on during the first period so that a compensation voltage of the data line is supplied to a gate electrode of the driving transistor and a reference voltage of the reference voltage line is supplied to a source electrode of the driving transistor And,
The first transistor is turned on during the second period so that the compensation voltage is supplied to the gate electrode of the driving transistor,
The first transistor is turned on during the third period so that the turn-off voltage is supplied to the gate electrode of the driving transistor,
The first and second transistors are turned off during the fourth and sixth periods,
Wherein the first transistor is turned on during the fifth period and a data voltage of the data line is supplied to a gate electrode of the driving transistor. 5. The method of claim 4,
Further comprising initialization lines connected to the pixels,
Wherein the first transistor is turned on when a scan signal of a gate-on voltage is supplied to the scan line to supply a voltage of the data line to a gate electrode of the drive transistor,
Wherein the second transistor is turned on when an initialization signal of a gate-on voltage is supplied to the initialization line to supply the reference voltage of the reference voltage line to the source electrode of the driving transistor. The method according to claim 6,
Wherein the scan lines, the initialization lines, and the driving voltage lines are parallel to each other. The method according to claim 6,
Further comprising an initialization driver for supplying initialization signals to the initialization lines,
Wherein the data driver supplies a compensation voltage for the first and second periods to the data line and supplies a turn-off voltage during the third and fourth periods, and,
The scan driver supplies a scan signal having a gate-on voltage to the scan line during the first period to the third period and the scan signal having a gate-off voltage during the fourth and sixth periods, Supply,
Wherein the initialization driver supplies an initialization signal having a gate-on voltage for the first period to the initialization line, and supplies an initialization signal having a gate-off voltage during the second to the sixth periods. A display panel having scan lines, data lines, voltage control signal lines, and pixels connected to drive voltage lines;
A scan driver for supplying scan signals to the scan lines;
A data driver for supplying data voltages to the data lines;
A driving voltage supplier for supplying a DC driving voltage to the driving voltage lines; And
And a voltage control signal driver for supplying voltage control signals swinging between a gate-on voltage and a gate-off voltage to the voltage control signal lines,
The display panel is divided into q (q is a positive integer of 2 or more) blocks, and each of the q blocks is connected to first to p (p is a positive integer equal to or more than two) voltage control signal lines Pixels,
Wherein a length of a period during which the voltage control signal of the gate off voltage is supplied to each of the q blocks is different for each of the first through p voltage control signal lines. 10. The method of claim 9,
Wherein a length of a period during which the voltage control signal of the gate off voltage is supplied to each of the q blocks becomes longer from the first voltage control signal line to the p voltage control signal line. 10. The method of claim 9,
The pixel includes:
Organic light emitting diodes;
A driving transistor connected to the organic light emitting diode and the driving voltage line to which a driving voltage is supplied;
A first transistor connected to the data line and a gate electrode of the driving transistor;
A second transistor connected to the reference voltage line and a source electrode of the driving transistor;
A third transistor connected to the driving voltage line and the drain electrode of the driving transistor; And
And a capacitor connected between the gate electrode and the source electrode of the driving transistor. 12. The method of claim 11,
Wherein the voltage control signal driver comprises:
A voltage control signal of the gate-on voltage is supplied to the voltage control signal line during a first period for initializing a source electrode of the driving transistor and a second period for sensing a threshold voltage of the driving transistor, Off voltage is supplied to the voltage control signal line during a third period during which the gate-source voltage of the driving transistor is maintained and during a fourth period during which the gate-source voltage of the driving transistor is maintained, And supplies a voltage control signal of the gate-on voltage to the voltage control signal line during a sixth period during which the organic light emitting diode emits light by a current of the driving transistor. 13. The method of claim 12,
The first to third transistors are turned on during the first period so that a compensation voltage of the data line is supplied to a gate electrode of the driving transistor and a reference voltage of the reference voltage line is supplied to a source electrode of the driving transistor The driving voltage is supplied to the drain electrode of the driving transistor,
The first and third transistors are turned on during the second period so that the compensation voltage is supplied to the gate electrode of the driving transistor, the driving voltage is supplied to the drain electrode of the driving transistor,
The first transistor is turned on during the third period so that the turn-off voltage is supplied to the gate electrode of the driving transistor,
During the fourth period, the first to third transistors are turned off,
The first and third transistors are turned on during the fifth period so that a data voltage of the data line is supplied to a gate electrode of the driving transistor and the driving voltage is supplied to a drain electrode of the driving transistor,
And the third transistor is turned on during the sixth period so that the driving voltage is supplied to the drain electrode of the driving transistor. 13. The method of claim 12,
Further comprising initialization lines connected to the pixels,
Wherein the first transistor is turned on when a scan signal of a gate-on voltage is supplied to the scan line to supply a voltage of the data line to a gate electrode of the drive transistor,
Wherein the second transistor is turned on when an initialization signal of a gate-on voltage is supplied to the initialization line to supply the reference voltage of the reference voltage line to the source electrode of the driving transistor,
And the third transistor is turned on when a voltage control signal of a gate-on voltage is supplied to the voltage control signal line to supply the driving voltage of the driving voltage line to the drain electrode of the driving transistor. 15. The method of claim 14,
Further comprising an initialization driver for supplying initialization signals to the initialization lines,
Wherein the data driver supplies the data line with a compensation voltage during the first and second periods, supplies the turn-off voltage during the third and fourth periods, and supplies the data voltage during the fifth period Supply,
The scan driver supplies a scan signal having a gate-on voltage to the scan line during the first period to the third period and the scan signal having a gate-off voltage during the fourth and sixth periods, Supply,
Wherein the initialization driver supplies an initialization signal having a gate-on voltage for the first period to the initialization line, and supplies an initialization signal having a gate-off voltage during the second to the sixth periods. The method according to claim 5, 8, 13, or 15,
Wherein the compensation voltage is higher than the reference voltage, the data voltage is higher than the compensation voltage, and the turn-off voltage is lower than the compensation voltage.

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