KR20160083338A - Display device - Google Patents

Abstract

An object of the present invention is to provide a scheme capable of preventing a gate driving signal transfer line from being defective due to static electricity. To this end, a display device according to the present invention includes a discharge pattern including first and second discharge patterns on a mother substrate, wherein the first discharge pattern surrounds first pads through which a gate driving signal is applied to a first display area on which a gate IC is mounted, and the second discharge pattern covers a transfer line. The discharge pattern is located on the outside of a first non-display area and connected to a guide ring connected to a ground terminal of the mother substrate. In addition, a connecting pad electrode terminal, which is located in a second non-display area adjacent to the first non-display area and connected to a flexible film, is connected to a guide ring outside the second non-display area. Therefore, during a process of manufacturing an array substrate, static electricity may not be introduced into the transfer line and may be exhausted into the ground terminal through the discharge pattern and a discharge pass including the connecting pad electrode terminal and the guide ring, so that an error of the transfer line may be prevented from occurring due to the static electricity. In addition, the discharge pass is formed on the transfer line, so that the discharge pass may be effectively implemented without enlarging the area of a non-display area.

Description

Display device

The present invention relates to a display device, and more particularly, to a display device capable of improving electrostatic defects of a transfer wiring through which a gate driving signal is transmitted in a COG display device.

2. Description of the Related Art [0002] As an information-oriented society develops, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various flat display devices such as an organic light emitting diode (OLED) have been utilized.

Of these flat panel display devices, liquid crystal display devices are widely used today because they have advantages of miniaturization, weight reduction, thinness, and low power driving.

In the COG type liquid crystal display device in which the driving IC is directly mounted on the array substrate of the liquid crystal panel, various driving signals for driving the driving IC are transmitted through the flexible circuit film connected to the liquid crystal panel. The drive signal thus transmitted is transferred to the data IC for outputting the data signal to the data wiring and to the gate IC for outputting the gate signal to the gate wiring.

The gate drive signal transmission wirings for transferring the gate drive signal to the gate IC are arranged in close proximity to each other at a narrow width, which corresponds to a large metal pattern as a whole. Accordingly, the gate drive signal transmission wirings are vulnerable to static electricity, and a failure can be caused by the static electricity generated in the manufacturing process of the array substrate.

That is, static electricity flows from the outside into the gate driving signal transmission line, causing a line defect such as an electrical open or a short, thereby lowering the product yield of the liquid crystal display device .

On the other hand, the above-described problem occurs in other display devices using a COG type array substrate in addition to a liquid crystal display device.

SUMMARY OF THE INVENTION The present invention has a problem to provide a method for preventing electrostatic defects in a gate drive signal transmission wiring.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a first non-display region of an array substrate on which a gate IC region is formed and including a first discharge pattern and a second discharge pattern, A plurality of first wiring patterns formed on the gate insulating film and overlapping the second discharge pattern; a plurality of first pads disposed in the gate IC region and surrounded by the first discharge pattern; The plurality of first pads being connected to the plurality of transmission wirings, and the plurality of second pads being connected to the plurality of gate wirings.

And a plurality of connection pads disposed in a second non-display area of the array substrate adjacent to the first non-display area, the plurality of connection pads being connected to the plurality of transmission wirings, And a connection pad electrode terminal located on the same layer as the first non-display region and extending to a second outer side of the array substrate outside the second non-display region.

And a part of the discharge pattern may extend to the first outer side of the array substrate outside the first non-display area.

Each of the gate pads includes a gate pad electrode located under the insulating film in the same layer as the gate wiring and a gate pad electrode terminal located in the same layer as the discharge pattern on the insulating film and in contact with the gate pad electrode can do.

A floating wiring electrically overlapped with the second discharge pattern may be formed under the insulating film.

According to the present invention, in a mother substrate, a first discharge pattern surrounding first pads to which a gate driving signal is applied in a first non-display region in which a gate IC is mounted, and a second discharge pattern covering a transfer wiring, And the discharge pattern is connected to the guide ring which is located outside the first non-display area and connected to the ground terminal of the mother board.

The connection pad electrode terminal, which is located in the second non-display region adjacent to the first non-display region and is connected to the flexible circuit film, is connected to the guide ring outside the second non-display region.

Therefore, in the process of manufacturing the array substrate, the static electricity does not flow into the transmission wiring, but can be discharged to the ground terminal through the discharge pattern and the discharge pad through the connection pad electrode terminal and the guide ring, thereby preventing defects in the transmission wiring due to static electricity .

Furthermore, since the discharge path is formed above the transfer wiring, the discharge path can be effectively implemented without enlarging the area of the non-display area.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a discharge path structure for a gate driving signal transmission wiring in a manufacturing process of an array substrate according to an embodiment of the present invention; Fig.
Fig. 2 is a plan view showing a part of a cell region of the mother board of Fig. 1; Fig.
Figures 3 and 4 are cross-sectional views taken along the cutting lines III-III and IV-IV, respectively, of Figure 2;
5 is a plan view showing a part of a non-display region of an array substrate in a liquid crystal panel state according to an embodiment of the present invention;
6 is a flowchart illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

As a display device according to an embodiment of the present invention, any type of display device in which a driving IC is mounted by a COG method can be used. Hereinafter, a liquid crystal display device will be described as an example for convenience of explanation.

1 is a schematic view illustrating a discharge path structure for a gate driving signal transmission wiring in a manufacturing process of an array substrate according to an embodiment of the present invention.

1, in the manufacturing process of the array substrate 110, a cell region CA corresponding to each of the plurality of array substrates 110 is defined in the mother substrate MG, The thin film forming process is performed.

Each cell region CA includes a first region A1 which is substantially the array substrate 110 and a second region A1 which is defined along the periphery of the first region A1 and which is removed by a subsequent liquid crystal panel- Area A2. At the boundary between the first and second areas A1 and A2, a cutting line SC for removing the second area A2 is located at the cutting step.

In the first area A1, pixels are arranged in a matrix form, and a display area AA for displaying an image and a non-display area NA around the display area AA are defined. The non-display area NA includes a first non-display area NA1 in which a gate IC area GICA in which the gate IC is mounted is defined and a second non-display area NA1 in which a data IC area DICA in which the data IC is mounted is defined. (NA2). ≪ / RTI > Here, in the embodiment of the present invention, a case where a plurality of gate ICs and a plurality of data ICs are used will be exemplified.

A flexible circuit film is connected to the outside of the second non-display area NA2, and a plurality of connection pads (PDC) receiving driving signals corresponding to a plurality of output bumps of the flexible circuit film are formed. Such a connection pad PDC can be transferred to the data IC and the gate IC through the transfer wiring formed in the second non-display area NA2.

Here, the gate driving signal for driving the gate IC includes control signals such as a gate start pulse signal GSP, a gate shift clock signal GSC and a gate output enable signal GOE, a gate high voltage VGH, And may include a power supply signal, such as a gate low voltage (VGL).

In the gate IC region GICA of the first non-display area NA1, a gate pad PDG corresponding to a plurality of bumps formed in the gate IC is formed.

Here, the gate IC may include a gate signal output bump for outputting a gate signal to a gate wiring, a drive signal input bump for receiving a drive signal, and an output bump for outputting a drive signal to a gate IC of a next next stage .

The gate pad PDG may include a plurality of first pads PDG1 corresponding to drive signal input bumps and output bumps of the gate IC and a plurality of second pads PDG2 corresponding to gate signal output bumps have. Meanwhile, the gate pad (PDG) may further include a dummy pad in an electrically floating state.

In the first non-display area NA1, a transfer wiring for transferring a driving signal to the gate IC extends along the longitudinal direction of the first non-display area NA1.

Such a transfer wiring is connected at one end to the corresponding connection pad PDC of the second non-display area NA2 and is connected to the first gate IC area GICA of the first non-display area NA1 (A gate IC region in which the gate ICs closest to the regions NA2 are mounted) and connected at the other end to the corresponding first pads PDG1, adjacent gate IC regions GICA And a second transfer wiring connected at one end and the other end to each of the corresponding first pads PDG1 of these gate IC regions between the first gate IC region and the second gate IC region of the next stage.

On the other hand, a floating wiring electrically floating in the vicinity of the transfer wiring for transferring the gate driving signal may be further formed in the first non-display area NA1.

At this time, in the embodiment of the present invention, a loop-shaped first discharge pattern ESD1 surrounding the above-described first pads PDG1 and a second discharge pattern ESD2 covering the transfer wiring and the floating wiring, A discharge pattern ESD including a discharge pattern ESD2 is formed.

Here, the first discharge pattern ESD1 may have a closed loop shape or an open loop shape. At this time, even when the first discharge pattern ESD1 is an open-loop shape, the first discharge pattern ESD1 may be connected to the guide ring GUR to form a closed loop shape together with the guide ring GUR.

The discharge pattern ESD is connected to a guide ring GUR formed along the second area A2 of each cell area CA to form a discharge path. That is, a part of the discharge pattern ESD is formed by extending to the guide ring GUR.

The guide ring GUR of each cell region CA is connected to the ground terminal GT formed in the peripheral region outside the cell region CA of the mother substrate MG.

With this structure, in the state of the mother substrate MG, the first discharge path DP1 from the discharge pattern ESD to the ground terminal GT via the guide ring GUR can be formed.

Furthermore, according to the embodiment of the present invention, the connection pad (PDC) from which the gate driving signal is output can also be configured to be connected to the guide ring GUR. That is, the connection pad electrode terminal located on the uppermost layer of the connection pad PDC is formed by extending the guide ring GUR. At this time, the connection pad electrode terminal is configured not to be connected to the discharge pattern (ESD) in the first region A1.

With this configuration, in the state of the mother substrate MG, the second discharge path DP2 is formed from the connection pad electrode terminal to the ground terminal GT of the mother substrate MG via the guide ring GUR .

Accordingly, the static electricity generated in the vicinity of the transfer wiring for transferring the gate driving signal during the fabrication of the array substrate 110 does not flow into the transfer wiring or the floating wiring, and the first discharge path and the second discharge path (DP1, DP2) It is possible to escape to the ground terminal GT of the mother substrate MG through the gate electrode of the transistor Q1.

After the manufacturing process for the array substrate 110 is completed in the state of the mother substrate MG, the mother substrate MG on which the array substrate 110 is manufactured, that is, the first mother substrate MG, do. Here, the second mother substrate is a counter substrate facing the array substrate, for example, a color filter substrate for forming a cell area unit. The second mother substrate on which the color filter substrate is manufactured is a first mother substrate ).

The first mother substrate MG and the second mother substrate are bonded to each other to form a liquid crystal panel. The liquid crystal panel is formed by cutting a cell unit. The non-display area NA of the array substrate 110 Is not substantially covered by the color filter substrate but exposed to the outside.

In this cell-based cutting process, the cell region CA of the first mother substrate MG is cut along the cutting line SC to remove the second region A2, The corresponding array substrate 110 is finally left.

As described above, in the state of the liquid crystal panel in which the cell-based cutting process is performed, the second region A2 of the cell region CA is removed, and the guide ring GUR formed in the second region A2 is also removed.

Accordingly, the discharge pattern ESD formed in the first non-display area NA1 of the array substrate 110 is disconnected from the guide ring GUR and finally left electrically floating. That is, part of the discharge pattern ESD configured to be connected to the guide ring GUR extends to the cutting line SC outside the first non-display area NA1, that is, to the first outer side L1 of the array substrate 110 .

The connection pad electrode terminal formed in the second non-display area NA2 of the array substrate 110 is disconnected from the guide ring GUR and is disconnected from the cut line SC outside the second non- That is, to the second outer side (L2) of the array substrate 110.

Hereinafter, the discharge path structure for the gate driving signal transmission wiring according to the embodiment of the present invention will be described in more detail with reference to FIGS. FIG. 2 is a plan view showing a part of the cell region of the mother substrate of FIG. 1, and FIGS. 3 and 4 are cross-sectional views taken along the cutting lines III-III and IV-IV of FIG. 2, the non-display area and the second area of the first area of the cell area are mainly shown for convenience of explanation.

2, the cell region CA includes a first region A1 which is substantially the array substrate 110 and a second region A1 which is located along the periphery of the first region A1 and which is formed in a subsequent step of cutting the liquid crystal panel unit And a second area A2 that is removed by the second area A2.

A cutting line SC for removing the second area A2 is located at the boundary between the first and second areas A1 and A2 during the cutting step for forming the liquid crystal panel and is formed along the cutting line SC When the cutting process is performed, the array substrate 110 having the cut line SC as an outer side is formed.

A guide ring GUR connected to the ground terminal GT of the mother substrate MG is formed in the second area A2 along the outer side of the array substrate 110 in the second area A1. The guide ring GUR may be formed of the same material as the discharge pattern ESD formed in the first area A1, but the present invention is not limited thereto.

A flexible circuit film is connected to the second non-display area NA2, and a plurality of connection pads (PDC) receiving driving signals corresponding to a plurality of output bumps of the flexible circuit film are formed.

3, each of the plurality of connection pads PDC includes a lower connection pad electrode 122 and a connection pad electrode terminal 142 exposed to the outside and connected to output bumps of the flexible circuit film do.

Here, the connection pad electrode 122 to which the gate driving signal is applied may be formed on the substrate 111 with the same material in the same layer as the gate wiring GL to which the gate signal is applied. At least one insulating layer 130 is formed on the connection pad electrode 122 and a second contact hole CH2 is formed in the insulating layer 130. The second contact hole CH2 is a contact hole exposing the connection pad electrode 122.

A connection pad electrode terminal 142 is formed on the insulating film 130 to contact the connection pad electrode 122 through the second contact hole CH2. The connection pad electrode terminal 142 may be formed of the same material as the pixel electrode formed in the pixel of the display area. That is, the connection pad electrode terminal 142 may be formed of a transparent conductive material such as ITO or IZO.

At this time, the connection pad electrode terminal 142 extends beyond the cut line SC to the outside of the second non-display area NA2, and is connected to the guide ring GUR located in the second area A2 of the cell area CA ). ≪ / RTI >

In the first non-display area NA1, a gate IC area GICA on which the gate IC is mounted is defined. In the gate IC region GICA, a plurality of gate pads PDG corresponding to the plurality of bumps formed in the gate IC are formed.

A plurality of gate pads PDG are formed of a plurality of first pads PDG1 and a plurality of second pads PDG2 and a plurality of first pads PDG1 and a plurality of second pads PDG2 are connected to a first discharge Pattern (ESD1). That is, a plurality of second pads PDG2 for outputting gate signals are formed on one side of the first discharge pattern ESD1, that is, on the second pad region on the outer side, with the first discharge pattern ESD1 as a boundary, A plurality of first pads PDG1 may be formed in the first pad region on the other side of the discharge pattern ESD1.

The plurality of first pads PDG1 may include a plurality of pads connected to a transmission line for transmitting a driving signal to which a driving signal is applied. The plurality of pads to which the driving signal is applied may include a pad PDG1 receiving a driving signal from the corresponding transmission line LL and a pad outputting a driving signal to the corresponding transmission line LL . At this time, the gate IC receives the driving signal through the pad receiving the driving signal, and the gate IC outputs the driving signal through the pad for outputting the driving signal.

The plurality of first pads PDG1 may further include a floating dummy pad PDD to which no additional signal is applied.

Referring to FIG. 4, each of the plurality of gate pads PDG formed as described above includes a lower gate pad electrode 121 and a gate pad electrode terminal 141 exposed to the outside and connected to the bump of the gate IC .

In this regard, the gate pad electrode 121 may be formed on the substrate 111 with the same material as the gate line GL to which the gate signal is applied. At least one insulating layer 130 is formed on the gate pad electrode 121. A first contact hole CH1 is formed in the insulating layer 130. The first contact hole CH1 is a contact hole exposing the gate pad electrode 121. [

A gate pad electrode terminal 141 is formed on the insulating layer 130 to contact the gate pad electrode 121 through the first contact hole CH1. The gate pad electrode terminal 141 may be formed of the same material as the pixel electrode formed in the pixel of the display area. That is, the gate pad electrode terminal 141 may be formed of a transparent conductive material such as ITO or IZO.

The first discharge pattern ESD1 may be formed in a loop shape surrounding the first pad region where the first pad PDG1 is formed in a state where the first discharge pattern ESD1 is electrically isolated from the plurality of first pads PDG1 described above have. The first discharge pattern ESD1 extends beyond the cutting line SC to the outside of the first non-display area NA1 and extends through the guide ring GUR located in the second area A2 of the cell area CA ). ≪ / RTI >

The first discharge pattern ESD1 is formed of the same material as the gate pad electrode terminal 141 in the same layer. That is, the first discharge pattern ESD1 may be positioned on the uppermost layer in the first non-display area NA1 together with the gate pad electrode terminal 141 and may be exposed to the outside.

On the other hand, in the first non-display area NA1, a transfer wiring LL extending along the longitudinal direction of the first non-display area NA1 and transmitting a gate driving signal is formed. Such a transfer wiring LL may be formed of the same material in the same layer as the gate wiring GL.

The transfer wiring LL is connected at one end to the corresponding connection pad electrode 122 of the second non-display area NA2 and extends to the first gate IC area GICA of the first non-display area NA1, The first transmission line LL1 connected to the first pad PDG1 at the other end and the corresponding first pad PDG1 of the gate IC regions GICA between the neighboring gate IC regions GICA, And a second transmission line LL2 connected at one end and the other end.

In addition to the transfer wiring LL for transferring the driving signal, the floating wiring FL in an electrically floating state may be formed around the transfer wiring LL in the first non-display area NA1. Such a floating interconnection line FL is formed to extend along the extending direction of the first non-display area NA1 similarly to the transmission line LL and may be formed of the same material as the transmission line LL .

Referring to FIG. 3, a second discharge pattern ESD2 may be formed on the transfer wiring LL and the floating wiring FL with the insulating film 130 interposed therebetween. The second discharge pattern ESD2 may be formed so as to overlap with the transfer wiring LL and the floating wiring FL located below the second discharge pattern ESD2. The second discharge pattern ESD2 is preferably formed to have a width equal to or greater than the width of the transfer line LL and the floating line FL so as to cover the lower transfer wiring LL and the floating wiring FL, But is not limited thereto.

Here, regarding the formation of the second discharge pattern ESD2 on the floating wiring line FL, when static electricity flows into the floating wiring line FL, electrostatic discharge is generated in the adjacent transfer wiring line LL, The second discharge pattern ESD2 is arranged correspondingly to the transfer wiring LL when the floating wiring FL is formed.

The second discharge pattern ESD2 may be formed of the same material as the first discharge pattern ESD1 and may be integrally formed with the first discharge pattern ESD1. The discharge pattern ESD composed of the first and second discharge patterns ESD1 and ESD2 is connected to the guide ring GUR.

As described above, in the state of the mother substrate MG, the first non-display area NA1 is provided with the loop-shaped first discharge pattern ESD1 surrounding the first pads PDG1 to which the gate driving signal is applied, A second discharge pattern ESD2 covering the transfer wiring and the floating wiring lines LL and FL is formed on the insulating film 130 and the first and second discharge patterns ESD1 and ESD2 are formed outside the first non- To the guide ring GUR of the main body. With this structure, in the state of the mother substrate MG, the first discharge path DP1 from the discharge pattern ESD to the ground terminal GT via the guide ring GUR can be formed.

Furthermore, the connection pad electrode terminal 142 to which the flexible circuit film is connected is configured to be connected to the guide ring GUR outside the second non-display area NA2. With this structure, in the state of the mother substrate MG, the second discharge path DP2 can be formed from the connection pad electrode terminal 142 to the ground terminal GT via the guide ring GUR.

The static electricity generated in the vicinity of the transfer wiring LL for transferring the gate driving signal during the manufacturing process of the array substrate 110 is not flowed into the transfer wiring LL but flows through the first discharge path DP1 and the second discharge path DP2 to the ground terminal GT of the mother substrate MG so that defects of the transfer wiring LL due to static electricity can be prevented.

Further, since the non-display area NA formed with the transfer wiring LL has a limited area, it is not easy to form the discharge path in the same layer as the transfer wiring LL. On the other hand, in the embodiment of the present invention, since the discharge path is formed above the transfer wiring LL with the insulating film 130 therebetween, it is possible to effectively implement the discharge path without enlarging the area of the non-display area NA It has advantages.

Hereinafter, an array substrate in a liquid crystal panel state according to an embodiment of the present invention will be described with reference to FIG. 5 is a plan view showing a part of a non-display region of the array substrate in the liquid crystal panel state according to the embodiment of the present invention.

Referring to FIG. 5, when the cell unit cutting process is performed to form the liquid crystal panel, the outside of the cut line SC of the cell region (CA in FIG. 2) of the first mother substrate (MG in FIG. 2) , And the first area (A1 in Fig. 2) inside the cut line is left, thereby forming the array substrate 110 in the liquid crystal panel state.

Thus, the guide ring (GUR in Fig. 2) formed in the second region (A2 in Fig. 2) of the cell region is removed, and the discharge pattern ESD located in the first non-display area NA1 is electrically discharged . Particularly, the discharge pattern (ESD) portion connected to the guide ring in the state of the mother substrate has a shape extending to the first outer side L1 of the array substrate 110 by the cutting process.

At this time, the first discharge pattern ESD1 in the array substrate 110 in the liquid crystal panel state may have a closed loop shape or an open loop shape opened toward the first outer side L1. In this regard, when the inner region surrounded by the first discharge pattern ESD1 in the form of a closed loop in the mother substrate is formed to be positioned in the first region of the cell region, the first discharge pattern ESD1 after the cutting process is still It has a closed loop shape. Alternatively, in the case where the inner region surrounded by the first discharge pattern ESD1 in the form of a closed loop in the mother substrate is formed to extend to the inside of the second region of the cell region, the first discharge pattern ESD1 after the cutting process, Has an open-loop shape. Further, even when the first discharge pattern ESD1 is formed to be connected to the guide ring in the form of an open loop in the mother substrate, the first discharge pattern ESD1 after the cutting process has an open loop shape.

The connection pad electrode terminal 142 located in the second non-display area NA2 has a shape extending to the second outer side L2 of the array substrate 110 by the cutting process.

Hereinafter, a method for manufacturing a liquid crystal display device having the above-described structure will be briefly described with reference to FIG.

Referring to FIG. 6, a plurality of array substrates (110 in FIG. 5) are manufactured (S11) in units of cell areas in a first mother substrate (MG in FIG. 2) And a filter substrate is manufactured (S12). Here, in manufacturing the array substrate in the first mother substrate, first and second discharge patterns (ESD1 and ESD2 in Fig. 2) connected to the guide ring (GUR in Fig. 2) 2 142) of the first and second guide ribs 141 and 142 are connected by a guide ring.

Next, the first and second mother boards are attached (S20). In such a laminating process, the liquid crystal layer can be filled between the array substrate and the color filter substrate.

Next, the cutting process is performed for each of the first and second mother boards, which are bonded together, in units of cells (S30). By such a cell unit cutting step, a cut liquid crystal panel is formed. As such, when the cell-by-cell cutting process is performed, the first and second discharge patterns and the connection pad electrode terminals are disconnected from the guide ring, resulting in a floating state.

Next, the data IC and the gate IC are mounted on the non-display area of the liquid crystal panel, and the flexible circuit film connected to the drive board is attached to the liquid crystal panel (S40).

Through the above process, the liquid crystal display device according to the embodiment of the present invention can be manufactured.

As described above, according to the embodiment of the present invention, in the state of the mother substrate, the first discharge pattern surrounding the first pads to which the gate driving signal is applied is applied to the first non-display region where the gate IC is mounted, And the discharge pattern is connected to a guide ring located outside the first non-display area and connected to the ground terminal of the mother board.

The connection pad electrode terminal, which is located in the second non-display region adjacent to the first non-display region and is connected to the flexible circuit film, is connected to the guide ring outside the second non-display region.

Therefore, in the process of manufacturing the array substrate, the static electricity does not flow into the transmission wiring, but can be discharged to the ground terminal through the discharge pattern and the discharge pad through the connection pad electrode terminal and the guide ring, thereby preventing defects in the transmission wiring due to static electricity .

Furthermore, since the discharge path is formed above the transfer wiring, the discharge path can be effectively implemented without enlarging the area of the non-display area.

Although the liquid crystal display device has been described as an example for convenience of description, it is obvious to those skilled in the art that the embodiments of the present invention can be applied to a COG type array substrate and all kinds of display devices using the same .

The embodiment of the present invention described above is an example of the present invention, and variations are possible within the spirit of the present invention. Accordingly, the invention includes modifications of the invention within the scope of the appended claims and equivalents thereof.

110: Arranger board 121: Gate pad electrode
122: connection pad electrode 130: insulating film
141: gate pad electrode terminal 142: connection pad electrode terminal
MG: Mosquito board
A1, A2: a first area, a second area
AA, NA: display area, non-display area
NA1, NA2: a first non-display area, a second non-display area
GICA, DICA: gate IC area, data IC area
ESD, ESD1, ESD2: discharge pattern, first discharge pattern, second discharge pattern
LL, LL1, LL2: a transfer wiring, a first transfer wiring, a second transfer wiring
PDC: Connection pad
PDD: dummy pad
PDG, PDG1, PDG2: gate pad, first pad, second pad
GL: gate wiring
FL: Floating wiring
CH1, CH2: first contact hole, second contact hole
GUR: Guide ring
GT: Ground terminal

Claims (5)

A discharge pattern which is located in a first non-display region of the array substrate on which the gate IC region is formed and includes first and second discharge patterns connected to each other on the insulating film;
A plurality of transfer wirings overlapping the second discharge pattern below the insulating film;
And a plurality of gate pads disposed in the gate IC region and including a plurality of first pads surrounded by the first discharge pattern and a plurality of second pads located outside the first discharge pattern,
The plurality of first pads are connected to the plurality of transmission wirings, and the plurality of second pads are connected to a plurality of gate wirings
Display device.
The method according to claim 1,
And a plurality of connection pads arranged in a second non-display area of the array substrate adjacent to the first non-display area, the plurality of connection pads being connected to the plurality of transmission wirings,
Wherein each of the plurality of connection pads includes a connection pad electrode terminal located on the same layer as the discharge pattern and extending to a second outer side of the array substrate outside the second non-
Display device.
The method according to claim 1,
And a part of the discharge pattern extends to a first outer side of the array substrate outside the first non-display area
Display device.
The method according to claim 1,
Each of the gate pads includes:
A gate pad electrode located under the insulating film and located in the same layer as the gate wiring;
And a gate pad electrode terminal disposed on the insulating layer in the same layer as the discharge pattern and contacting the gate pad electrode,
Display device.
The method according to claim 1,
And a floating wiring layer which overlaps with the second discharge pattern and is in an electrically floating state,
.

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