KR20160064486A - Solar cell - Google Patents

Abstract

The present invention relates to a solar cell capable of minimizing a reduction in fill factor. The solar cell according to an embodiment of the present invention comprises: a semiconductor substrate containing impurities of a first conductivity type; an emitter unit disposed on the front surface of the semiconductor substrate and containing impurities of a second conductivity type opposite to the first conductivity type; a tunnel layer disposed on the back surface of the semiconductor substrate and including a dielectric material; a back surface field unit disposed on the back surface of the tunnel layer, doped with the impurities of the first conductivity type at a higher concentration than the semiconductor substrate, and including a polycrystalline silicon material; a first electrode connected to the emitter unit; and a second electrode connected to the back surface field unit. The front surface of the semiconductor substrate includes a first area having a first reflectivity and a second area having a second reflectivity higher than the first reflectivity and disposed on the front edge of the semiconductor substrate while surrounding the first area. The width of the second area is greater than 0 mm but less than or equal to 2 mm.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell.

With the recent depletion of existing energy resources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells produce electric energy from solar energy, and they are attracting attention because they have abundant energy resources and there is no problem about environmental pollution.

Typical solar cells have a substrate made of different conductivity type semiconductors, such as p-type and n-type, an emitter layer, and electrodes connected to the substrate and the emitter, respectively. At this time, a p-n junction is formed at the interface between the substrate and the emitter.

When light is incident on such a solar cell, a plurality of electron-hole pairs are generated in the semiconductor, and the generated electron-hole pairs are separated into electrons and holes, so that electrons and holes are directed toward the n-type semiconductor and the p- And is collected by an electrode electrically connected to the substrate and the emitter portion, and these electrodes are connected to each other by electric wires to obtain electric power.

The object of the present invention is to provide a solar cell.

A solar cell according to an example of the present invention includes: a semiconductor substrate containing an impurity of a first conductivity type; An emitter section located on the front surface of the semiconductor substrate and containing an impurity of a second conductivity type opposite to the first conductivity type; A tunnel layer located on a rear surface of the semiconductor substrate and including a dielectric material; A rear electric field portion located on the rear surface of the tunnel layer and including a polycrystalline silicon material doped with impurities of the first conductive type at a higher concentration than the semiconductor substrate; A first electrode connected to the emitter portion; And a second electrode connected to the rear electric field portion, wherein the front surface of the semiconductor substrate has a first region having a first reflectance and a second reflectance higher than the first reflectance, the first region surrounding the first region, And a second region located at the edge portion, wherein the width of the second region is greater than 0 mm and less than 2 mm.

Here, more preferably, the width of the second region may be between 10 탆 and 50 탆.

In addition, the flatness of the second region may be higher than the flatness of the first region. For example, pyramid-like irregularities may be formed in the first region, and pyramidal irregularities may not be formed in the second region.

In this case, the emitter section may further include an antireflection film made of a dielectric material. In a state where the antireflection film is provided, the first reflectance of the first region may be 5% or less. In the state where the antireflection film is provided, 2 The reflectance may be between 20% and 30%.

 Further, the back surface reflectance of the semiconductor substrate may be the same as the reflectance of the second region.

Also, the first electrode may be located above the first region, and not above the second region.

Further, the emitter portion and the antireflection film may be located over the first region and the second region.

Further, the thickness of the rear surface electric field portion may be between 50 nm and 500 nm.

In addition, the thickness of the tunnel layer may be between 0.5 nm and 2.5 nm, and the tunnel layer may be formed of SiOx or SiCx material.

A solar cell according to the present invention controls a width of a second region having a relatively low reflectance in a front surface of a semiconductor substrate to secure a second region functioning as an align key, FF) reduction can be minimized.

1 to 5 are views for explaining a solar cell according to an example of the present invention.
FIG. 6 is a view for explaining the reduction rate of the fill factor FF according to the width WS2 of the second region S2 of the semiconductor substrate 110 shown in FIG. 4 and FIG.
FIG. 7 is a view for explaining an example of a method of forming the second region S2 of the semiconductor substrate 110 among the solar cells illustrated in FIGS. 1 to 5. FIG.
8 is an experimental example in which the lifting height (BH) according to the temperature of the semiconductor substrate 110 during the process of forming the etching preventive film (AEM) is measured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

The front surface may be a surface of the semiconductor substrate to which the direct light is incident, and the rear surface may be the opposite surface of the semiconductor substrate on which no direct light is incident or on which reflected light other than direct light may be incident.

In addition, the fact that any two values are equal means that the error range is equal to or less than 10%.

Hereinafter, a solar cell according to the present invention will be described with reference to the accompanying drawings.

1 is a perspective view of a solar cell according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a solar cell according to an embodiment of the present invention. FIG. 3 is a view for explaining another example of the second bus bar 153 in FIGS. 1 and 2, and FIG. 4 is a cross-sectional view taken along line II-II of FIG. FIG. 5 (a) is an enlarged view of the portion K in FIG. 4, and FIG. 5 (b) is an enlarged view of the portion of the solar cell shown in FIG. Sectional view taken along the line X1-X1 in Fig. 5 (a).

1, an example of a solar cell according to the present invention includes a semiconductor substrate 110, an emitter section 120, an antireflection film 130, a tunnel layer 160, a rear electric section 170, A second electrode 190, a first electrode 140, and a second electrode 150.

Although the solar cell according to the present invention includes the antireflection film 130 in FIG. 1, the antireflection film 130 may be omitted in the present invention. However, in consideration of the efficiency of the solar cell, since it is more efficient to include the antireflection film 130, it will be explained that the antireflection film 130 is included as an example.

The semiconductor substrate 110 is a semiconductor semiconductor substrate 110 made of silicon containing an impurity of a first conductivity type, for example, a p-type conductivity type. As an example, the semiconductor substrate 110 may be a semiconductor wafer made of monocrystalline silicon or polycrystalline silicon.

When the semiconductor substrate 110 has a p-type conductivity type, it contains an impurity of a trivalent element such as boron (B), gallium, indium, or the like. Alternatively, however, the semiconductor substrate 110 may be of the n-type conductivity type and may be made of a semiconductor material other than silicon. When the semiconductor substrate 110 has an n-type conductivity type, the semiconductor substrate 110 may contain impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb) Hereinafter, a case where the semiconductor substrate 110 has an n-type conductivity type will be described as an example.

1 and 2, a front surface of the semiconductor substrate 110 is only a portion having a texturing surface, which is an uneven surface that has been subjected to texturing, And may include portions that do not have textured surfaces. This will be described in more detail with reference to FIG.

The emitter section 120 is disposed on the front surface of the semiconductor substrate 110 on which light is incident and includes a second conductive type opposite to the conductive type of the semiconductor substrate 110, for example, an n-type conductive type impurity So as to form a pn junction with the semiconductor semiconductor substrate 110.

The pair of electrons and holes, which are carriers generated by light incident on the semiconductor substrate 110 from the outside by the p-n junction, are separated into electrons and holes, electrons move toward the n-type, and holes move toward the p-type. Therefore, when the semiconductor substrate 110 is p-type and the emitter section 120 is n-type, the separated holes move toward the semiconductor substrate 110 and the separated electrons can move toward the emitter section 120.

Alternatively, when the semiconductor substrate 110 has an n-type conductivity type, the emitter portion 120 has a p-type conductivity type. In this case, the separated electrons may move toward the semiconductor substrate 110 and the separated holes may move toward the emitter section 120.

When the emitter section 120 has an n-type conductivity type, the emitter section 120 dopes impurities of pentavalent elements such as phosphorus (P), arsenic (As), antimony (Sb) Or may be formed by doping an impurity of a trivalent element such as boron (B), gallium, indium or the like into the semiconductor substrate 110 when the p-type conductive type is employed.

The emitter layer 120 may be formed by diffusing a second conductive type impurity into the front surface of the semiconductor substrate 110. In this case, the emitter layer 120 may be formed of the same silicon material as the semiconductor substrate 110 As shown in FIG.

For example, when the semiconductor substrate 110 is formed of a polycrystalline silicon wafer, the emitter section 120 may be formed of a polycrystalline silicon material, and the semiconductor substrate 110 may be an emitter section formed of a wafer of monocrystalline silicon 120 may be formed of a single-sided silicon material.

The antireflection film 130 is disposed on the emitter layer 120 and may be formed of at least one of an aluminum oxide film (AlOx), a silicon nitride film (SiNx), a silicon oxide film (SiOx), and a silicon oxynitride film (SiOxNy) Layer film.

Although FIGS. 1 and 2 illustrate the case where the anti-reflection film 130 is formed as a single film, it is not limited to a single film.

The antireflection film 130 reduces the reflectivity of light incident on the solar cell and increases the selectivity of a specific wavelength region, thereby enhancing the efficiency of the solar cell.

The first electrode 140 is disposed in direct contact with the emitter section 120 and is electrically connected to the emitter section 120. The first electrode 140 may include a plurality of first finger electrodes 141 and a plurality of first bus bars 143, as shown in FIG.

The plurality of first finger electrodes 141 may be located on the emitter section 120 and electrically connected to the emitter section 120 and may extend in a first direction x away from each other.

1 and 2, when the semiconductor substrate 110 is n-type, the plurality of first finger electrodes 141 may include a carrier moved to the p-type emitter section 120, for example, , Holes can be collected.

The plurality of first bus bars 143 are located on the same layer as the plurality of first finger electrodes 141 on the emitter section 120 and electrically connect the plurality of first finger electrodes 141 to each other, May extend in a second direction (y) intersecting the first finger electrode (141)

The plurality of first bus bars 143 are connected to an interconnecting connector (not shown) for connecting the solar cells to each other. The plurality of first bus bars 143 collect the carriers collected by the plurality of first finger electrodes 141, Output.

The plurality of first finger electrodes 141 and the first bus bar 143 are made of at least one conductive metal material such as Ni, Cu, Ag, May be at least one selected from the group consisting of aluminum (Al), tin (Sn), zinc (Zn), indium (In), titanium (Ti), gold (Au) ≪ / RTI >

The first electrode 140 may be formed by forming an antireflection film 130 on the entire surface of the semiconductor substrate 110 and then forming a first electrode 140 for forming the first electrode 140 on the antireflection film 130. [ The first electrode 140 may be formed by firing the paste of the first electrode 140 through the antireflection film 130 and connecting the emitter layer 120 to the first electrode 140 and firing it.

The tunnel layer 160 is disposed on the rear surface of the semiconductor substrate 110 and may include a dielectric material.

1 and 2, the tunnel layer 160 may be formed on the rear surface of the semiconductor substrate 110, and may be formed in direct contact with the rear surface of the semiconductor substrate 110.

In addition, the tunnel layer 160 may be formed on the entire rear surface region of the semiconductor substrate 110.

The tunnel layer 160 passes carriers generated in the semiconductor substrate 110 in the direction of the rear electric section 170 and may perform a passivation function with respect to the rear surface of the semiconductor substrate 110. In addition, the tunnel layer 160 may serve to increase the open-circuit voltage Voc of the solar cell.

The tunnel layer 160 may be formed of a dielectric material formed of SiCx or SiOx having high durability even at a high temperature process of 600 ° C or more. However, it is also possible to form silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenerated SiON.

In addition, the thickness (T160) of the tunnel layer 160 may be between 0.5 nm and 2.5 nm. The tunnel layer 160 may be formed by an oxidation process, an LPCVP process, or a PECVD deposition process.

Herein, the tunneling layer 160 has a thickness (T160) of 0.5 nm to 2.5 nm in order to realize the tunneling effect, and the limited range may be slightly larger than 0.5 nm to 2.5 nm. However, Can be reduced. In addition, the tunnel layer 160 may partially perform a passivation function with respect to the rear surface of the semiconductor substrate 110.

Next, the rear electric field portion 170 is located on the rear surface of the semiconductor substrate 110, impurities of the first conductive type are contained at a higher concentration than the semiconductor substrate 110, and may include a polycrystalline silicon material.

1 and 2, when the tunnel layer 160 is formed on the rear surface of the semiconductor substrate 110, the rear electric section 170 is formed directly on the rear surface of the tunnel layer 160, And may be spaced apart from the substrate 110.

1 and 2, the rear electric section 170 is formed on the rear surface of the semiconductor substrate 110, and the rear electric section 170 is formed on the semiconductor substrate 110 The open voltage Voc of the solar cell can be further improved if it is formed of polysilicon material on the rear surface of the tunnel layer 160. [

In addition, since the rear electric part 170 is formed outside the semiconductor substrate 110 without forming the rear electric part 170 in the semiconductor substrate 110, in the process of forming the rear electric part 170 in the manufacturing process, , Heat damage to the semiconductor substrate 110 can be minimized, and the characteristics of the semiconductor substrate 110 can be prevented from deteriorating. Therefore, the solar cell as shown in Figs. 1 and 2 can further improve the efficiency.

The thickness T170 of the rear electric section 170 may be between 50 nm and 500 nm.

The second electrode 150 is disposed on the rear surface of the rear electric part 170 and is electrically connected to the rear electric part 170. The second electrode 150 may include a plurality of second finger electrodes 151 and a plurality of second bus bars 153, as shown in FIGS.

The plurality of second finger electrodes 151 may extend in a first direction x away from each other on the rear surface of the rear electric part 170 and may include a carrier moved toward the rear electric part 170, , Holes can be collected.

The plurality of second bus bars 153 are located on the same layer as the plurality of second finger electrodes 151 on the rear electric unit 170 and electrically connect the plurality of second finger electrodes 151 to each other, May extend in a second direction (y) intersecting the plurality of second finger electrodes (151).

The plurality of second bus bars 153 are connected to interconnectors (not shown) for connecting the solar cells to each other. The second bus bars 153 collect the carriers collected by the second finger electrodes 151 and output the collected carriers to an external device .

Here, the longitudinal direction of the second bus bar 153 is the same as the longitudinal direction of the first bus bar 143, and the longitudinal direction of the second finger electrode 151 is the same as the longitudinal direction of the first finger electrode 141 And the material of the second electrode 150 may be the same as that of the first electrode 140.

1 and 2, the second finger electrode 151 and the second bus bar 153 in the second electrode 150 penetrate the rear protective layer 190 and are directly connected to the rear electric part 170, The second finger electrode 151 and the second bus bar 153 are both electrically connected to the rear electric unit 170. Alternatively, as shown in FIG. 3, the second finger electrode 151 The second bus bar 153 is not directly connected to the rear electric part 170 but is connected directly to the rear surface of the rear protective film 190 .

3, the second bus bar 153 may be electrically connected to the rear electric section 170 through the second finger electrode 151. In this case,

The width of the second finger electrode 151 may be between 150 μm and 400 μm and the width of the second bus bar 153 may be greater than the width of the second finger electrode 151. Lt; / RTI > However, it is not necessarily limited to this, and may have a different width.

1 and 2, the rear protective layer 190 may be located on the entire surface of the back surface of the rear electric part 170 except the area where the second electrode 150 is formed.

The rear passivation layer 190 may be formed of a dielectric material and may be formed of a single layer or a plurality of layers and may have a specific fixed charge in consideration of the polarity of the rear electric section 170.

The material of the rear passivation layer 190 may be at least one of SiCx, SiOx, silicon nitride (SiNx), hydrogenerated SiNx, aluminum oxide (AlOx), silicon oxynitride (SiON), or hydrogenated SiON.

The rear protective layer 190 may function to passivate the rear surface of the rear electric part 170.

In FIGS. 1 and 2, the operation of the solar cell according to this embodiment having such a structure is as follows.

When light is irradiated by the solar cell and is incident on the semiconductor substrate 110 through the antireflection film 130 and the emitter section 120, electron-hole pairs are generated in the semiconductor substrate 110 by the light energy. At this time, the reflection loss of light incident on the semiconductor substrate 110 is reduced by the anti-reflection film 130, and the amount of light incident on the semiconductor substrate 110 is increased.

These electron-hole pairs are separated from each other by the pn junction of the semiconductor substrate 110 and the emitter section 120, and the holes and electrons are separated from each other by, for example, an emitter section 120 having a p- To the semiconductor substrate 110 having the conductive type. The holes transferred to the emitter section 120 are collected by the first finger electrodes 141 and transferred to the first bus bar 143 and are electrically connected to the rear electric section 170 located on the rear side of the semiconductor substrate 110 The moved electrons may be collected by the second finger electrode 151 and transmitted to the second bus bar 153.

When the first and second bus bars 143 and 153 of the solar cells adjacent to each other are connected to each other by an interconnecting connector (not shown), a current flows and it can be used as electric power from the outside.

4 and 5, in the solar cell according to the present invention, the front surface of the semiconductor substrate 110 includes a first region S1 having a textured surface and a second region S2 having no textured surface ).

4 and 5, the first region S1 may be located at a central portion of the front surface of the semiconductor substrate 110 among the entire front surface region of the semiconductor substrate 110, As shown in FIG.

The second region S2 is located at the front edge portion of the semiconductor substrate 110 surrounding the first region S1 of the entire front surface region of the semiconductor substrate 110 and has no textured surface, And can have a second reflectance that is relatively higher than the first reflectance.

In addition, the second reflectance of the second region S2 may be equal to the reflectance of the back surface of the semiconductor substrate 110 having no textured surface, as shown in FIGS. 1, 2 and 5 (b) .

For example, when the antireflection film 130 is provided on the entire surface of the emitter 120 formed on the front surface of the semiconductor substrate 110, when the antireflection film 130 is provided on the basis of the wavelength band of 500 nm, The first reflectance of the first region S1 may be 5% or less and the second reflectance of the second region S2 may be 20% to 30%.

Therefore, the flatness of the second region S2 may be higher than the flatness of the first region S1. More specifically, as shown in Figs. 5A and 5B, the first area S1 has a textured surface formed thereon. For example, the first area S1 is provided with a plurality of irregularities having a pyramid shape, The area S2 is not provided with the surface for the test, and the pyramid-shaped irregularities provided in the first area S1 may not be provided.

Accordingly, the second region S2 having a relatively higher reflectance may be arranged in a manner that the alignment mark (e.g., the first region 140) for recognizing the boundary of the semiconductor substrate 110 during the process of forming the first electrode 140, align key.

4 and 5, the first electrode 140 may be located on the first region S1 of the semiconductor substrate 110 and may not be located on the second region S2. 4 and 5 (a), the first finger electrode 141 and the first bus bar 143 of the first electrode 140 described above are connected only to the first region S1, Can be located.

The reason why the first electrode 140 is located only on the first region S1 is that when the first electrode 140 is located above the second region S2 which is the edge portion of the semiconductor substrate 110 , The side surface of the semiconductor substrate 110 and the first electrode 140 are connected to each other to cause a shunt.

5B, the emitter layer 120 and the anti-reflection layer 130 are all located on the first region S1 and the second region S2 on the front surface of the semiconductor substrate 110 .

5B, the emitter layer 120 and the anti-reflection layer 130 are located only on the first region S1 and the second region S2 on the entire surface of the semiconductor substrate 110, (LF) of the semiconductor substrate 110 in parallel with the third direction z intersecting with the first direction (x, y). Alternatively, the emitter layer 120 and the reflective layer The prevention layer 130 may be formed not only on the front surface of the semiconductor substrate 110 including the first and second regions S1 and S2 but also on the side surface LF of the semiconductor substrate 110. [

Here, the width WS2 of the second area S2 may be more than 0 mm but not more than 2 mm. Here, the width WS2 of the second region S2 is set to 2 mm or less in order to minimize the decrease in the fill factor (FF) of the solar cell.

Hereinafter, the influence of the width WS2 of the second region S2 on the fill factor will be described in more detail.

6 is a view for explaining the reduction rate of the fill factor F. F according to the width WS2 of the second region S2 of the semiconductor substrate 110 shown in FIGS.

6, the x-axis represents the width WS2 of the second area S2, and the y-axis represents the reduction rate of the fill factor FF.

As shown in FIG. 6, the decrease rate of the fill factor F.F increases as the width WS2 of the second area S2 increases.

Particularly, although the influence of the reduction of the fill factor within 0.5% is very small until the width WS2 of the second area S2 is 2 mm or less, the width WS2 of the second area S2 exceeds 3.0 mm It can be seen that the slope of the reduction factor of the fill factor further increases when the width WS2 of the second area S2 exceeds 3.04 mm.

The reason why the fill factor decreases as the width WS2 of the second region S2 increases is that the second region S2 of the semiconductor substrate 110 increases as the width WS2 of the second region S2 increases. The distance at which the carrier generated at the end portion moves to the first electrode 140 located in the first region S1 increases. In this way, when the movement distance of the carrier increases, the series resistance component in the direction in which the first electrode 140 is positioned from the end of the semiconductor substrate 110, which is the end of the second region S2, Thereby reducing the fill factor.

Therefore, in order to sufficiently perform the function as an align key in the second region S2 while minimizing adverse effects on the efficiency of the solar cell in consideration of the reduction rate of the fill factor, It is possible to make the width WS2 of the second substrate S2 greater than 0 mm and less than 2 mm.

In addition, the width WS2 of the second area S2 can be set within the range of more than 0 mm and 2 mm, more preferably the width WS2 of the second area S2 can be between 10 and 50 m. The width WS2 of the second area S2 is 10 mu m or more so that the second area S2 functions as at least the alignment mark and the width WS2 of the second area S2 ) Is 50 탆 or less in order to minimize the reduction of the fill factor as described above.

Although the structure of the solar cell according to one example of the present invention has been described so far, an example of a method of forming the width WS2 of the second region S2 in the semiconductor substrate 110 as described above will be described below .

FIG. 7 is a view for explaining an example of a method of forming the second region S2 of the semiconductor substrate 110 in the solar cell shown in FIGS. 1 to 5, and FIG. 8 is a cross- (BH) according to the temperature of the semiconductor substrate 110 during the process.

The second region S2 of the semiconductor substrate 110 is a portion having a relatively low second reflectivity and is a region which is generated due to no texturing process during the process of texturing the first region S1 of the semiconductor substrate 110 to be.

Here, a method of forming the second region S2 on the semiconductor substrate 110 is as follows.

7 (a), the semiconductor substrate 110 supports the semiconductor substrate 110, and supports the semiconductor substrate 110 to heat the semiconductor substrate 110. In this case, Lt; / RTI >

7B, an etch barrier (AEM) may be deposited by PECVD to prevent the texturing process from being performed on the rear surface BS of the semiconductor substrate 110 in the direction of the arrow. Here, the material of the etching preventive film (AEM) may be, for example, SiNx or SiCx.

When the etch stop layer (AEM) is deposited on the back surface (BS) of the semiconductor substrate 110 by the PECVD method, the support plate HP applies heat to the semiconductor substrate 110 so that the etch stop layer (AEM) (BS), the degree to which the semiconductor substrate 110 is bent can be controlled.

More specifically, due to the heat applied to the semiconductor substrate 110 by the supporting plate HP during the deposition of the etching preventive film (AEM) material on the semiconductor substrate 110 by the PECVD method, The semiconductor substrate 110 is bent due to the difference between the thermal expansion coefficient of the semiconductor substrate 110 which is a silicon material and the thermal expansion coefficient of the etching preventive film AEM, As with the enlarged part, the end part can be lifted. In other words, both ends of the semiconductor substrate 110 having a relatively small thermal expansion coefficient due to the thermal expansion coefficient generated by contraction of the etching preventive film (AEM) having a relatively large thermal expansion coefficient, HP) may be generated.

As the semiconductor substrate 110 is lifted as described above, the end of the semiconductor substrate 110 may be lifted from the support plate HP, and the etch stop layer (not shown) may be formed on the edge of the front surface FS of the semiconductor substrate 110, AEM) may be partially deposited.

At this time, the width WS2 'of the edge portion at which the etching preventive film AEM is deposited on the front surface FS of the semiconductor substrate 110 is, for example, about 1/2 of the height BH of the semiconductor substrate 110 ≪ / RTI >

That is, the ratio of the width WS2 'of the edge portion at which the anti-etching film AEM is deposited to the height BH of the semiconductor substrate 110 may be 1: 1/2 or less.

7 (c), the semiconductor substrate 110 is etched using an etchant in a state where an etch stopping layer (AEM) is deposited on the back surface (BS) and front edge portions of the semiconductor substrate 110, Texturing can be done.

7C, the portion of the front surface FS of the semiconductor substrate 110 where the etching prevention film AEM is not deposited is formed as the first region S1, and the etching prevention film AEM The edge portion WS2 'of the front surface FS of the deposited semiconductor substrate 110 may be formed as the second region S2.

For example, an etching solution such as KOH may be used as the texturing treatment, but not limited thereto, various methods can be used.

Thereafter, as shown in FIG. 7D, the etch stopping layer AEM is removed to form the first region S1 and the second region S2 on the front surface FS of the semiconductor substrate 110 The semiconductor substrate 110 can be formed.

7B, during the process of depositing the etching preventive film AEM on the rear surface BS of the semiconductor substrate 110, the semiconductor substrate 110 is bent so that the both ends of the semiconductor substrate 110 Lifting phenomenon from the support plate (HP) may occur.

The height BH of the semiconductor substrate 110 is determined by the temperature applied to the semiconductor substrate 110, the difference in thermal expansion coefficient between the semiconductor substrate and the anti-etching film AEM, the size of the semiconductor substrate 110, (The length in the two directions) and the thickness of the etching preventive film (AEM), and may be inversely proportional to the thickness of the semiconductor substrate 110.

Therefore, if the difference in thermal expansion coefficient, the size of the semiconductor substrate 110, the thickness of the semiconductor substrate 110, and the thickness of the etching preventive film AEM are determined in advance, during the process of depositing the etching preventive film AEM, The width WS2 'of the edge portion where the etching preventive film (AEM) is deposited can be controlled according to the temperature received by the substrate 110.

8, when the thickness of the semiconductor substrate 110 is 200 μm, the size of the semiconductor substrate 110 (length in the first and second directions) is 156.75 mm, and the thickness of the anti-etching film AEM to be deposited is 100 nm, And the lifting height (BH) of the substrate 110 with respect to the temperature was measured.

Referring to FIG. 8, it can be seen that the height BH of the semiconductor substrate 110 is proportional to the temperature of the semiconductor substrate 110 during the deposition process of the anti-etching film (AEM).

For example, when the temperature of the semiconductor substrate 110 received from the support plate HP during the deposition process is 25 ° C, which is approximately the same as the room temperature, the height BH at which the semiconductor substrate 110 is lifted at both ends is 0 mm , It can be seen that the semiconductor substrate 110 is not lifted substantially.

The height BH of the semiconductor substrate 110 is about 4 mm when the temperature of the semiconductor substrate 110 is about 550 ° C. At this time, The width WS2 of the edge portion at which the etch stopping film AEM is deposited on the front surface FS of the semiconductor substrate 110 becomes equal to or smaller than the width WS2 ' 'May be formed to be 2 mm or less.

As described above, according to the present invention, before the front surface FS of the semiconductor substrate 110 is textured, the temperature of the support plate HP is controlled during the process of depositing the anti-etching film AEM on the back surface BS of the semiconductor substrate 110 The height BH of the semiconductor substrate 110 can be controlled.

For example, when the temperature of the support plate HP is controlled to be between about 25 DEG C and 550 DEG C, the width WS2 'of the edge portion of the semiconductor substrate 110 can be set to 0 mm to 2 mm or less. At this time, since the edge portion is formed as the second region S2, the temperature of the support plate HP is set to be higher than 25 DEG C in order to perform a function as an alignment mark in the manufacturing process of the solar cell, WS2 ') is greater than 0 mm, but may be between 10 탆 and 50 탆.

The first region S1 and the second region S2 are formed on the front surface FS of the semiconductor substrate 110 and the width of the second region S2 is set to The second region S2 may be formed by various methods other than the method described above with reference to FIG. 7, and the width of the second region S2 WS2) can also be controlled through various methods.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Claims (12)

A semiconductor substrate containing an impurity of a first conductivity type;
An emitter section located on the front surface of the semiconductor substrate and containing an impurity of a second conductivity type opposite to the first conductivity type;
A tunnel layer located on a rear surface of the semiconductor substrate and including a dielectric material;
A rear electric field portion located on the rear surface of the tunnel layer and including a polycrystalline silicon material doped with impurities of the first conductive type at a higher concentration than the semiconductor substrate;
A first electrode connected to the emitter; And
And a second electrode connected to the rear electric field portion,
The front surface of the semiconductor substrate includes a first region having a first reflectance and a second region having a second reflectance higher than the first reflectance and surrounding the first region and positioned at a front edge portion of the semiconductor substrate and,
And the width of the second region is more than 0 mm and not more than 2 mm. The method according to claim 1,
And the width of the second region is between 10 탆 and 50 탆. The method according to claim 1,
Wherein the flatness of the second region is higher than the flatness of the first region. The method according to claim 1,
Wherein the first region is provided with a pyramid-shaped concavo-convexity, and the second region is formed with the pyramid-shaped concavo-convex. The method according to claim 1,
Further comprising an antireflection film made of a dielectric material on the front surface of the emitter,
Wherein a first reflectance of the first region is 5% or less in a state where the anti-reflection film is provided. The method according to claim 1,
And the second reflectance of the second region is between 20% and 30% in a state where the anti-reflection film is provided. The method according to claim 1,
Wherein a back surface reflectance of the semiconductor substrate is equal to a reflectance of the second region. The method according to claim 1,
Wherein the first electrode is located above the first region and not above the second region. The method according to claim 1,
Wherein the emitter portion and the antireflection film are located over the first region and the second region. The method according to claim 1,
And the thickness of the rear electric field portion is between 50 nm and 500 nm. The method according to claim 1,
And the thickness of the tunnel layer is between 0.5 nm and 2.5 nm. The method according to claim 1,
Wherein the tunnel layer is formed of SiOx or SiCx.

Images