KR20160046042A - Display device and timing controller - Google Patents

Abstract

Embodiments of the present invention relate to a display device and a timing controller which provide a way and a structure to monitor a situation in advance, that a panel burnt phenomenon can be occurred, thereby preventing the panel burnt phenomenon. The display device comprises: a display panel; a timing controller; and source driver integrated circuits.

Description

[0001] DISPLAY DEVICE AND TIMING CONTROLLER [0002]

The present invention relates to a display device and a timing controller.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display device (LCD), a plasma display panel (PDP) Various display devices such as an organic light emitting display device (OLED) and the like are being utilized.

Such a display device includes a display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged, a data driver for driving the plurality of data lines, a gate driver for driving the plurality of gate lines, A timing controller for controlling the data driver and the gate driver, and the like.

On the other hand, when a defect such as a malfunction of the source driver ICs included in the data driver occurs or a connection failure of a flexible flat cable (FFC) occurs, The voltage may not be supplied or an abnormal data voltage may be supplied.

In the case where the normal supply of the data voltage to the sub-pixel occurs, the display panel may not be normally driven. Particularly, in the case of an OLED display panel, a data voltage may not be supplied to a gate node of a driving transistor or an abnormal data voltage may be supplied while a driving voltage is applied to a source node or a drain node of the driving transistor.

In this case, an abnormal overcurrent flows to the corresponding sub-pixel, resulting in abnormal excessive light emission. In severe cases, a burst phenomenon of the display panel may occur.

It is an object of the present embodiments to provide a display apparatus and a timing controller which can prevent a panel bunting phenomenon by providing a method and structure for monitoring in advance a situation in which a panel bunting phenomenon may occur .

Another object of the present invention is to provide an organic light emitting diode in which a data voltage is not normally applied to a gate node of a driving transistor of a subpixel due to a data voltage undulation of a source driver integrated circuit, And to provide a display device and a timing controller capable of preventing a panel bunting phenomenon in advance through the monitoring of the panel bunting phenomenon.

One embodiment includes a display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged, a timing controller for transmitting data, a source for converting data into a data voltage, Driver integrated circuits, wherein at least one of the source driver integrated circuits transmits a lock signal indicative of a data reception state to a timing controller, the timing controller being responsive to a lock signal received from at least one of the source driver integrated circuits And executes a predetermined panel-bunching prevention process.

According to another embodiment of the present invention, there is provided a display device including a display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged, a timing controller for transmitting data, a source for converting data into a data voltage, Driver integrated circuits, wherein at least one of the source driver integrated circuits transmits a lock signal indicative of a data reception state to the timing controller, and the timing controller controls the timing of the lock signal received from at least one of the source driver integrated circuits And monitors whether there is a source driver integrated circuit that can not output a data voltage or outputs an abnormal data voltage among the source driver integrated circuits, and outputs a monitoring result.

Yet another embodiment provides a method of driving a semiconductor integrated circuit, comprising: a transmitter for transmitting data to source driver integrated circuits; a receiver for receiving a lock signal indicative of a data reception state from at least one of the source driver integrated circuits; And a panel-bust preventing unit for executing a predetermined panel-bust prevention process based on the received lock signal.

As described above, according to the embodiments, a method and structure for monitoring the situation in which the panel bunting phenomenon may occur can be provided in advance, and a display device and a timing controller .

In addition, according to the present embodiments, the data voltage is not normally applied to the gate node of the driving transistor of the sub-pixel due to the data voltage undesired output of the source driver integrated circuit, cable connection failure, etc., and an overcurrent flows to the organic light- The present invention provides a display device and a timing controller capable of preventing a panel bunting phenomenon in advance by monitoring a panel bunting phenomenon that may occur due to the occurrence of a panel bang phenomenon.

1 is a schematic system configuration diagram of a display apparatus according to the present embodiments.
2 is a diagram illustrating a subpixel structure of a display device according to the present embodiments.
FIG. 3 and FIG. 4 are diagrams showing abnormal light emission phenomenon of a subpixel due to a data voltage undesired power of a source driver integrated circuit and a panel bunting phenomenon in the display device according to the present embodiments.
5 is a block diagram of the timing controller of the display device according to the present embodiments.
6 is a diagram exemplarily showing a point-to-point (P2P) -based lock signal transmission method between the source driver integrated circuits and the timing controller in the display device according to the present embodiments.
FIG. 7 is an exemplary diagram of a state-voltage-level-based lock signal under the P2P-based lock signal transmission scheme in the display device according to the present embodiments.
8 is a diagram showing a state in which the source driver integrated circuits transmit the lock signal based on the status voltage level under the P2P based lock signal transmission method in the display device according to the present embodiments, Fig.
9 is a diagram exemplarily showing state-bit-based lock signals under a P2P-based lock signal transmission scheme in a display device according to the present embodiments.
Fig. 10 is a diagram showing a state in which the source driver integrated circuits transmit a state bit-based lock signal under the P2P-based lock signal transmission method in the display device according to the present embodiments, and the timing controller performs the panel- Fig.
11 and 12 are diagrams showing examples of a method for finally determining whether or not a source driver integrated circuit is defective under the P2P-based lock signal transmission method in the display device according to the present embodiments.
13 is a diagram exemplarily showing a cascade-based lock signal transmission method between the source driver integrated circuits and the timing controller in the display device according to the present embodiments.
14 is a diagram showing a state in which, in the display device according to the present embodiments, under the cascade lock signal transmission scheme, the source driver integrated circuits carry the state voltage level-based cascade lock signal, To the timing controller, and the timing controller executes the panel bunching prevention process based on the lock signal.
15 is an exemplary diagram of a state bit-based lock signal transmitted by a representative source driver integrated circuit to a timing controller under a cascade lock signal transmission scheme in a display device according to the present embodiments.
16 is a diagram showing a state in which, in the display device according to the present embodiments, under the cascade lock signal transmission scheme, each of the source driver integrated circuits carries a status bit-based cascade lock signal, To the timing controller, and the timing controller executes the panel bunching prevention process based on the lock signal.
17 and 18 are illustrations of a method for finally determining whether or not a source driver integrated circuit is defective under a cascade lock signal transmission system in a display device according to the present embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display apparatus 100 according to the present embodiments.

1, the display device 100 according to the present embodiment includes a display panel 110 having a plurality of data lines and a plurality of gate lines, a data driver 120 driving a plurality of data lines, A gate driver 130 for driving a plurality of gate lines, a timing controller 140 for controlling the data driver 120 and the gate driver 130, and the like.

In the display panel 110, a plurality of sub pixels (SP: Sub Pixel) are arranged, each sub pixel being arranged at a point where one data line intersects with one or more gate lines.

The timing controller 140 starts scanning according to the timing implemented in each frame and switches the image data input from the interface according to the data signal format used by the data driver 120 to output the converted image data Data And controls the data driving at a suitable time according to the scan.

The timing controller 140 controls various control signals such as a data control signal (DCS) and a gate control signal (GCS) to control the data driver 120 and the gate driver 130 Can be output.

Under the control of the timing controller 140, the gate driver 130 sequentially supplies the scan signals of the On voltage or the Off voltage to the plurality of gate lines to sequentially drive the plurality of gate lines .

The data driver 120 stores the inputted image data Data in a memory (not shown) under the control of the timing controller 140 and stores the image data Data in an analog form Into a data voltage (Vdata), and supplies the data to a plurality of data lines, thereby driving a plurality of data lines.

The data driver 120 includes a plurality of source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7), also referred to as a data driver IC SDIC # 0, SDIC # 1,..., SDIC # 7) may be formed by a tape automated bonding (TAB) method or a chip on glass (COG) May be connected to the bonding pad of the display panel 110 or may be directly disposed on the display panel 110 and may be integrated and disposed on the display panel 110 as occasion demands. In FIG. 1, the number of source driver integrated circuits is eight. However, this is only an example for convenience of explanation, and the number of source driver integrated circuits may be one or two or more.

The gate driver 130 may be located on one side of the display panel 110 as shown in FIG. 1 or on both sides of the display panel 110 divided into two, depending on the driving method.

Also, the gate driver 130 may include a plurality of gate driver ICs (GDIC # 0, GDIC # 1, ..., GDIC # 4) The circuits GDIC # 1 to GDIC # 4 are connected to bonding pads of the display panel 110 by tape automated bonding (TAB) or chip on glass (COG) Or may be implemented in a GIP (Gate In Panel) type and directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110, as the case may be. In FIG. 1, the number of gate driver integrated circuits is eight. However, the number of gate driver integrated circuits may be variously designed, and the number of gate driver integrated circuits may be as many as the number of gate lines.

1, one end and the other end of each of a plurality of source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) are connected to a display panel 110 and one or more source boards 150a, 150b.

Also, referring to FIG. 1, the timing controller 140 may be disposed on the control board 160.

The control board 160 and one or more source boards 150a and 150b are connected to each other through a flexible printed circuit (FPC), a flexible flat cable (FFC) 170a, .

1, SDIC # 0, SDIC # 1, SDIC # 2 and SDIC # 3 are connected to a first source board 170a together with two source boards 170a and 170b. The SDIC # 4, the SDIC # 5, the SDIC # 6, and the SDIC # 7 are included in the second group because they are connected to the second source board 170b together .

The display device 100 shown in FIG. 1 may include, for example, a liquid crystal display device (LCD), a plasma display device, an organic light emitting display device (OLED) ) Or the like.

In each of the subpixels arranged in the display panel 110, circuit elements such as transistors and capacitors are arranged. For example, when the display panel 110 is an organic light emitting display panel, circuit elements such as organic light emitting diodes, two or more transistors, and one or more capacitors are disposed in each pixel. Hereinafter, when the display panel 110 is an organic light emitting display panel, a subpixel structure will be exemplarily described.

2 is a diagram illustrating a subpixel structure of the display apparatus 100 according to the present embodiments.

As described above, two or more transistors and one or more capacitors may be disposed on a sub pixel of the organic light emitting display panel to drive the organic light emitting diode (OLED).

2 illustrates an example of a sub-pixel of a 2T (Capacitor) structure including two transistors T1 and T2 and one capacitor C1 in order to drive the organic light emitting diode OLED.

Referring to Figure 2,

The first transistor T1 receives a driving voltage EVDD from a first node N1 such as a source node or a drain node and supplies a current to the organic light emitting diode OLED to drive the organic light emitting diode OLED Is connected to a driving voltage line (DVL) for supplying a driving voltage (EVDD) or a pattern connected thereto and an organic light emitting diode (OLED) as a driving transistor.

The second transistor T2 is controlled by a scan signal applied through the gate line GL and is connected between the data line DL and the second node N2 of the first transistor T1 . The second transistor T2 is turned on and supplies the data voltage Vdata output to the corresponding source driver integrated circuit SDIC through the data line DL to the second node T1 of the first transistor T1 N2 so that the first transistor T1 can be turned on and off.

The first capacitor C1 is a storage capacitor connected between the first node N1 and the second node N2 of the first transistor T1 and for maintaining a constant voltage for one frame .

FIGS. 3 and 4 are diagrams showing an abnormal light emission phenomenon of the subpixel due to the data voltage undesired power of the source driver integrated circuit and the panel bunting phenomenon in the display device 100 according to the present embodiments.

Referring to FIG. 3, when the connection failure of the flexible flat cables 150a and 150b, defective or malfunction of the source driver integrated circuit, or the like occurs, the data voltage may not be supplied to the sub pixels.

As shown in FIG. 3, when the data voltage is not supplied to the sub-pixel, the driving voltage EVDD is applied to the first node N1 of the first transistor T1 corresponding to the driving transistor, The data voltage is not applied to the corresponding second node N2. As described above, when the second node N2 corresponding to the gate node of the first transistor T1 corresponding to the driving transistor floats, an abnormal current (overcurrent) flows to the organic light emitting diode OLED, The subpixel can perform abnormal light emission (and light emission).

As described above, due to various factors such as the data voltage undesirable output of the source driver integrated circuit (SDIC) or the malfunction of the flexible flat cable, the data voltage is not supplied to the subpixel, A current leaking phenomenon occurs in the display panel 110 and heat may be generated in a portion where the current leaning phenomenon occurs on the display panel 110. [

The heat generated on the display panel 110 may cause other structural changes such as a polarizing plate, and in a severe case, a burnt phenomenon of the display panel 110 may occur.

4 shows a case where data voltages are supplied from the two source driver integrated circuits (SDIC # 2 and SDIC # 5) in the case where the data voltages are not output from the two source driver integrated circuits (SDIC # 2 and SDIC # 5) And abnormal light emission occurs in the regions 400a and 400b in which sub pixel columns are arranged.

Accordingly, the embodiments disclose various methods and structures for preventing a panel-bunching phenomenon that may occur when a data voltage in a source driver integrated circuit (SDIC) is low.

The timing controller 140 included in the display device 100 according to the present embodiment can supply data to the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7).

In this case, when an EPI (Embedded Clock Point to Point Interface) interface standard is used, a clock signal can be transmitted in a signal representing data. That is, the signal may include data and a clock. In this case, no clock signal wiring is required. If a low voltage differential signal (LVDS) interface standard is used, clock signal wiring may be separately required. Hereinafter, it is assumed that signal transmission between the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) and the timing controller 140 is performed according to the EPI interface standard .

Each of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) receives a signal including data and a clock from the timing controller 140, Converts the data included in the signal received from the timing controller 140 into a data voltage, and outputs the data voltage to the corresponding data lines.

In order to monitor the possibility of a data voltage undesired phenomenon occurring in at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7), the source driver integrated circuits At least one of the SDIC # 0, SDIC # 1, ..., SDIC # 7 transmits a "lock signal" indicating the data reception state to the timing controller 140.

Here, the data reception state refers to whether or not a signal including data and a clock is received, or whether the data is normally acquired using a clock even if a signal is received. A state indicating whether data that can be output to the data lines is prepared and a state indicating whether a normal data voltage or an abnormal data voltage is output even if the data voltage is output. Such a data reception state includes a normal state in which a signal is normally received, data can be normally acquired, and a normal data voltage can be output through a digital-analog conversion procedure, and an abnormal state in which the data can not be output.

The timing controller 140 determines a predetermined "panel bunching prevention process" based on the lock signal received from at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # .

Here, the panel-bust prevention process includes, for example, a process as a final means for cutting off the power supply to the display apparatus 100, and the source driver ICs (SDIC # 0, SDIC # 7), if a phenomenon that a data voltage is not output at least in one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) is detected, In the future, it may include a process of storing the sensed result as a monitoring result in order to perform a power-off process as a final measure.

According to the above description, at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) detects a phenomenon in which the data voltage is not output, .

In the following, various methods and structures for preventing the panel bunting phenomenon will be described in detail with reference to the drawings.

First, a timing controller 140 that performs various control functions for preventing panel bunting will be described with reference to FIG.

5 is a block diagram of the timing controller 140 of the display apparatus 100 according to the present embodiments.

5, the timing controller 140 transmits a signal including data and a clock to each of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) (S) indicative of a data reception state from at least one of the driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7), and based on the received lock signal (s) It is monitored whether a source driver integrated circuit which can not output the data voltage or outputs the abnormal data voltage among the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) ).

Referring to FIG. 5, the timing controller 140 outputs a monitoring result and stores the monitoring result in the memory 540.

Referring to FIG. 5, the timing controller 140 outputs a power shutdown control signal to the power management unit 550 based on the monitoring result.

According to the above description, in order to prevent the occurrence of the panel bunting phenomenon in advance, it is preferable that at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # Or the like.

The internal configuration of the above-described timing controller 140 will be described with reference to Fig.

Referring to FIG. 5, the timing controller 140 includes a transmitter 510, a receiver 520, and a panel-bust preventing unit 530.

5, the transmitter 510 transmits a signal including data and a clock to each of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7).

5, the receiving unit 520 receives data from at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) receiving the signal including the data and the clock And receives a lock signal indicating the state.

5, the panel-bust prevention unit 530 generates a panel-bust prevention unit 530 based on a lock signal received from at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # Panel bang prevention process "

The timing controller 140 monitors the data reception state of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7), and according to the result, It is possible to prevent the panel bunting phenomenon according to the corresponding data reception state in advance.

5, the above-described panel-bust prevention unit 530 may be configured to prevent the panel-bust preventing unit 530 based on the lock signal received from one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # And monitors whether an abnormal data reception state has occurred in at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) SDIC # 1, ..., SDIC # 7) on the basis of the lock signals received from each of the SDICs # 1, ..., SDIC # And may store the monitoring result in the memory 540. [0054] FIG.

5, the panel-bust prevention unit 530 performs a panel-bust prevention process by outputting a power-off control signal to the power management unit 550, for example, .

The panel-bust prevention unit 530 refers to the monitoring result stored in the memory 540 in deciding whether to execute the power-off process corresponding to the panel bust prevention process, and determines whether or not to substantially execute the power-off process.

For example, referring to the monitoring result stored in the memory 540, if the data reception state of any one of the source driver ICs is continuously checked for a certain number of times or more or is continuously checked for a predetermined time, You can decide to actually run the process.

This is because even if a data reception state of any one of the source driver integrated circuits is abnormal, it may be a temporary phenomenon that can be normally recovered.

As described above, when it is determined that there is a possibility that the panel bunting phenomenon may occur based on the lock signal (s), the panel shut-off phenomenon can be prevented in advance by outputting the power cutoff control signal to the power management unit 550.

The timing controller 140 must receive the lock signal from at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) in order to execute the above-described panel bunting prevention process.

The present embodiments disclose two types of lock signal transmission methods including "Point-to-Point (P2P) -based lock signal transmission method" and "cascade-based lock signal transmission method".

First, the "P2P-based lock signal transmission method" is a method in which each of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # To the timing controller (140).

The source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) are connected to one or more groups according to a signal transmission path or a connected source board in connection with the "cascade- , And the source driver integrated circuits included in each group have a predetermined sequence. In each group, the last source driver integrated circuit (SDIC # 3 in case of group 1, SDIC # 3 in case of group 1, SDIC # (SDIC # 3 in case of group 1, SDIC # 7 in case of group 2) is transferred to the immediately preceding source driver integrated circuit (SDIC # When receiving the cascade lock signal from the SDIC # 2 in the case of the group 1 and the SDIC # 6 in the case of the group 2, the final lock signal is generated in consideration of the received lock signal and the data reception state of the received lock signal, 140).

SDIC # 0, SDIC # 1, SDIC # 2 and SDIC # 3 in the case of group 1, SDIC # 4, SDIC # 5 and SDIC # 6 in case of group 2) # 7), the cascade lock signal transmitted in the form of a cascade is the final lock signal transmitted by the last source driver integrated circuit in each group (SDIC # 3 in group 1, SDIC # 7 in group 2) In order to distinguish from the final lock signal transmitted by the last source driver integrated circuit (SDIC # 3 in case of group 1, SDIC # 7 in case of group 2) as the same type of lock signal, It was named after the term "cascade". That is, in this specification, only the final lock signal transmitted to the timing controller 140 is referred to as "lock signal ".

The last source driver integrated circuit (SDIC # 3 of group 1, SDIC # 7 of group 2) in each group is connected to the source driver integrated circuits (SDIC # 0, SDIC # 1, A source driver integrated circuit for transmitting a lock signal to the timing controller 140 among SDIC # 2 and SDIC # 3, and SDIC # 4, SDIC # 5, SDIC # 6 and SDIC # 7 in the case of group 2, Is also referred to as a " representative source driver integrated circuit (Representative SDIC) ".

On the other hand, the lock signal transmission wiring conforming to the above two types of lock signal transmission schemes can be disposed over the source boards 150a and 150b, the flexible flat cables 170a and 170b, and the control board 160 and the like. In some cases, a part of the lock signal transmission wiring may be arranged in a non-active area where an image is not displayed on the display panel 110. [

First, in the case of the P2P-based lock signal transmission method, the timing controller 140 in each of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # An individual lock signal line (ILSL) is used as a lock signal transmission line between each of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # Line is connected.

Next, in the case of the cascade-based lock signal transmission method, the source driver integrated circuits (SDIC # 0, SDIC # 1, SDIC # 2 and SDIC # 3 in the group 1, SDIC # (SDIC # 3 of group 1, SDIC # 7 of group 2) of the representative source driver integrated circuit (SDIC # 5, SDIC # 6 and SDIC # 7) A Representative Lock Signal Line (RLSL) is used as a lock signal transmission wiring between the representative source driver integrated circuit (SDIC # 3 of Group 1, SDIC # 7 of Group 2) and the timing controller 140, Lt; / RTI > In addition, a cascade signal line (CSL) is connected as a cascade lock signal transmission line between two adjacent source driver integrated circuits among the source driver integrated circuits.

Hereinafter, a method for preventing panel banging and a structure for preventing the panel bang under a P2P-based lock signal transmission method will be described in detail first, and a method for preventing panel banging and a structure therefor will be described in detail below with reference to a cascade lock signal transmission method.

Hereinafter, for convenience of description, it is assumed that the data reception states of the SDIC # 2 and the SDIC # 5 are in an abnormal state as illustrated in FIG. It is also assumed that the abnormal data reception state of the SDIC # 2 is a temporary phenomenon and the abnormal data reception state of the SDIC # 5 is a permanent phenomenon.

6 is a diagram illustrating a P2P-based lock signal transmission between the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) and the timing controller 140 in the display device 100 according to the present embodiments Fig.

Referring to FIG. 6, the individual lock signal lines ILSL # 0, ILSL # 1, ..., ILSL # 7 are locked by the lock signal for transmitting the lock signal according to the P2P- And is used as a transmission wiring.

Referring to FIG. 6, the source driver integrated circuits SDIC # 0, SDIC # 1, ..., SDIC # 7 are connected to the individual lock signal lines ILSL # 0 ILSL # 1, ..., ILSL # And is connected to the timing controller 140.

That is, the ILSL # 0 connects the SDIC # 0 and the timing controller 140. The ILSL # 1 connects the SDIC # 1 and the timing controller 140. The ILSL # 2 connects the SDIC # 2 and the timing controller 140. The ILSL # 3 connects the SDIC # 3 and the timing controller 140. The ILSL # 4 connects the SDIC # 4 and the timing controller 140. The ILSL # 5 connects the SDIC # 5 and the timing controller 140. The ILSL # 6 connects the SDIC # 6 and the timing controller 140. The ILSL # 7 connects the SDIC # 7 and the timing controller 140.

The source driver ICs SDIC # 0, SDIC # 1, ..., and SDIC # 7 are connected to the individual lock signal interconnects ILSL # 0, ILSL # LS # 1, ..., LS # 7 indicating their own data reception states to the timing controller 140 via the RS # 1.

The source driver ICs SDIC # 0, SDIC # 1, ..., and SDIC # 7 are connected to each other using the individual lock signal wires ILSL # 0, ILSL # ) Can individually inform their respective data reception states. Thus, the timing controller 140 can correctly know the data reception state of each of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7).

On the other hand, each of the lock signals LS # 0, LS # 1, ..., LS # 7 transmitted via the individual lock signal wires ILSL # 0, ILSL # 1, ..., ILSL # (Status Voltage Level) corresponding to the status of the data, or a Status Bit indicating the status of data reception.

As described above, the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) ) Or the status bit-based lock signals (LS # 0, LS # 1, ..., LS # 7) can be transmitted, thereby providing various lock signal transmission systems suited to the system environment of the display apparatus 100 I can do it. That is, depending on the system environment, it is possible to use the lock signal based on the state voltage level or to use the state bit based lock signal, thereby improving the system adaptability.

In the following, a method for preventing panel bunting will be described using a lock signal based on a status voltage level or a lock signal based on a status bit under a P2P-based lock signal transmission system. First, a method for preventing panel bunting will be described using a lock signal based on the state voltage level under a P2P-based lock signal transmission system.

7 is an exemplary diagram of a state-voltage level-based lock signal under the P2P-based lock signal transmission method in the display device 100 according to the present embodiments.

Referring to FIG. 7, the lock signal based on the state voltage level may have a specific state voltage level.

Referring to FIG. 7, the lock signal may be a high level voltage or a low level voltage. Here, the high level voltage means a normal data reception state and the low level voltage means an abnormal data reception state. The high level voltage is a value designed in advance as a voltage which is as high as a constant voltage based on a reference voltage (Reference Voltage). The low level voltage may be a reference voltage or a voltage lower than the high level voltage by a predetermined voltage and is a pre-designed value.

4, SDIC # 2 and SDIC # 5 are in an abnormal state, and SDIC # 0, SDIC # 1, SDIC # 3, SDIC # 4, SDIC # 7 are in a normal state, the lock signal LS # 2 transmitted to the SDIC # 2 and the lock signal LS # 5 transmitted from the SDIC # 5 have low level state voltage levels, and the SDIC # The lock signal LS # 0 transmitted to the SDIC # 1, the lock signal LS # 1 transmitted to the SDIC # 1, the lock signal LS # # 4), the lock signal LS # 6 transmitted to the SDIC # 6 and the lock signal LS # 7 transmitted to the SDIC # 7 have the state voltage level of the high level.

8 is a diagram showing a state in which the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) in the display device 100 according to the present embodiment are set to the state voltage level Based on the lock signals LS # 0, LS # 1, ..., LS # 7, and the timing controller 140 transmits the lock signals LS # And executes the panel bunting prevention process.

8, the individual lock signal wires ILSL # 0, ILSL # 1, ..., ILSL # 7 are connected to the source driver ICs (SDIC # 0, SDIC # The timing controller 140 determines that the individual lock signal lines LS # 0, LS # 1, ..., and LS # LS # 0, LS # 1, ..., LS # 7 via the control signals ILSL # 0, ILSL # 1, ..., ILSL # 1, ..., LS # 7) is a high-level voltage corresponding to a normal data reception state or a low-level voltage corresponding to an abnormal data reception state and outputs the confirmed result (all the source driver integrated circuits (ILSL # 0, ILSL # 1, ..., ILSL # 7), together with identification information and data reception status information for each of the source driver integrated circuits The beam, or a source driver integrated circuit (SDIC # 0, SDIC # 1, ..., SDIC # 7) can be stored in the memory 540 as the results of monitoring the respective identification information.

At this time, the timing controller 140 checks the data reception state of all the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) (SDIC # 0, SDIC # 1, ..., SDIC # 7) of each of the source driver integrated circuits (ILSL # 0, ILSL # 1, ..., ILSL # It is possible.

Alternatively, the timing controller 140 may supply the low level voltage lock signal LS # corresponding to the abnormal data reception state among all the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 2 and LS # 5) of the low level voltage together with the confirmation result (information indicating that the data reception state of the SDIC # 2 and the SDIC # 5 is abnormal) (SDIC # 2, SDIC # 5) that has transmitted the identification information of each of the individual lock signal wires (ILSL # 2, ILSL # 5) or the lock signal of the low level voltage .

As described above, the lock signals (LS # 0, LS # 1, ..., LS # 7) transmitted from the source driver integrated circuits (SDIC # 0, SDIC # It is checked whether the data reception state of each of the source driver integrated circuits SDIC # 0, SDIC # 1, ..., SDIC # 7 is normal or abnormal, It is possible to identify the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) or the source driver integrated circuits (SDIC # 2 and SDIC # 5) (SDIC # 2, SDIC # 5) in an abnormal data receiving state by storing the data in the memory 540 in the memory 540. This helps to determine whether to execute the panel bust prevention process You can give.

8, the timing controller 140 receives the lock signals LS # 0 and LS # 0 received from the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 1,..., LS # 7) corresponding to the statuses of the statuses (corresponding to the data reception status).

Referring to FIG. 8, the timing controller 140 performs monitoring several times, that is, the timing of the lock signals (SDIC # 0, SDIC # 1, ..., SDIC # (Identification information of each SDIC and data reception status information, or identification information of the SDIC in an abnormal data reception state) by receiving the monitoring results (LS # 0, LS # 1, LS # It is possible to store it in the memory 540 and refer to the monitoring result information to determine whether to execute the panel prevention process.

8, the timing controller 140 receives the lock signals LS # 0, LS # 0, ... received from the source driver ICs (SDIC # 0, SDIC # When the lock signal having the state voltage level corresponding to the abnormal state is consistently checked for a predetermined number of times or more for a predetermined time or longer from among the LS # 1, ..., LS # 7.

As described above, the timing controller 140 receives the lock signals LS # 0 and LS # 1 received once from the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # ,..., LS # 7), it is possible to determine whether or not there is a source driver integrated circuit having an abnormal data reception state by checking whether or not there is a source driver integrated circuit having an abnormal data reception state, In the case where it is confirmed that a source driver integrated circuit showing a temporary and one-time abnormal data reception state exists by executing the panel bunting prevention process only when it is continuously checked for a predetermined number of times or more for a predetermined time or more, It is possible to prevent the boot process from being executed, and it is possible to prevent the source driver < RTI ID = 0.0 > If the circuit only can be controlled to run at the panel bunt prevention process.

On the other hand, the timing controller 140 can execute the panel bunching prevention process by outputting the power supply cut-off control signal of the display device 100 to the power management unit 550 in executing the panel bunching prevention process.

Thus, by turning off the power supply to the display device 100 by outputting the power-off control signal, at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # The gate node N2 of the first transistor T1 corresponding to the driving transistor in any sub-pixel is floated and an abnormal overcurrent flows to the organic light emitting diode OLED so that the sub-pixel emits abnormal light It is possible to prevent the display panel 110 from being burnt.

Hereinafter, with reference to FIG. 9 and FIG. 10, a method of preventing panel banging will be described using a state bit-based lock signal under a P2P-based lock signal transmission scheme.

9 is a diagram exemplarily showing state-bit-based lock signals under the P2P-based lock signal transmission scheme in the display device 100 according to the present embodiments.

9, under the P2P-based lock signaling scheme, each of the status bit-based lock signals is basically composed of source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) And a status bit indicating a data reception state of the mobile station.

For example, if the status bit is 1, it means a normal data reception state, and if the status bit is 0, it means an abnormal data reception state.

The state bits included in the lock signals LS # 2 and LS # 5 transmitted from the SDIC # 2 and the SDIC # 5 are set to be "0" because the data reception states of the SDIC # 2 and the SDIC # LS # 0, LS # 1, and LS # 0 transmitted from the remaining source driver integrated circuits (SDIC # 0, SDIC # 1, SDIC # 3, SDIC # 4, SDIC # # 3, LS # 4, LS # 6, and LS # 7) is 1.

, ILSL # 7, ILSL # 0, ILSL # 1, ..., ILSL # 7 by the source driver integrated circuits (SDIC # 0, SDIC # , LS # 0, LS # 1, ..., LS # 7) transmitted through the mobile station MS includes a status bit indicating the data reception state,

Is transmitted through the individual lock signal interconnects ILSL # 0, ILSL # 1, ..., ILSL # 7 by the source driver integrated circuits SDIC # 0, SDIC # 1, ..., SDIC # Each of the lock signals LS # 0, LS # 1, ..., LS # 7 includes, in addition to a status bit, a status bit (ID bit) of the source driver integrated circuit (SDIC) as an option.

Here, the identification information (ID bit) must have the number of bits for identifying all of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7).

In this specification, since three source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) are taken as an example, three bits are required as identification information (ID bits). 9, SDIC # 0 is 000, SDIC # 1 is 001, SDIC # 2 is 010, SDIC # 3 is 011, SDIC # 4 is 100, SDIC # 5 is 101 SDIC # 6 is 110, SDIC # 7 is 111, and so on.

, ILSL # 7, ILSL # 0, ILSL # 1, ..., ILSL # 7 by the source driver integrated circuits (SDIC # 0, SDIC # Each of the lock signals LS # 0, LS # 1, ..., and LS # 7 transmitted through the source driver integrated circuit is selectively provided with the identification information (also referred to as "ID bits" The timing controller 140 can identify the source driver integrated circuit in an abnormal data reception state.

10 is a diagram showing a state in which the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) in the display device 100 according to the present embodiment The timing controller 140 transmits the lock signals LS # 0, LS # 1, ..., LS # 7, Fig. 7 is a diagram illustrating an example of executing the panel bang prevention process based on the panel bang prevention process.

10, the data reception states of SDIC # 2 and SDIC # 5 among the eight source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) LS # 0 transmitted from SDIC # 0 through ILSL # 0 is 0001, LS # 1 transmitted from SDIC # 1 through ILSL # 1 is 0011, and ILSL # 2 is 0100, LS # 3 transmitted from SDIC # 3 through ILSL # 3 is 0111, LS # 4 transmitted from SDIC # 4 via ILSL # 4 is 1001, and SDIC # LS # 5 transmitted from ILIC # 5 through ILSL # 5 is 1010, LS # 6 transmitted from SDIC # 6 through ILSL # 6 is 1101, and LS # 7 transmitted from SDIC # 7 through ILSL # to be.

10, the timing controller 140 controls the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 1) through the individual lock signal wires ..., and LS # 7) received from the respective lock signals (LS # 0, ..., SDIC # 7) (SDIC # 2, SDIC # 5) or the flexible flat cables 150a and 150b corresponding to the defective occurrence position or the source driver integrated circuit (SDIC # 2, SDIC # Identification information for the bonding pad or data line or subpixel column may be stored in the memory 540 as a monitoring result.

As described above, the timing controller 140 receives a status bit (e.g., a 1-bit backward digit) and identification information (e.g., 1 bit) from the lock signals LS # 0, LS # (SDIC # 2, SDIC # 5) or the flexible flat cables 150a and 150b or bonding pads or data lines or data lines corresponding to the defect occurrence position By storing the identification information on the pixel column in the memory 540 as a monitoring result, if there is a phenomenon of abnormal data voltage output to the subpixel or an abnormal data voltage output phenomenon, it is easy and easy to grasp the position of the abnormal data voltage output .

10, the timing controller 140 receives the lock signals LS # 0, LS # 1, ..., LS # 1 received from the source driver ICs (SDIC # 0, SDIC # If at least one of the lock signals LS # 2 and LS # 5 including the status bits corresponding to the abnormal status is continuously checked for a predetermined number of times or more for a predetermined time or more, .

Accordingly, the timing controller 140 receives the lock signals (LS # 0, LS # 1, ..., LS) received from the source driver ICs (SDIC # 0, SDIC # # 7), the existence of a source driver integrated circuit having an abnormal data reception state is not immediately detected, but the presence of an abnormal data reception state is continuously maintained In the case where it is confirmed that there is a source driver integrated circuit showing a temporary and one-time abnormal data reception state by executing the panel bunting prevention process only when the number of times is more than or equal to a predetermined time, unnecessary panel bunting prevention process Can be prevented from being executed, and the source driver integrated circuit having a permanent abnormal data receiving state It is possible to control so that the panel bust prevention process is executed only.

On the other hand, the timing controller 140 can execute the panel bunching prevention process by outputting the power supply cut-off control signal of the display device 100 to the power management unit 550 in executing the panel bunching prevention process.

Thus, by turning off the power supply to the display device 100 by outputting the power-off control signal, at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # The gate node N2 of the first transistor T1 corresponding to the driving transistor in any sub-pixel is floated and an abnormal overcurrent flows to the organic light emitting diode OLED so that the sub-pixel emits abnormal light It is possible to prevent the display panel 110 from being burnt.

11 and 12 are diagrams for explaining the operation of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) under the P2P-based lock signal transmission method in the display device 100 according to the present embodiments. And an example of a method for finally determining whether or not a fault occurs.

11, the timing controller 140 receives the lock signals LS # 0, LS # 1, ..., LS # 0 received from the source driver ICs (SDIC # 0, SDIC # At least one lock signal having a state bit (0) corresponding to an abnormal state or a state voltage level (low level voltage) corresponding to an abnormal state among a plurality of times (for example, four times) It is determined that the abnormal data reception state of the corresponding source driver integrated circuit is permanently determined and the source driver integrated circuit is finally determined as a fault.

If the lock signal having the state bit (0) corresponding to the abnormal state or the state voltage level (low level voltage) corresponding to the abnormal state is confirmed, the timing controller (140) ), And when the status bit of the lock signal changes back to the bit value (1) corresponding to the steady state or when the status voltage level of the lock signal changes back to the high voltage level corresponding to the normal state again, It is determined that the abnormal data reception state of the driver integrated circuit is temporary and temporary, and the corresponding source driver integrated circuit is not finally determined as a fault.

For example, in the case of SDIC # 2 in FIG. 11, the lock signal LS # having the status bit 0 indicating the abnormal data reception state for four consecutive times or having the state voltage level (low level voltage) corresponding to the abnormal state, 2, the timing controller 140 can finally determine that a permanent failure has occurred to the extent that the panel-bust prevention process needs to be executed in the SDIC # 2.

On the other hand, in the case of SDIC # 5, the lock signal LS # 5 including the status bit 0 indicating the abnormal data reception state for three consecutive times or the state voltage level (low level voltage) corresponding to the abnormal state is transmitted , A lock signal LS # 5 having a state bit (1) indicating a normal data reception state at the fourth time corresponding to the threshold number of times (4) or having a state voltage level (high voltage level) indicating a normal data reception state The timing controller 140 can finally determine that a permanent failure has not occurred to such an extent that the panel-bunching prevention process must be executed in the SDIC # 5.

12, the timing controller 140 uses the timer 1200 to determine a state corresponding to an abnormal state from the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) (LS # 0, LS # 1, ..., LS # 7) having the state voltage level (low level voltage) corresponding to the abnormal state or including the bit 0 is continuously received for a certain period of time If it is judged that the abnormal data reception state of the corresponding source driver integrated circuit is permanent and the corresponding source driver integrated circuit is judged to be the final one in case of a predetermined period of time (for example, 100 ms) .

If the timing controller 140 receives a state bit 0 corresponding to an abnormal state from the source driver ICs SDIC # 0, SDIC # 1, ..., SDIC # 7 using the timer 1200, (LS # 0, LS # 1, ..., LS # 7) having a state voltage level (low level voltage) corresponding to an abnormal state are continuously received for a certain period of time, If the determined duration is less than a predetermined time, the abnormal data reception state of the corresponding source driver integrated circuit is determined to be temporary, and the source driver integrated circuit is not finally determined as a fault.

For example, in the case of SDIC # 2 in FIG. 12, a lock signal LS (low level voltage) including a status bit 0 indicating an abnormal data reception state for a predetermined period of time or having a state voltage level # 2, the timing controller 140 can finally determine that a permanent failure has occurred to the extent that the panel-bust prevention process needs to be executed in the SDIC # 2.

On the other hand, in the case of the SDIC # 5, the lock signal LS # 5 including the state bit 0 indicating the abnormal data reception state or the state voltage level (low level voltage) corresponding to the abnormal state is transmitted several times When the predetermined period of time has elapsed, since the lock signal LS # 5 including the status bit (1) indicating the normal data reception state and having the state voltage level (high voltage level) corresponding to the normal data reception state is transmitted, 140 can finally determine that a permanent failure has not occurred to such an extent that the panel bunting prevention process must be executed in SDIC # 5.

By finally determining that a defect has occurred in one SDIC # 5 among all the eight source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) as in the example of FIGS. 11 and 12, It is possible to execute the panel bunting prevention process for cutting off the power supply to the apparatus 100 and to replace the defective SDIC # 5 or the related structure.

In the above description, all the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) transmit the lock signals LS # 0, LS # Under the P2P lock signal transmission method, the panel bang prevention method has been described.

In the following, only one or a part of all the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) transmits a lock signal to the timing controller 140 as a representative, And the remaining source driver integrated circuits transmit a cascade lock signal to each other.

13 is a diagram illustrating a cascade-based lock signal transmission between the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) and the timing controller 140 in the display device 100 according to the present embodiment Fig.

13, the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) are classified into at least one group, and the timing controller There is one representative source driver integrated circuit for transmitting the lock signal to the source driver IC 140. [

Thus, in the case of the cascade lock signal transmission method, each of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) outputs a lock signal to the timing controller 140 like a P2P lock signal transmission method Only the source driver integrated circuit of some of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) transfers the lock signal to the timing controller 140, The number of signal transfers and the number of signal lines between the integrated circuit and the timing controller 140 can be reduced.

In the following description, it is assumed that the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) are classified into the first group and the second group according to the connection with the source board, SDIC # 4, SDIC # 1, SDIC # 1, SDIC # 2 and SDIC # 3 (representative SDIC) are included in the first group and SDIC # .

In this way, when the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) are classified into two groups (first group and second group) 3 is a first group representative source driver integrated circuit for transmitting the lock signal LS # G1 to the timing controller 140. In the second group, SDIC # 7 transfers the lock signal LS # G2 to the timing controller 140 To the second group of source driver ICs. Here, the number of representative source driver integrated circuits can be determined according to the number of groups or the number of source boards.

13, one or more representative source driver ICs (SDIC # 3, SDIC # 7) of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # (Representative Lock Signal Line # 3, RLSL # 7) are connected to each other in groups.

13, only the SDIC # 3 and the SDIC # 7 corresponding to the representative source driver integrated circuits of the first group and the second group transmit the lock signals LS # G1 and LS # G2 to the timing controller 140 do. That is, in the first group, the SDIC # 3 corresponding to the representative source driver integrated circuit of the first group transfers the lock signal LS # G1 to the timing controller 140. In the second group, the SDIC # 7 corresponding to the representative source driver IC of the second group transfers the lock signal LS # G2 to the timing controller 140.

All of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) do not transfer the lock signal to the timing controller 140, and only a part of the source driver IC By transmitting the lock signal to the timing controller 140, the analysis amount of the lock signal of the timing controller 140 can be reduced. In addition, the number of wiring lines for transferring the lock signal between the source driver integrated circuit and the timing controller 140 can be reduced.

13, between the two source driver integrated circuits in the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7), cascade signal lines (CSL Line # 01, CSL # 12, CSL # 23, CSL # 45, CSL # 56, and CSL # 67.

Accordingly, the source driver ICs (SDIC # 0, SDIC # 1, SDIC # 2 and SDIC # 3 in the first group, SDIC # 4, SDIC # 5 and SDIC # (In the case of the first group, SDIC # 3, in the case of the second group, SDIC # 4) in the first source driver integrated circuit (SDIC # (CSL # 01, CSL # 12, CSL # 23, CSL # 45, CSL # 56, and CSL # 67) sequentially to the representative source driver integrated circuit which is the SDIC # (CLS # 0, CLS # 1, CLS # 2, CLS # 4, CLS # 5, CLS # 6)

Therefore, the representative source driver integrated circuit (SDIC # 3 in the case of the first group, SDIC # 7 in the case of the second group) is connected to the previous source driver integrated circuit (in the case of the first group, SDIC # (In the case of the first group, the CLS # 2, the second group, the second group, and the second group) via the cascade signal wiring (CSL # (In the case of the first group, LS # 1), the lock signal is transmitted through the representative lock signal wiring (RLSL # 3 in the first group, RLSL # 7 in the second group) G1 for the first group and LS # G2 for the second group) to the timing controller 140. [

Referring back to FIG. 13, in the first group, the SDIC # 0 corresponding to the first source driver IC transfers CLS #O indicating its data reception state to the SDIC # 1 through the CSL # 01 .

In the first group, the SDIC # 1 corresponding to the second source driver integrated circuit transfers CLS # 1 indicating the data reception state to the SDIC # 2 through the CSL # 12. Here, the data reception state indicated by the CLS # 1 is determined by the data reception state of the SDIC # 1 when the data reception state indicated by the CLS #O is normal. If the data reception state indicated by the CLS #O is abnormal, Irrespective of the data reception state of # 1, an abnormal data reception state is obtained. That is, when the cascade lock signal CLS # 0 transmitted from the previous SDIC # 0 indicates an abnormal data reception state, the SDIC # 1 transfers CLS # 1 indicating an abnormal data reception state to the next SDIC # 2, 1 indicating the data reception state of its own is transmitted to the next SDIC # 2 when the cascade lock signal CLS # 0 transmitted from the SDIC # 0 of the SDC # 0 indicates the normal data reception state.

In the same manner, in the first group, the SDIC # 2 corresponding to the third source driver integrated circuit transfers CLS # 2 indicating the data reception state to the SDIC # 3 through the CSL # 23.

Similarly, in the first group, SDIC # 3, which is a representative source driver integrated circuit corresponding to the last source driver integrated circuit, outputs CLS # 3 indicating the data reception state as a lock signal LS # G1 through RLSL # (140).

Referring to FIG. 13, in the second group, SDIC # 4 corresponding to the first source driver integrated circuit transfers CLS # 4 indicating its data reception state to SDIC # 5 through CSL # 45.

In the second group, the SDIC # 5 corresponding to the second source driver integrated circuit transfers the CLS # 5 indicating the data reception state to the SDIC # 6 through the CSL # 56. Here, the data reception state indicated by the CLS # 5 is determined by the data reception state of the SDIC # 5 when the data reception state indicated by the CLS # 4 is normal. If the data reception state indicated by the CLS # 4 is abnormal, Irrespective of the data reception state of # 5, an abnormal data reception state is obtained. That is, when the cascade lock signal CLS # 4 transmitted from the previous SDIC # 4 indicates an abnormal data reception state, the SDIC # 5 transfers CLS # 5 indicating the abnormal data reception state to the next SDIC # 6, The CLS # 5 indicating its own data reception state is transferred to the next SDIC # 6 when the cascade lock signal CLS # 4 transmitted from the SDIC # 4 of the SDIC # 4 indicates a normal data reception state.

In the same manner, in the second group, the SDIC # 6 corresponding to the third source driver integrated circuit transfers CLS # 6 indicating the data reception state to the SDIC # 7 through the CSL # 67.

Similarly, in the second group, SDIC # 7, which is the representative source driver integrated circuit corresponding to the last source driver integrated circuit, outputs CLS # 7 indicating the data reception state as lock signal LS # G2 through RLSL # (140).

Even if only a part of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) transmits the lock signals indicating the data reception state to the timing controller 140, It is possible to provide a signal transmission system capable of informing the timing controller 140 of the overall data reception state of the circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) and a signal wiring structure therefor.

Similarly to the P2P lock signal transmission system, in the cascade lock signal transmission system, the lock signal transmitted to the timing controller 140 may be a state voltage level lock signal or a state bit based lock signal.

In other words, the lock signals (LS # G1 and LS # G2) transmitted to the timing controller 140 through the representative lock signal lines (RLSL # 3 and RLSL # 7) It is determined whether the data reception states of all the source driver integrated circuits (SDIC # 0 to SDIC # 3 in the first group, SDIC # 4 to SDIC # 7 in the second group) are normal, At least one of the source driver integrated circuits (SDIC # 0 to SDIC # 3 in the first group, SDIC # 4 to SDIC # 7 in the second group) becomes a state voltage level indicating that the data reception state is abnormal Can be.

The lock signals LS # G1 and LS # G2 transmitted to the timing controller 140 through the representative lock signal lines RLSL # 3 and RLSL # 7 are the state bit-based lock signals, And a status bit indicating the data reception status for each of the source driver integrated circuits (SDIC # 0 to SDIC # 3 in the first group, SDIC # 4 to SDIC # 7 in the second group).

As described above, under the cascade-based lock signal transmission system, it is possible to transmit the lock signal LS # G1, LS # G2 based on the status voltage level or the lock signal LS # G1, LS # G2 based on the status bit It is possible to provide a variety of lock signal transmission systems suitable for the system environment of the display apparatus 100. [ That is, depending on the system environment, it is possible to use the lock signal based on the state voltage level or to use the state bit based lock signal, thereby improving the system adaptability.

In the following, a method for preventing panel bunting will be described using a lock signal based on a state voltage level or a lock signal based on a state bit under a cascade-based lock signal transmission system. First, a panel burst prevention method will be described using a lock signal based on a state voltage level under a cascade-based lock signal transmission system.

FIG. 14 is a diagram showing a state in which in the display device 100 according to the present embodiments, under the cascade lock signal transmission scheme, the source driver integrated circuits carry the state voltage level-based cascade lock signal and the representative source driver integrated circuit (SDIC # 3 in the case of the second group, SDIC # 7 in the case of the second group) transmits the lock signal LS # G1, LS # 2 based on the state voltage level to the timing controller 140, And executes the panel bunting prevention process based on the signals LS # G1 and LS # 2.

As described above, the data reception states of the SDIC # 2 and the SDIC # 5 are abnormal and the data reception states of the remaining SDIC # 0, SDIC # 1, SDIC # 3, SDIC # 4, SDIC # It is assumed that all are normal.

Therefore, as shown in Fig. 14, in the first group, the SDIC # 0 outputs the cascade lock signal CLS # 0 having the state voltage level of the high voltage level indicating the normal data reception state through the cascade signal line CSL # 01 SDIC # 1.

Since the CLS # 0 transmitted through the CSL # 01 has the state voltage level of the high voltage level, the SDIC # 1 receives the CLS # 0 having the state voltage level of the high voltage level indicating the normal data receiving state, # 1 to SDIC # 2 via CSL # 12.

Since the CLS # 1 transmitted through the CSL # 12 has the state voltage level of the high voltage level, the SDIC # 2 has the state voltage level of the low voltage level indicating the abnormal data reception state in accordance with its own data reception state And transmits CLS # 2 to SDIC # 3 through CSL # 23.

Since the CLS # 2 transmitted through the CSL # 23 has the state voltage level of the low voltage level, the SDIC # 3 corresponding to the representative source driver integrated circuit in the first group has the abnormality CLS # 3 having the state voltage level of the low voltage level indicating the data reception state is transmitted as the first group of lock signal LS # G1 to the timing controller 140 via the representative lock signal wiring RLSL # 3.

Further, in the second group, the SDIC # 4 corresponding to the first source driver integrated circuit receives the cascade signal CLS # 4 having the state voltage level of the high voltage level indicating the normal data reception state to the cascade signal line CSL # 45 To SDIC # 5.

Since the CLS # 4 transmitted through the CSL # 45 has the state voltage level of the high voltage level, the SDIC # 5 has the CLS # 4 having the state voltage level of the low voltage level indicating the abnormal data reception state, # 5 to the SDIC # 6 through the CSL # 56.

Since the CLS # 5 transmitted through the CSL # 56 has the state voltage level of the low voltage level indicating the abnormal data reception state, the SDIC # 6 generates the low voltage indicating the abnormal data reception state Level to the SDIC # 7 through the CSL # 67.

The SDIC # 7 corresponding to the representative source driver integrated circuit in the second group has the state voltage level of the low voltage level transmitted through the CSL # 67, so that the SDIC # CLS # 7 having the state voltage level of the low voltage level indicating the data reception state is transmitted as the second group of lock signal LS # G2 to the timing controller 140 via the representative lock signal wiring RLSL # 7.

Referring to FIG. 14, the timing controller 140 performs monitoring several times, that is, when the lock signals LS # G1 and LS # 2 transmitted from the representative source driver ICs SDIC # 3 and SDIC # The monitoring result information (status voltage level information and group information of the lock signal, etc.) is stored in the memory 540, and the monitoring result information is referred to to determine whether to execute the panel prevention process You can decide.

14, referring to the monitoring results stored in the memory 540, the timing controller 140 receives from the representative source driver ICs (SDIC # 3, SDIC # 7) for each group a state voltage Level of the lock signals LS # G1 and LS # G2 is continuously checked for a certain number of times or more for a predetermined time or more, the panel booting prevention process can be executed.

In this manner, the timing controller 140 generates an abnormal data reception state (state) based on the lock signals LS # G1 and LS # G2 received once from the representative source driver ICs SDIC # 3 and SDIC # In the case where the existence of the source driver integrated circuit having an abnormal data reception state has been continuously checked for a certain number of times or more or for a predetermined time or longer instead of immediately executing the panel bunting prevention process by confirming the presence of the source driver integrated circuit having the abnormal data reception state It is possible to prevent the unnecessary panel booting prevention process from being executed and to prevent the permanent booting process from being performed when a source driver integrated circuit that is temporarily and one-time- If there is a source driver integrated circuit in an abnormal data reception state It is possible to control so that the UMAN only panel boot prevention process is executed.

Referring to Fig. 14, the timing controller 140 outputs a power-off control signal for the display device 100 to the power management unit 550, thereby executing the panel-bust prevention process.

Thus, by turning off the power supply to the display device 100 by outputting the power-off control signal, at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # The gate node N2 of the first transistor T1 corresponding to the driving transistor in any sub-pixel is floated and an abnormal overcurrent flows to the organic light emitting diode OLED so that the sub-pixel emits abnormal light It is possible to prevent the display panel 110 from being burnt.

Hereinafter, with reference to FIG. 15 and FIG. 16, a panel burst prevention method will be described using a state-bit-based lock signal under a cascade-based lock signal transmission scheme.

15 is a diagram showing a state bit-based (non-volatile) state in which the representative source driver ICs (SDIC # 3, SDIC # 7) transfers to the timing controller 140 in the display device 100 according to the present embodiment under the cascade lock signal transmission scheme. And is an example of the lock signals LS # G1 and LS # G2.

15, representative source driver integrated circuits (SDIC # 3 in the first group, SDIC # 7 in the second group) in each group are connected to the representative lock signal wiring RLSL # 3 in the cascade lock signal transmission system, (LS # G1 in the case of the first group and LS # G2 in the case of the second group), which are transmitted to the timing controller 140 via the RBSL # 3 and the RLSL # 7, (1: normal, 0: abnormal) for each of the integrated circuits (SDIC # 0 to SDIC # 3 in the case of the first group and SDIC # 4 to SDIC # 7 in the case of the second group).

15, the representative source driver ICs (SDIC # 3 in the first group, SDIC # 7 in the second group) in each group are connected to the representative lock signal lines RLSL # 3 and RLSL # 7 Group source driver ICs (first group) included in the state bit-based lock signal (LS # G1 in the first group, LS # G2 in the second group) The status bits indicating the data reception status for each of the SDIC # 0 to SDIC # 3 in the case of the group 1 and the SDIC # 4 to SDIC # 7 in the case of the second group are the same as those in the source driver ICs SDIC # 0 to SDIC # 3 in the first group, and SDIC # 4 to SDIC # 7 in the second group, respectively.

15, since the first group includes four source driver integrated circuits (SDIC # 0 to SDIC # 3), the lock signal LS # G1 transmitted from the first group to the timing controller 140 is And may include four status bits.

15, in the four status bits included in the lock signal LS # G1 transmitted from the first group to the timing controller 140, the first bit indicates a state bit indicating the data reception state of the SDIC # 0 (Bit value: 1) indicating the data reception state of the SDIC # 1, and the third bit is the status bit (bit value: 1) indicating the data reception state of the SDIC # Value: 0), and the fourth bit is a status bit (bit value: 1) indicating the data reception state of the SDIC # 3.

Similarly, in the four status bits included in the lock signal LS # G2 transmitted from the second group to the timing controller 140, the first bit is a status bit indicating the data reception state of the SDIC # 4 (bit value: 1), the second bit is a status bit (bit value: 0) indicating the data reception status of the SDIC # 5, the third bit is a status bit (bit value: 1) indicating the data reception status of the SDIC # , And the fourth bit is a status bit (bit value: 1) indicating the data reception state of the SDIC # 7.

As described above, under the cascade lock signal transmission system, the lock signal transmitted by the representative source driver integrated circuit expresses the data reception state of all the source driver integrated circuits with the state bits corresponding to the number of the source driver integrated circuits, So that it is possible to distinguish the data reception states of all the source driver integrated circuits with a small number of bits. Accordingly, the amount of data stored in the memory 540 can be reduced.

16 is a block diagram of a display device 100 according to the present embodiment in which, under a cascade lock signal transmission scheme, each of the source driver integrated circuits in each group carries a status bit-based cascade lock signal, An integrated circuit (SDIC # 3 in the case of the first group and SDIC # 7 in the second group) transmits a state bit-based lock signal to the timing controller 140 and the timing controller 140 Fig. 2 is an example of executing a panel bunting prevention process. Fig.

16, the data reception states of the SDIC # 2 and the SDIC # 5 are abnormal and the remaining SDIC # 0, SDIC # 1, SDIC # 3, SDIC # 4, SDIC # 7 are assumed to be normal.

Referring to FIG. 16, in the first group, the SDIC # 0 corresponding to the first source driver IC integrates the first bit corresponding to its position among the four bits included in the lock signal LS # The status bit 1 indicating the data reception state is recorded, and the cascade lock signal CLS # 0 is transmitted to the SDIC # 1 via the cascade signal line CSL # 01.

The next SDIC # 1 further records a state bit 1 indicating a normal data reception state in the second bit corresponding to its position among the four bits included in the lock signal LS # G1, and outputs the cascade lock signal CLS # 1 to the SDIC # 2 through the cascade signal line CSL # 12.

The next SDIC # 2 further records a state bit 0 indicating an abnormal data reception state in the third bit corresponding to its own position among the four bits included in the lock signal LS # G1 and outputs the cascade lock signal CLS # 2 to the SDIC # 3 through the cascade signal line CSL # 23.

Next, the SDIC # 3 corresponding to the representative source driver integrated circuit in the first group indicates a normal data reception state at the fourth bit corresponding to its position among the four bits included in the lock signal LS # G1 And further transmits the cascade lock signal CLS # 3 as the lock signal LS # G1 to the timing controller 140 via the representative lock signal RLSL # 3.

At this time, the lock signal LS # G1 finally transmitted to the timing controller 140 includes 1101 status bits.

16, in the second group, the SDIC # 4 corresponding to the first source driver integrated circuit receives the first bit corresponding to its position among the four bits included in the lock signal LS # And transmits the cascade lock signal CLS # 4 to the SDIC # 5 through the cascade signal line CSL # 45.

The next SDIC # 5 further records a state bit 0 indicating a normal data reception state in the second bit corresponding to its position among the four bits included in the lock signal LS # G2, and outputs the cascade lock signal CLS # 5 to the SDIC # 6 through the cascade signal line CSL # 56.

The next SDIC # 6 further records a state bit 1 indicating an abnormal data reception state in the third bit corresponding to its position among the four bits included in the lock signal LS # G2, and outputs the cascade lock signal CLS # 6 to the SDIC # 7 through the cascade signal line CSL # 67.

Next, the SDIC # 7 corresponding to the representative source driver integrated circuit in the second group indicates a normal data reception state at the fourth bit corresponding to its own position among the four bits included in the lock signal LS # G2 And further transmits the cascade lock signal CLS # 7 as the lock signal LS # G2 to the timing controller 140 via the representative lock signal RLSL # 3.

At this time, the lock signal LS # G2 finally transmitted to the timing controller 140 includes 1011 status bits.

16, the timing controller 140 controls all the source driver integrated circuits SDIC # 0, SDIC # 1, ..., SDIC # 1, SDIC # 2, ..., SDIC # 7) to identify the source driver integrated circuit or the flexible flat cable or bonding pad or data line or subpixel column corresponding to the defect occurrence position as a monitoring result in the memory 540 ).

The status bits included in the lock signals LS # G1 and LS # G2 transmitted from the representative driver ICs SDIC # 3 and SDIC # 7 of each group are stored in the cascade lock signal transmission system It is confirmed whether the data reception state of each of the source driver integrated circuits SDIC # 0, SDIC # 1, ..., SDIC # 7 is normal or abnormal and stored in the memory 540. Thus, (SDIC # 2, SDIC # 5) of the source driver integrated circuit (SDIC # 5) in the status of the panel boot prevention process.

On the other hand, the timing controller 140 receives from the representative source driver ICs (SDIC # 3 and SDIC # 7) in each group the lock signals LS # G1 and LS # G2 including the status bit 0 corresponding to the abnormal state ) Is continuously checked for a certain number of times or more, or for a predetermined time or more, rather than once, the panel bang prevention process can be executed.

Accordingly, the timing controller 140 determines whether there is an abnormal data reception state based on the lock signals LS # G1 and LS # G2 received from the representative source driver ICs (SDIC # 3 and SDIC # 7) If the presence of the source driver integrated circuit having an abnormal data reception state has been continuously checked for a predetermined number of times or more or for a predetermined time or more instead of immediately executing the panel booting prevention process by checking once whether the source driver integrated circuit is present It is possible to prevent the unnecessary panel booting prevention process from being executed and to prevent the permanent booting process from being performed when a source driver integrated circuit that is temporarily and one-time- If there is a source driver integrated circuit in an abnormal data reception state It is possible to control so that the UMAN only panel boot prevention process is executed.

On the other hand, when the timing controller 140 determines to execute the panel-bunnning prevention process, it outputs the power-off control signal of the display device 100 to the power management unit 550, thereby executing the panel-bunnning prevention process.

Thus, by turning off the power supply to the display device 100 by outputting the power-off control signal, at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # The gate node N2 of the first transistor T1 corresponding to the driving transistor in any sub-pixel is floated and an abnormal overcurrent flows to the organic light emitting diode OLED so that the sub-pixel emits abnormal light It is possible to prevent the display panel 110 from being burnt.

17 and 18 are illustrations of a method for finally determining whether or not a source driver integrated circuit is defective under the cascade lock signal transmission system in the display device 100 according to the present embodiments.

17, the timing controller 140 checks the lock signals LS # G1 and LS # G2 received from the representative source driver ICs SDIC # 3 and SDIC # 7 of each group, The number of times (for example, four times) that the star lock signals LS # G1 and LS # 2 include the state bit 0 corresponding to the abnormal state or the state voltage level (low level voltage) corresponding to the abnormal state, The abnormal data reception state of the corresponding source driver integrated circuit is permanently determined, and the source driver integrated circuit is finally determined as a fault.

If the timing controller 140 confirms the lock signals LS # G1 and LS # G2 received from the representative source driver ICs SDIC # 3 and SDIC # 7 of each group several times, It is determined that the signals LS # G1 and LS # 2 continue to have a state voltage level (low level voltage) corresponding to the abnormal state for less than a predetermined number of times (for example, four times) Or the lock signal LS # G1 or LS # 2 for each group has a state bit (0) corresponding to an abnormal state lasts less than a certain number of times (for example, 4 times) It is determined that the abnormal data reception state of the corresponding source driver integrated circuit is temporary, and the source driver integrated circuit is not finally determined as a fault.

17, for example, the second bit indicating the data reception state of the SDIC # 2 is the lock signal LS # G1 which is the state bit (0) indicating the abnormal data reception state or the state voltage level (low level voltage Since the lock signal LS # G1 with the lock signal LS # G1 having the first group has been transferred to the timing controller 140 more than four times, the timing controller 140 has a permanent failure such that the panel- It can be decided finally.

In contrast, when the second bit indicating the data reception state of the SDIC # 5 is the lock signal LS # G2 which is the status bit (0) indicating the abnormal data reception state or the lock having the state voltage level (low level voltage) corresponding to the abnormal state Since the signal LS # G2 has been transferred to the timing controller 140 only three times, the timing controller 140 determines that a permanent failure has occurred in the SDIC # 5 or the second group I never do that.

18, the timing controller 140 receives from the representative source driver ICs (SDIC # 3 and SDIC # 7) of each group a state bit 0 corresponding to an abnormal state or a state corresponding to an abnormal state It is confirmed through the timer 1800 how long the lock signal LS # G1, LS # G2 having the voltage level (low level voltage) is continuously received for a certain period of time, For example, 100 ms), it is determined that there is a source driver integrated circuit permanently in an abnormal data reception state.

If the timing controller 140 receives a state bit 0 corresponding to an abnormal state from the representative source driver ICs (SDIC # 3 and SDIC # 7) of each group or a state voltage level (LS # G1, LS # G2) having a predetermined voltage level (for example, level voltage) is continuously received for a certain period of time through a timer 1800. If the confirmed duration is less than a predetermined time, It is determined that there is no source driver integrated circuit in an abnormal data reception state.

18, the second bit indicating the data reception state of the SDIC # 2 is the lock signal LS # G1 which is the state bit (0) indicating the abnormal data reception state, or the state voltage level corresponding to the abnormal state (low level voltage Since the lock signal LS # G1 having the lock signal LS # G1 having a high level is continuously transmitted for a predetermined time or more determined by the timing controller 140, the timing controller 140 sets the lock signal LS # G1 to the SDIC # You can make a final decision that a permanent failure has occurred.

In contrast, when the second bit indicating the data reception state of the SDIC # 5 is the lock signal LS # G2 which is the status bit (0) indicating the abnormal data reception state or the lock having the state voltage level (low level voltage) corresponding to the abnormal state Since the signal LS # G2 has been transmitted to the timing controller 140 for less than a predetermined time, the timing controller 140 has been judged to be in the final state that the SDIC # 5 or the second group has suffered a permanent failure such that the panel- Do not decide.

17 and 18, it is finally determined that one SDIC # 5 out of all the eight source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) The panel booting prevention process for cutting off the power supply to the display device 100 may be executed and the operation of replacing the defective SDIC # 5 or the related structure may be performed.

As described above, under the P2P lock signal transmission system or the cascade lock signal transmission system, the signal transmission between the source driver integrated circuits and the timing controller is performed by, for example, an Embedded Clock Point to Point Interface (EPI) standard or a Low Voltage Differential Signal (LVDS) Based on the interface specification.

If signal transmission between the source driver integrated circuits and the timing controller is performed based on the LVDS (Low Voltage Differential Signal) interface standard, high-speed signal transmission can be performed while reducing power consumption. However, in the case of the LVDS interface, since the RGB video data and the clock are respectively transmitted in the form of a differential signal, when the odd data and the excellent data are simultaneously transmitted, the signal wiring between the timing controller 140 and the source driver integrated circuits There are many disadvantages. Compared to the LVDS interface, since the signal transmission between the source driver integrated circuits and the timing controller is based on the EPI interface specification, no separate clock signal wiring between the timing controller 140 and the source driver integrated circuits is required, There is an advantage that the number of signal lines between the timing controller 140 and the source driver integrated circuits can be minimized.

As described above, according to the present embodiments, a display apparatus 100 capable of monitoring a situation in which a panel bunting phenomenon may occur and a structure thereof, And the timing controller 140 are provided.

In addition, according to the present embodiments, the data voltage is not normally applied to the gate node of the driving transistor of the sub-pixel due to the data voltage undesired output of the source driver integrated circuit, cable connection failure, etc., and an overcurrent flows to the organic light- The present invention provides a display device 100 and a timing controller 140 that can prevent a panel bunting phenomenon in advance by monitoring a panel bunting phenomenon that may occur due to the occurrence of a panel bang phenomenon.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: Gate driver
140: Timing controller

Claims (18)

A display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged;
A timing controller for transmitting data; And
And source driver integrated circuits for converting the data into a data voltage and outputting the data voltage to a data line,
At least one of the source driver integrated circuits transmits a lock signal indicating a data reception state to the timing controller,
Wherein the timing controller executes a panel bunching prevention process based on a lock signal received from at least one of the source driver integrated circuits. The method according to claim 1,
Each of the source driver integrated circuits being connected to the timing controller via a separate lock signal wiring,
Wherein each of the source driver integrated circuits individually transmits a lock signal indicating a data reception state through the individual lock signal wiring to the timing controller. 3. The method of claim 2,
Wherein the lock signal transmitted through the individual lock signal wiring comprises:
And a state bit indicating a data reception state or a state voltage level corresponding to a data reception state. The method of claim 3,
When the lock signal transmitted through the individual lock signal wiring is at the state voltage level corresponding to the data reception state,
The timing controller includes:
The identification information of the individual lock signal wiring or the identification information of the source driver integrated circuit connected to the individual lock signal wiring is stored in the memory. The method of claim 3,
When the lock signal transmitted through the individual lock signal wiring includes a status bit indicating a data reception state,
Wherein the lock signal transmitted through the individual lock signal wiring comprises:
Further comprising identification information of a source driver integrated circuit connected to the individual lock signal wiring in addition to the status bits. 6. The method of claim 5,
The timing controller includes:
The status bit and the identification information from the lock signal received from each of the source driver integrated circuits through the individual lock signal wiring to determine whether the source driver integrated circuit or the flexible flat cable, And stores identification information on a line or a sub-pixel column in a memory. The method of claim 3,
The timing controller includes:
At least one lock signal having a state voltage level corresponding to an abnormal state or a state bit indicating an abnormal state among the lock signals received from the source driver integrated circuits is continuously supplied for a predetermined number of times or more And when it is confirmed, executes the panel bunching prevention process. The method according to claim 1,
A representative lock signal wiring is connected between the representative source driver integrated circuit and the timing controller of the source driver integrated circuits,
And only the representative source driver integrated circuit transmits the lock signal to the timing controller. 9. The method of claim 8,
In the source driver integrated circuits, a cascade signal wiring is connected between two adjacent source driver integrated circuits,
The source driver integrated circuits sequentially transmit the cascade lock signal through the corresponding cascade signal line from the first source driver integrated circuit to the representative source driver integrated circuit which is the last source driver integrated circuit,
Wherein the representative source driver integrated circuit receives a cascade lock signal through a cascade signal wiring connected to a previous source driver integrated circuit and then transmits a lock signal to the timing controller through the representative lock signal wiring. 10. The method of claim 9,
Wherein the lock signal transmitted through the representative lock signal wiring includes:
The source driver integrated circuits are both in a normal data reception state or at least one of the source driver integrated circuits is at a state voltage level indicating that the data reception state is abnormal,
And a status bit indicating a data reception status indicating whether each of the source driver integrated circuits has normally received the data. 11. The method of claim 10,
When the lock signal transmitted through the representative lock signal wiring includes a status bit indicating a data reception state for each of the source driver integrated circuits,
And a status bit indicating a data reception state for each of the source driver integrated circuits is included in a unique position of each of the source driver integrated circuits. 12. The method of claim 11,
The timing controller includes:
The status bit position and the status bit for each of the source driver integrated circuits through the representative lock signal line to identify a source driver integrated circuit or a flexible flat cable or bonding pad or data line or sub- And the identification information about the column is stored in the memory. 11. The method of claim 10,
The timing controller includes:
When the lock signal including the status bit corresponding to the abnormal status or the status bit indicating the abnormal status is continuously checked for a predetermined number of times or more for a predetermined time or longer from the representative source driver integrated circuit, And the display device. 9. The method of claim 8,
Wherein the source driver integrated circuits are classified into at least one group, and the representative source driver integrated circuits each for transmitting a lock signal to the timing controller exist for each group. The method according to claim 1,
The timing controller includes:
And outputs the power-off control signal of the display device to the power management unit, thereby executing the panel-bust prevention process. The method according to claim 1,
Wherein signal transmission between the source driver integrated circuits and the timing controller is performed based on an Embedded Clock Point to Point Interface (EPI) standard or a Low Voltage Differential Signal (LVDS) interface standard. A display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged;
A timing controller for transmitting data; And
And source driver integrated circuits for converting the data into a data voltage and outputting the data voltage to a data line,
Wherein at least one of the source driver integrated circuits comprises:
A lock signal indicating a data reception state is transmitted to the timing controller,
The timing controller includes:
Monitoring whether a source driver integrated circuit that fails to output a data voltage or outputs an abnormal data voltage among the source driver integrated circuits exists based on a lock signal received from at least one of the source driver integrated circuits, And outputs the output signal. A transmitter for transmitting data to the source driver integrated circuits;
A receiver for receiving a lock signal indicating a data reception state from at least one of the source driver integrated circuits; And
And a panel-bust prevention unit for executing a predetermined panel-bust prevention process based on the lock signal received from at least one of the source driver integrated circuits.

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