KR102448353B1 - Display device - Google Patents

Abstract

An object of the present application is to provide a display device that can check the clock detection readiness state of a source driver IC in a point-to-point manner, thereby contributing to cost reduction and productivity improvement. In the display device according to the present application, a gate line and a data line crossing the gate line are disposed, the display panel having the gate line and a plurality of pixels connected to the data line, a gate driver supplying a gate signal to the gate line, and a data line a data driver comprising a plurality of source driver ICs for supplying a data voltage to the circuit board, and a timing controller controlling operation timings of the gate driver and the data driver, wherein the timing controller comprises a set number of source driver ICs from among the plurality of source driver ICs. A single acknowledgment signal is supplied from the driver ICs.

Description

display device {DISPLAY DEVICE}

This application relates to a display device.

In the information society, many technologies have been developed in the field of display devices for displaying visual information as images or images. A display device includes a display panel, a gate driver, a data driver, a timing controller, and a host system. The display panel includes data lines, gate lines, and a plurality of pixels formed at intersections of data lines and gate lines to receive data voltages of the data lines when gate signals are supplied to the gate lines.

The data driver includes a plurality of source driver ICs. It is necessary to check the Clock Detection Ready status of the source driver IC. To this end, the LOCK signal of the EPI protocol is supplied to the timing controller in a cascade method to determine whether it is normal or not.

If bonding between the source driver IC and the source printed circuit board or display panel is not performed normally, the transmission of the lock signal may fail due to CDR failure. In this case, the screen of the display panel is in an image insensitive state and the lock signal maintains a low logic level. However, in the conventional structure, since the timing controller receives the lock signal of the last source driver IC, there is a problem in that it is not known which source driver IC has failed.

In this case, if a lock signal-related failure occurs in the manufacturing process of the display device, it is not possible to know which source driver IC has the defect, and since it is necessary to measure the bonding resistance of all source driver ICs for analysis, productivity decreases. do.

In addition, in the case of lock signal-related failures caused by internal problems such as source driver IC damage, it is impossible to determine the cause, and since the defective source driver IC cannot be limited to a specific source driver IC, lock signal-related failures In this case, since the entire source printed circuit board must be replaced, a large amount of cost is consumed to proceed with the repair.

An object of the present application is to provide a display device that can check the clock detection readiness state of a source driver IC in a point-to-point manner, thereby contributing to cost reduction and productivity improvement.

In the display device according to the present application, a gate line and a data line crossing the gate line are disposed, the display panel having the gate line and a plurality of pixels connected to the data line, a gate driver supplying a gate signal to the gate line, and a data line a data driver comprising a plurality of source driver ICs for supplying a data voltage to the circuit board, and a timing controller controlling operation timings of the gate driver and the data driver, wherein the timing controller comprises a set number of source driver ICs from among the plurality of source driver ICs. A single acknowledgment signal is supplied from the driver ICs.

The display device according to the present application connects the clock detection readiness state of the source driver IC in a point-to-point manner, thereby reducing the cost of replacing the source driver IC by accurately detecting which source driver IC has a defect. can do it

The display device according to the present application may reduce repair costs due to defective or poor coupling of the source driver IC.

The display device according to the present application may prevent damage to a display panel or circuit components inside the display device due to a defective source driver IC or a defective coupling.

1 is a perspective view of a display device according to the present application.
2 is a block diagram of a display device according to the present application.
3 is a circuit diagram illustrating the pixel of FIG. 2 .
4 is a block diagram illustrating a signal transmission/reception relationship between a conventional timing controller and a plurality of source driver ICs.
FIG. 5 is a block diagram illustrating a signal transmission/reception relationship when an arbitrary source driver IC in FIG. 4 fails.
6 is a block diagram illustrating a signal transmission/reception relationship between a timing controller and a plurality of source driver ICs according to an example of the present application.
7 is a waveform diagram illustrating a clock preparation signal and a confirmation signal in a clock training period according to an example of the present application.
8 is a waveform diagram illustrating a clock preparation signal and a confirmation signal in a data transmission section, a clock training section, and an arrangement section according to an example of the present application.
9 is a waveform diagram illustrating a clock preparation signal and a confirmation signal in a data transmission section, a clock training section, and an arrangement section according to a failure of a source driver IC in the clock training section according to an example of the present application.
10 is a waveform diagram illustrating a clock preparation signal and a confirmation signal in a data transmission section and a clock training section according to a failure of a timing controller in a clock training section according to an example of the present application.

Advantages and features of the present application and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which this application belongs It is provided to fully inform the possessor of the scope of the invention, and the present application is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present application are exemplary and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present application.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than the range in which the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present application may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.

1 is a perspective view of a display device according to the present application. 2 is a block diagram of a display device according to the present application. 3 is a circuit diagram illustrating the pixel of FIG. 2 . The display device according to the present application includes a display panel 110 , a gate driver 120 , a data driver 130 , a flexible film 140 , a printed circuit board (PCB) 150 , a connection unit 160 , a set 170 , a timing controller (T-con) 200 , and a host system 300 . Hereinafter, it is assumed that the display device according to the present application is an organic light emitting display device.

The display panel 110 includes a lower substrate 111 and an upper substrate 112 . The lower substrate 111 may be a thin film transistor substrate made of plastic or glass. The upper substrate 112 may be an encapsulation substrate made of a plastic film, a glass substrate, or a protective film.

The lower substrate 111 includes a display area and a non-display area provided around the display area. The display area is an area in which pixels P are provided to display an image. Gate lines GL1 to GLp, where p is a positive integer greater than or equal to 2), data lines DL1 to DLq, q is a positive integer greater than or equal to 2), and sensing lines SL1 to SLq are disposed on the lower substrate 111 . do. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be disposed parallel to each other. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be disposed to cross the gate lines GL1 to GLp.

Each of the pixels P includes an organic light emitting diode (OLED) and a pixel driver PD. In FIG. 2 , for convenience of explanation, the jth (j is a positive integer satisfying 1≤≤j≤≤q) data line DLj, the jth sensing line SLj, and the kth (k is 1≤≤k) Only the pixel P connected to the scan line Sk and the k-th sensing signal line SSk (a positive integer satisfying ≤ ≤ p) is illustrated. The k-th scan line Sk and the k-th sensing signal line SSk are included in the k-th gate line GLk.

The organic light emitting diode OLED emits light according to a current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the source electrode of the driving transistor DT, and the cathode electrode is connected to the low potential voltage line ELVSSL to which the low potential voltage ELVSS lower than the high potential voltage ELVDD is supplied. can be connected.

An organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In an organic light emitting diode (OLED), when a voltage is applied to an anode electrode and a cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and the holes and electrons are combined with each other in the organic light emitting layer to emit light.

The pixel driver PD supplies current to the organic light emitting diode OLED and the j-th sensing line SLj. The pixel driver PD includes a driving transistor DT, a first transistor ST1 controlled by a scan signal of a scan line Sk, and a second transistor ST1 controlled by a sensing signal of a sensing signal line SSk. A transistor ST2 and a capacitor C may be included.

The pixel driver PD receives the data voltage VDATA of the data line DLj connected to the pixel P when a scan signal is supplied from the scan line Sk connected to the pixel P in the display mode, A current of the driving transistor DT according to the data voltage VDATA is supplied to the organic light emitting diode OLED. When a sensing signal is supplied from the sensing signal line SSk connected to the pixel P in the sensing mode, the pixel driver PD transfers the current of the driving transistor DT to the sensing line SLj connected to the pixel P. shedding

The driving transistor DT is provided between the high potential voltage line ELVDDL and the organic light emitting diode OLED. The driving transistor DT adjusts a current flowing from the high potential voltage line ELVDDL to the organic light emitting diode OLED according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1 , the source electrode is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode is supplied with the high potential voltage ELVDD. may be connected to the high potential voltage line ELVDDL.

The first transistor ST1 is turned on by the k-th scan signal of the k-th scan line Sk to supply the voltage of the j-th data line DLj to the gate electrode of the driving transistor DT. The gate electrode of the first transistor T1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the driving transistor DT, and the second electrode is connected to the j-th data line DLj. can be The first transistor ST1 may be collectively referred to as a scan transistor.

The second transistor ST2 is turned on by the k-th sensing signal of the k-th sensing signal line SSk to connect the j-th sensing line SLj to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the k-th sensing signal line SSk, the first electrode is connected to the j-th sensing line SLj, and the second electrode is connected to the source electrode of the driving transistor DT. can be connected. The second transistor ST2 may be collectively referred to as a sensing transistor.

The capacitor C is provided between the gate electrode and the source electrode of the driving transistor DT. The capacitor C stores a difference voltage between the gate voltage and the source voltage of the driving transistor DT.

In FIG. 2 , the driving transistor DT and the first and second transistors ST1 and ST2 are mainly described as being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it should be noted that the present invention is not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In addition, it should be noted that the first electrode may be a source electrode and the second electrode may be a drain electrode, but the present invention is not limited thereto. That is, the first electrode may be a drain electrode and the second electrode may be a source electrode.

In the display mode, when a scan signal is supplied to the k-th scan line Sk, the data voltage VDATA of the j-th data line DLj is supplied to the gate electrode of the driving transistor DT, and the k-th sensing signal line ( When the sensing signal is supplied to SSk), the initialization voltage of the j-th sensing line SEj is supplied to the source electrode of the driving transistor DT. Accordingly, in the display mode, the current of the driving transistor DT flowing according to the voltage difference between the voltage of the gate electrode and the voltage of the source electrode of the driving transistor DT is supplied to the organic light emitting diode OLED, and the organic light emitting diode OLED ) emits light according to the current of the driving transistor DT. In this case, since the data voltage VDATA is a voltage that compensates for the threshold voltage and electron mobility of the driving transistor DT, the current of the driving transistor DT does not depend on the threshold voltage and electron mobility of the driving transistor DT. .

In the sensing mode, when a scan signal is supplied to the k-th scan line Sk, the sensing voltage of the j-th data line is supplied to the gate electrode of the driving transistor DT, and the sensing signal is applied to the k-th sensing signal line SSk. When supplied, the initialization voltage of the j-th sensing line SLj is supplied to the source electrode of the driving transistor DT. In addition, when a sensing signal is supplied to the k-th sensing signal line SSk, the second transistor ST2 is turned on and the driving transistor DT flows according to a voltage difference between the voltage of the gate electrode and the voltage of the source electrode of the driving transistor DT. The current of the transistor DT flows to the j-th sensing line SLj.

The gate driver 120 receives the gate driver control signal GCS from the timing controller 200 . The gate driver 120 supplies gate signals to the gate lines GL1 to GLp according to the gate driver control signal GCS. The gate signals include a scan signal and a sensing signal. The gate driver 120 may be formed in a non-display area on one side or both sides of the display area of the display panel 110 by a gate driver in panel (GIP) method.

The data driver 130 receives the compensation digital video data CDATA and the data driver control signal DCS from the timing controller 200 . The compensated digital video data CDATA is a digital video corrected by performing external compensation for compensating the threshold voltage of the driving transistor DT and afterimage compensation for compensating for the degree of deterioration of the organic light emitting diode (OLED) on the digital video data DATA. is data. The data driver 130 converts the compensation digital video data CDATA into an analog data voltage according to the data driver control signal DCS and supplies it to the data lines DL1 to DLq. Pixels P to which data voltages are to be supplied are selected by scan signals supplied from the gate driver 120 . The selected pixels P receive data voltages and emit light with a predetermined brightness.

The data driver 130 receives a sensing voltage or a sensing current from the sensing lines SL1 to SLq. The data driver 130 uses the sensing voltage or the sensing current to detect the threshold voltage of the driving transistor DT of each pixel P and the sensing data SEN including information on the degree of deterioration of the organic light emitting diode (OLED). create The data driver 130 supplies the sensing data SEN to the timing controller 200 .

The data driver 130 includes a plurality of source driver integrated circuits (SDICs) 131 . Each of the source driver ICs 131 is mounted on each of the flexible films 140 . Each of the flexible films 140 may be attached to the pads provided on the lower substrate 111 by a tape automated bonding (TAB) method using an anisotropic conductive film (ACF). The pads are connected to the data lines DL1 to DLq, so that the source driver ICs 131 may be connected to the data lines DL1 to DLq.

Each of the flexible films 140 may be provided by a chip on film (COF) method or a chip on plastic (COP) method. The chip-on-film may include a base film such as polyimide and a plurality of conductive lead wires provided on the base film. Each of the flexible films 140 may be bent or bent. Each of the flexible films 140 may be attached to the lower substrate 111 and the printed circuit board 150 of the display panel 110 .

The printed circuit board 150 may be attached to the flexible films 140 . The printed circuit board 150 may mount the timing controller 200 . The printed circuit board 150 may be a flexible printed circuit board (FPCB). The printed circuit board 150 is connected to the set 170 through the connection unit 160 .

The connection unit 160 connects the printed circuit board 150 and the set 170 . The connection unit 160 may be a plurality of wires including a bus, which is an input/output terminal to which a Vx1 interface is applied between the timing controller 200 and the host system 300 . The Vx1 interface is an interface that can process multiple input data at high speed. However, the present invention is not limited thereto, and the connection unit 160 may be implemented with a plurality of wires including an arbitrary interface capable of transmitting data and an arbitrary input/output terminal.

The set 170 supplies power supply voltages and driving signals to the display device. The set 170 may be implemented as a set-top box, a phone system, a personal computer (PC), a broadcast receiver, a navigation system, a DVD player, a Blu-ray player, a home theater system, and the like. Set 170 may mount host system 300 . The set 170 is connected to the printed circuit board 150 by a connection unit 160 .

The timing controller 200 receives digital video data DATA and timing signals TS from the host system 300 . The host system 300 includes a system on chip (SoC) in which a scaler is embedded. The host system 300 converts the digital video data DATA input from the outside into a format suitable for display on the display panel 110 .

The timing signals TS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a dot clock, and the like. The vertical sync signal is a signal defining one frame period. The horizontal synchronization signal is a signal defining one horizontal period required to supply data voltages to the pixels P of one horizontal line of the display panel 110 . The data enable signal is a signal defining a period in which valid data is input. The dot clock is a signal that is repeated with a predetermined short period.

The timing controller 200 controls the operation timing of the gate driver 120 and the data driver 130 , and a gate driver control signal for controlling the operation timing of the gate driver 120 based on the timing signals TS. A data driver control signal DCS for controlling the operation timing of the GCS and the data driver 130 is generated. The timing controller 200 outputs the gate driver control signal GCS to the gate driver 120 and outputs the data driver control signal DCS to the data driver 130 .

The timing controller 200 receives sensing data SEN from the data driver 130 . The timing controller 200 generates compensation data capable of performing external compensation and afterimage compensation by using the sensing data SEN. The timing controller performs external compensation and residual image compensation using compensation data. The timing controller 200 supplies the compensated digital video data CDATA for which external compensation and afterimage compensation have been completed, to the data driver 130 .

To summarize the contents described in connection with FIGS. 1 to 3 , in the present application, the gate lines GL1 to GLp and the data lines DL1 to DLq intersecting the gate lines GL1 to GLp are disposed, and the gate line GL1 GLp) and the display panel 110 having a plurality of pixels P connected to the data lines DL1 to DLq, the gate driver 120 supplying gate signals to the gate lines GL1 to GLp, and the data line DL1 to DLq) a data driver 130 for supplying a data voltage, and a timing controller 200 for controlling operation timings of the gate driver 120 and the data driver 130 .

4 is a block diagram illustrating a signal transmission/reception relationship between the conventional timing controller 200 and a plurality of source driver ICs 131 .

The plurality of source driver ICs 131 are connected to the first and second printed circuit boards 151 and 152 by the flexible film 140 .

Among the plurality of source driver ICs 131 , the source driver IC 131 connected to the first printed circuit board 151 is defined as the first group of source driver ICs 131 . Among the plurality of source driver ICs 131 , the source driver IC 131 connected to the second printed circuit board 152 is defined as the second group of source driver ICs 131 .

The source driver ICs 131 of the first group receive the 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N, respectively. Each of the 1-1 to 1-Nth clock ready signals EPI1_1 to EPI1_N is Clock Detection Ready for detecting whether an internal clock generated by each of the source driver ICs 131 included in the first group is abnormal. , CDR), a clock training period (C/T) is set.

The first source driver IC 131 of the first group, which is the source driver IC 131 disposed on one side of the first printed circuit board 151 among the source driver ICs 131 of the first group, has a first power voltage ( VCC1) is supplied. The first source driver IC 131 of the first group generates the first lock signal LOCK1_1 of the first group by using the first power voltage VCC1. The first lock signal LOCK1_1 of the first group confirms whether the first source driver IC 131 of the first group can perform clock detection preparation, and the first source driver IC 131 of the first group is normally Check whether it is running. The first source driver IC 131 of the first group supplies the first lock signal LOCK1_1 of the first group to the second source driver IC 131 of the first group.

The second source driver IC 131 of the first group receives the first lock signal LOCK1_1 of the first group. The second source driver IC 131 of the first group generates the second lock signal LOCK1_2 of the first group when the first lock signal LOCK1_1 of the first group is not abnormal, and the third source driver of the first group It is supplied to the IC (131).

In the same manner, the N-th source driver IC 131 of the first group, which is the source driver IC 131 disposed on the other side of the first printed circuit board 151 among the source driver ICs 131 of the first group, is The first group of the N-1 th lock signal LOCK1_N-1 is supplied. The N-th source driver IC 131 of the first group generates the N-th lock signal LOCK1_N of the first group when there is no abnormality in the N-1 th lock signal LOCK1_N-1 of the first group. The N-th source driver IC 131 of the first group supplies the N-th lock signal LOCK1_N of the first group to the timing controller 200 .

The second group of source driver ICs 131 receive the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N, respectively. Each of the 2-1 to 2-Nth clock ready signals EPI2_1 to EPI2_N is Clock Detection Ready for detecting whether an internal clock generated by each of the source driver ICs 131 included in the second group is abnormal. , CDR), a clock training period (C/T) is set.

The first source driver IC 131 of the second group, which is the source driver IC 131 disposed on one side of the second printed circuit board 152 among the source driver ICs 131 of the second group, has a second power supply voltage ( VCC2) is supplied. The first source driver IC 131 of the second group generates the first lock signal LOCK2_1 of the second group by using the second power voltage VCC2. The first lock signal LOCK2_1 of the second group checks whether the first source driver IC 131 of the second group can perform clock detection preparation, and the first source driver IC 131 of the second group is normally Check whether it is running. The first source driver IC 131 of the second group supplies the first lock signal LOCK2_1 of the second group to the second source driver IC 131 of the second group.

The second source driver IC 131 of the second group receives the first lock signal LOCK2_1 of the second group. The second source driver IC 131 of the second group generates the second lock signal LOCK2_2 of the second group when the first lock signal LOCK2_1 of the second group is not abnormal, and the third source driver of the second group It is supplied to the IC (131).

In the same manner, the N-th source driver IC 131 disposed on the other side of the second printed circuit board 152 among the source driver ICs 131 of the second group receives the N-1th lock signal LOCK2_N of the second group. -1) is supplied. The N-th source driver IC 131 of the second group generates the N-th lock signal LOCK2_N of the second group when there is no abnormality in the N-1 th lock signal LOCK2_N-1 of the second group. The Nth source driver IC 131 of the second group supplies the Nth lock signal LOCK2_N of the second group to the timing controller 200 .

The timing controller 200 supplies the 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N to the plurality of source driver ICs 131 of the first group, respectively. The timing controller 200 supplies the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N to the plurality of source driver ICs 131 of the second group, respectively. The timing controller 200 receives the N-th lock signal LOCK1_N of the first group from the N-th source driver IC 131 of the first group. When the N-th lock signal LOCK1_N of the first group is normally supplied, the timing controller 200 determines that all of the source driver ICs 131 of the first group are normally prepared for clock detection and all are normally driven. When the second group's Nth lock signal LOCK2_N is normally supplied, the timing controller 200 determines that all of the source driver ICs 131 of the second group are normally prepared for clock detection and all are normally driven.

FIG. 5 is a block diagram illustrating a signal transmission/reception relationship when an arbitrary source driver IC 131 in FIG. 4 fails. 5 exemplifies a case in which the second source driver ICs 131 of the first and second groups fail. The cause of the failure of the source driver IC 131 is damage to the source driver IC 131 due to static electricity (ESD), a sudden surge in the voltage supplied to the source driver IC 131, and other external shocks. .

The failed source driver IC 131 receives the first lock signal LOCK1_1 of the first group and the first lock signal LOCK2_1 of the second group, which are normal lock signals. However, the failed source driver IC 131 does not generate a lock signal. Accordingly, the second source driver ICs 131 of the first and second groups do not generate the second lock signal LOCK1_2 of the first group and the second lock signal LOCK2_2 of the second group. Accordingly, the third source driver ICs 131 of the first and second groups do not receive the lock signal. In this case, all of the third to Nth source driver ICs 131 do not generate a normal lock signal. The N-th source driver ICs 131 of the first and second groups also fail to generate the N-th lock signals LOCK1_N and LOCK2_N or generate abnormal N-th lock signals LOCK1_N and LOCK2_N.

The timing controller 200 does not receive the normal first and second group N-th lock signals LOCK1_N and LOCK2_N. Accordingly, the timing controller 200 may detect that a failure has occurred in any of the source driver ICs 131 in the first and second groups. However, the timing controller 200 cannot determine which source driver IC 131 in the first and second groups has a failure.

6 is a block diagram illustrating a signal transmission/reception relationship between the timing controller 200 and a plurality of source driver ICs 131 according to an example of the present application.

The plurality of source driver ICs 131 are connected to the first and second printed circuit boards 151 and 152 by the flexible film 140 .

Among the plurality of source driver ICs 131 , the source driver IC 131 connected to the first printed circuit board 151 is defined as the first group of source driver ICs 131 . Among the plurality of source driver ICs 131 , the source driver IC 131 connected to the second printed circuit board 152 is defined as the second group of source driver ICs 131 .

The source driver ICs 131 of the first group receive the 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N, respectively. Each of the 1-1 to 1-Nth clock ready signals EPI1_1 to EPI1_N is Clock Detection Ready for detecting whether an internal clock generated by each of the source driver ICs 131 included in the first group is abnormal. , CDR), a clock training period (C/T) is set. Each of the source driver ICs 131 of the first group generates a first confirmation signal ELVDS1. Each of the source driver ICs 131 of the first group supplies the first confirmation signal ELVDS1 to the timing controller 200 .

The second group of source driver ICs 131 receive the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N, respectively. Each of the 2-1 to 2-Nth clock ready signals EPI2_1 to EPI2_N is Clock Detection Ready for detecting whether an internal clock generated by each of the source driver ICs 131 included in the second group is abnormal. , CDR), a clock training period (C/T) is set. Each of the second group of source driver ICs 131 generates a second confirmation signal ELVDS2. Each of the second group of source driver ICs 131 supplies the second confirmation signal ELVDS2 to the timing controller 200 .

The timing controller 200 supplies the 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N to the source driver ICs 131 of the first group, respectively. The timing controller 200 supplies the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N to the source driver ICs 131 of the second group, respectively.

The timing controller 200 receives a single confirmation signal from the source driver ICs 131 of a group consisting of a set number among the plurality of source driver ICs 131 . "A single acknowledgment signal is supplied." may mean that an acknowledgment signal is supplied from each source driver IC through each signal line. Accordingly, the source driver ICs 131 of the first group supply a confirmation signal to the timing controller 200 through one wire. In addition, the second group of source driver ICs 131 supplies a confirmation signal to the timing controller 200 through one wire.

More specifically, the timing controller 200 receives the first confirmation signal ELVDS1 from the first group of source driver ICs 131 connected to the first printed circuit board 151 . The timing controller 200 receives the second confirmation signal ELVDS2 from the second group of source driver ICs 131 connected to the second printed circuit board 152 .

The confirmation signal supplied from each of the source driver ICs 131 is supplied to the timing controller 200 from the plurality of source driver ICs 131 in the BLVDS method.

The first and second confirmation signals ELVDS1 and ELVDS2 may be supplied by a Bus Low Voltage Differential Signaling (BLVDS) method or a low potential differential signal transmission method using a bus terminal. The BLVDS method is particularly useful when sequentially supplying signals supplied from multiple IC chips to one terminal.

The first confirmation signal ELVDS1 includes information on whether each of the source driver ICs 131 of the first group is normally driven. The second confirmation signal ELVDS2 includes information on whether each of the source driver ICs 131 of the second group is normally driven. The first and second confirmation signals ELVDS1 and ELVDS2 sequentially supply information on whether each of the source driver ICs 131 is normally driven to the timing controller 200 .

The 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N and the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N are transmitted to each of the plurality of source driver ICs 131 in the EPI protocol method. is transmitted The EPI protocol method can efficiently transmit information necessary for setting a clock training period (C/T) to each source driver IC 131 .

Also, the 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N and the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N have different operation timings. When the operation timings of the 1-1 to 1-Nth clock preparation signals EPI1_1 to EPI1_N are all different, the first confirmation signal ELVDS1 generated by each of the source driver ICs 131 of the first group has different timings. has In addition, when the operation timings of the 2-1 to 2-Nth clock preparation signals EPI2_1 to EPI2_N are all different, the second confirmation signal ELVDS2 generated by each of the source driver ICs 131 of the second group is It has different operation timings.

The first confirmation signal ELVDS1 detects whether each of the source driver ICs 131 of the first group operates normally and whether the clock training period is normally performed. In order to detect whether each source driver IC 131 is operating normally, the first check signal ELVDS1 output from each source driver IC 131 should have different operation timings. The first confirmation signal ELVDS1 is a signal obtained by summing signals output from each of the source driver ICs 131 of the first group. The waveforms constituting the first confirmation signal ELVDS1 are waveforms output from each of the source driver ICs 131 of the first group, and are combined without overlapping each other to constitute one first confirmation signal ELVDS1 . Each of the source driver ICs 131 of the first group outputs sequentially set signals. Accordingly, by determining whether a signal set at a specific operation timing is normally output, it is possible to determine whether each of the source driver ICs 131 of the first group operates normally and whether the clock training period is normally performed.

Similarly, the second confirmation signal ELVDS2 detects whether each of the source driver ICs 131 of the second group operates normally and whether the clock training period is normally performed. In order to detect whether each source driver IC 131 is operating normally, the second confirmation signal ELVDS2 output from each source driver IC 131 should have different operation timings. The second confirmation signal ELVDS2 is a signal obtained by summing signals output from each of the source driver ICs 131 of the second group. Waveforms constituting the second confirmation signal ELVDS2 are waveforms output from each of the source driver ICs 131 of the second group, and are combined without overlapping each other to constitute one second confirmation signal ELVDS2. Each of the source driver ICs 131 of the second group outputs sequentially set signals. Accordingly, by determining whether a signal set at a specific operation timing is normally output, it is possible to determine whether each of the source driver ICs 131 of the second group operates normally and whether the clock training period is normally performed.

7 is a waveform diagram illustrating clock preparation signals EPI1-1 to EPI2-N and confirmation signals ELVDS in a clock training period C/T according to an example of the present application.

The clock preparation signals EPI1-1 to EPI2-N are continuously alternated within the clock training period C/T while having a first logic level L1 and a second logic level lower than the first logic level L1. It has a logic level (L2). While having the first logic level L1 , each of the clock preparation signals EPI1-1 to EPI2-N is sequentially supplied to each of the plurality of source driver ICs 131 .

The confirmation signal ELVDS maintains the second logic level L2, and after the power-on sequence period, which is a period in which the operation is started by receiving a power supply voltage, the first logic level L1 and the first 2 The logic level L2 is alternately driven a plurality of times. In this case, the timing of the falling edge of the clock preparation signals EPI1-1 to EPI2-N is the same as the timing of the falling edge of the confirmation signal ELVDS. After alternating the first logic level L1 and the second logic level L2 a plurality of times, the confirmation signal ELVDS is between the first logic level L1 and the second logic level L2 and has a high impedance (High). The third logic level L3 defining the impedance, Hi-Z) section is maintained.

8 is a data transmission period (D/T), a clock training period (C/T), and clock preparation signals (EPI1-1 to C/F) of a configuration period (C/F) according to an example of the present application. It is a waveform diagram showing the EPI2-N) and the confirmation signal (ELVDS).

In the data transmission period D/T, the clock preparation signals EPI1-1 to EPI2-N alternately have the first and second logic levels L1 and L2 at a predetermined period. In the data transmission period D/T, the clock preparation signals EPI1-1 to EPI2-N transmit digital video data required for image display.

In the clock training period C/T, the clock preparation signals EPI1-1 to EPI2-N alternately have the first and second logic levels L1 and L2 with a longer period than in the data transmission period D/T. . In the clock training period C/T, the clock preparation signals EPI1-1 to EPI2-N perform clock detection preparation to detect the presence or absence of an internal clock generated by each of the source driver ICs 131 .

In the arrangement period C/F, the clock preparation signals EPI1-1 to EPI2-N alternately have the first and second logic levels L1 and L2 at the same period as the data transmission period D/T. In the data transmission period D/T, the clock preparation signals EPI1-1 to EPI2-N arrange digital video data necessary for image display.

In addition, in the data transmission period D/T, the clock training period C/T, and the arrangement period C/F, the confirmation signal ELVDS has a first logic level L1 and a second logic level L2. and maintains the third logic level L3 defining a high impedance (Hi-Z) section.

9 is a data transmission period (D/T), clock training period (C/T), and arrangement period (C/F) according to a failure of the source driver IC 131 of the clock training period according to an example of the present application. It is a waveform diagram showing the clock ready signal (EPI1-1 to EPI2-N) and the confirmation signal (ELVDS) of

In the data transmission period D/T, the clock preparation signals EPI1-1 to EPI2-N alternately have the first and second logic levels L1 and L2 at a predetermined period. In the data transmission period D/T, the clock preparation signals EPI1-1 to EPI2-N transmit digital video data required for image display.

In the clock training period C/T, the clock preparation signals EPI1-1 to EPI2-N alternately have the first and second logic levels L1 and L2 with a longer period than in the data transmission period D/T. . In the clock training period C/T, the clock preparation signals EPI1-1 to EPI2-N perform clock detection preparation to detect the presence or absence of an internal clock generated by each of the source driver ICs 131 .

In the arrangement period C/F, the clock preparation signals EPI1-1 to EPI2-N alternately have the first and second logic levels L1 and L2 at the same period as the data transmission period D/T. In the data transmission period D/T, the clock preparation signals EPI1-1 to EPI2-N arrange digital video data necessary for image display.

In addition, in the data transmission period D/T, the clock training period C/T, and the arrangement period C/F, the confirmation signal ELVDS has a first logic level L1 and a second logic level L2. While maintaining the third logic level L3 that defines the high impedance (Hi-Z) section, the second logic level L2 is maintained from the section where the failure occurs due to the generation of static electricity (ESD). . When the confirmation signal ELVDS maintains the second logic level L2 , the timing controller 200 may detect that a failure has occurred in the source driver IC 131 that outputs the confirmation signal ELVDS in the corresponding section. .

As described above, in the present application, when a failure occurs in any source driver IC 131 among the plurality of source driver ICs 131 , the group including the source driver IC 131 is a confirmation signal including failure information. (ELVDS) is generated and supplied to the timing controller 200 .

When a failure occurs in any of the source driver ICs 131 , the confirmation signal ELVDS generates failure information including the first pattern PTN1 and the second pattern PTN2 .

The first pattern PTN1 determines whether the clock signal is ready to be generated. The first pattern PTN1 may check whether each of the source driver ICs 131 can perform clock detection preparation. The first pattern PTN1 is collectively referred to as a CDR check pattern.

The second pattern PTN2 determines whether the source driver IC 131 itself is normally driven. The second pattern PTN2 determines whether digital video data normally set by the source driver IC 131 is output. The second pattern PTN2 is collectively referred to as an IC indication pattern.

When receiving the confirmation signal ELVDS including the first and second patterns PTN1 and PTN2 , the timing controller 200 may identify which source driver IC 131 has a failure.

In addition, when receiving the confirmation signal ELVDS including the first and second patterns PTN1 and PTN2 , the timing controller 200 may identify a cause of a failure occurring in an arbitrary source driver IC 131 . . This can be found by analyzing the length of the first or second patterns PTN1 and PTN2 , the number of repetitions, and the frequency of occurrence of the first or second patterns PTN1 and PTN2 .

10 is a diagram illustrating clock preparation signals EPI1-1 to EPI2 in a data transmission period (D/T) and a clock training period (C/T) according to a failure of the timing controller 200 in the clock training period according to an example of the present application. -N) and a waveform diagram showing the confirmation signal (ELVDS).

A clock preparation signal EPI1 for setting a clock training period C/T, which is a period in which the timing controller 200 can perform a clock detection preparation for detecting whether an internal clock generated by each of the source driver ICs 131 is abnormal -1 to EPI2-N) is not normally supplied, the clock training period (C/T) may continue without being terminated at a normal time point. This is a phenomenon that occurs when the timing controller 200 that outputs the clock preparation signals (EPI1-1 to EPI2-N) fails due to static electricity (ESD), a sudden increase in input voltage (Surge), or an external shock. to be.

In this case, the plurality of source driver ICs 131 continuously supply the first pattern PTN1 and the second pattern PTN2 to the timing controller 200 .

The first pattern PTN1 determines whether the clock signal is ready to be generated. The first pattern PTN1 may check whether each of the source driver ICs 131 can perform clock detection preparation. The first pattern PTN1 is collectively referred to as a CDR check pattern.

The second pattern PTN2 determines whether the source driver IC 131 itself is normally driven. The second pattern PTN2 determines whether digital video data normally set by the source driver IC 131 is output. The second pattern PTN2 is collectively referred to as an IC indication pattern.

The display device according to the present application connects the clock detection readiness state of the source driver IC in a point-to-point manner, thereby reducing the cost of replacing the source driver IC by accurately detecting which source driver IC has a defect. can do it

The display device according to the present application may reduce repair costs due to defective or poor coupling of the source driver IC.

The display device according to the present application may prevent damage to a display panel or circuit components inside the display device due to a defective source driver IC or a defective coupling.

Those skilled in the art through the above-described content will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

110: display panel 111: lower substrate
112: upper substrate 120: gate driver
130: data driver 131: source driver IC
140: flexible film 150: printed circuit board
151: a first printed circuit board 152; 2nd printed circuit board
160: connection unit 170: set
200: timing controller 300: host system

Claims (10)

a display panel having a gate line and a data line crossing the gate line, the display panel having a plurality of pixels connected to the gate line and the data line;
a gate driver supplying a gate signal to the gate line;
a data driver comprising a plurality of source driver ICs supplying data voltages to the data lines; and
a timing controller for controlling operation timings of the gate driver and the data driver;
The timing controller receives a single confirmation signal from the source driver ICs of a group consisting of a set number among the plurality of source driver ICs,
The confirmation signal is a signal for sequentially supplying signals supplied from each of the source driver ICs of the group through one wire. The method of claim 1,
The confirmation signal is supplied from the plurality of source driver ICs to the timing controller in a BLVDS method. The method of claim 1,
The timing controller supplies a clock preparation signal for setting a clock training period, which is a period in which a clock detection preparation for detecting an abnormality of an internal clock generated by each of the source driver ICs can be performed. 4. The method of claim 3,
The clock preparation signal is transmitted to each of the plurality of source driver ICs in an EPI manner,
The clock preparation signals transmitted to different source driver ICs have different operating timings. The method of claim 1,
a first printed circuit board connected to a first group of source driver ICs among the plurality of source driver ICs; and
a second printed circuit board connected to a second group of source driver ICs among the plurality of source driver ICs;
the source driver ICs of the first group supply a first acknowledgment signal to the timing controller;
The second group of source driver ICs supplies a second confirmation signal to the timing controller. The method of claim 1,
When a failure occurs in any source driver IC among the plurality of source driver ICs, the group including the arbitrary source driver IC generates a confirmation signal including failure information and supplies it to the timing controller. 7. The method of claim 6,
The failure information may include: a first pattern for determining whether a clock signal is ready to be generated; and
and a second pattern for determining whether the source driver IC itself is normally driven. 8. The method of claim 7,
wherein the timing controller is supplied with the first and second patterns and identifies a cause of a failure occurring in the arbitrary source driver IC. The method of claim 1,
When the plurality of source driver ICs are normal, the confirmation signal maintains a third level of a high impedance state at a level between a first level that is a high logic level and a second level that is a low logic level,
The display device maintains the second level when a faulty source driver IC is included among the plurality of source driver ICs. The method of claim 1,
When the timing controller fails to normally supply a clock preparation signal for setting a clock training period, which is a period in which a clock detection preparation for detecting an abnormality of an internal clock generated by each of the source driver ICs can be performed,
The plurality of source driver ICs may include: a first pattern for determining whether a clock signal is ready to be generated; and
A display device for continuously supplying a second pattern for determining whether the source driver IC itself is normally driven to the timing controller.

Images