KR102453658B1 - Organic light emitting diode display device and its driving method - Google Patents

Abstract

An embodiment of the present invention relates to an organic light emitting display device and a method of driving the same for preventing a timing control circuit from performing abnormal compensation by determining abnormal sensing data or data other than sensing data as sensing data. An organic light emitting display device according to an embodiment of the present invention senses sensing voltages from pixels through a display panel including pixels displaying an image and sensing lines connected to the pixels, and sensing lines, and converts the sensing voltages to digital data. and a plurality of sensing data output circuits for generating sensed data by converting , and a timing control circuit for receiving digital video data and sensed data, and compensating for digital video data based on the sensed data and outputting the digital video data. The timing control circuit according to an embodiment of the present invention masks input of sensing data between periods in which sensing data is received from a plurality of sensing data output circuits.

Description

Organic light emitting display device and driving method thereof

An embodiment of the present invention relates to an organic light emitting display device and a driving method thereof.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have recently been used.

Among them, the organic light emitting display device can be driven at a low voltage, is thin, has an excellent viewing angle, and has a fast response speed. The organic light emitting diode display includes a display panel including a plurality of pixels and a data driver supplying data voltages to data lines connected to the pixels.

The data driver includes a plurality of source drive ICs. The source drive IC includes a sensing data conversion circuit that receives the sensing voltages of the sensing line, converts it into sensing data using an analog-to-digital converter (ADC), and supplies it to the source drive IC.

The timing control circuit receives sensing data to perform external compensation using the sensed data. The timing control circuit first receives a transfer signal (TS) informing that sensing data starts to be supplied before receiving sensing data from any source drive IC that supplies sensing data. Thereafter, the timing control circuit receives sensing data sequentially or non-sequentially from the source drive ICs according to a preset order.

However, when abnormal sensing data or data other than the sensing data is applied to the timing control circuit during a period from when the timing control circuit finishes supplying the sensing data of a certain source drive IC until the sensing data of the next source drive IC is supplied , there is a problem in that the timing control circuit performs abnormal compensation by determining abnormal sensing data or data other than the sensing data as sensing data.

SUMMARY Embodiments of the present invention provide an organic light emitting diode display that prevents a timing control circuit from performing abnormal compensation by determining abnormal sensing data or data other than sensing data as sensing data, and a driving method thereof.

An organic light emitting display device according to an embodiment of the present invention senses sensing voltages from pixels through a display panel including pixels displaying an image and sensing lines connected to the pixels, and sensing lines, and converts the sensing voltages to digital data. and a plurality of sensing data output circuits for generating sensed data by converting , and a timing control circuit for receiving digital video data and sensed data, and compensating for digital video data based on the sensed data and outputting the digital video data. The timing control circuit according to an embodiment of the present invention masks input of sensing data between periods in which sensing data is received from a plurality of sensing data output circuits.

A method of driving an organic light emitting display device according to an embodiment of the present invention includes sensing sensing voltages of pixels, converting the sensing voltages into digital data to generate sensing data, and outputting a transmission signal for notifying the output of the sensing data. Step, outputting arbitrary sensing data, when the output of the arbitrary sensing data is completed, masking the input of the sensing data until output of the next sensing data is started, and outputting the next sensing data includes

An organic light emitting diode display according to an embodiment of the present invention includes a timing control circuit for masking input of sensing data between periods in which sensing data is received from a plurality of sensing data output circuits. Accordingly, the embodiment of the present invention masks the input of the sensing data between the periods in which the sensing data is received from the plurality of sensing data output circuits, so that the digital video data is erroneously compensated based on the abnormal sensing data. can be prevented from doing

The method of driving an organic light emitting display device according to an embodiment of the present invention includes, when output of any sensed data is completed, masking input of the sensed data until output of the next sensed data is started. . Accordingly, in the method of driving an organic light emitting display device according to an embodiment of the present invention, even when abnormal sensing data or non-sensing data is supplied during the masking period, the abnormal sensing data or data that is not the sensing data is recognized as sensing data. It is possible to prevent digital data compensation from being performed.

1 is a block diagram of an organic light emitting display device according to an exemplary embodiment.
FIG. 2 is a circuit diagram illustrating the pixel of FIG. 1 in detail.
3 is a plan view illustrating a lower substrate, a data driver, source drive ICs, flexible films, a timing control circuit, a control printed circuit board, and sensing lines of a display panel of an organic light emitting diode display according to an embodiment of the present invention; .
4 is a block diagram illustrating the source drive IC of FIG. 3 in detail.
5 is a block diagram illustrating a timing control circuit of an organic light emitting diode display according to a first exemplary embodiment of the present invention.
6 is a block diagram illustrating a timing control circuit of an organic light emitting diode display according to a second exemplary embodiment of the present invention.
7 is a waveform diagram of each of the sensing data output circuits of the organic light emitting diode display according to an embodiment of the present invention.
8 is a flowchart of a method of driving an organic light emitting display device according to an exemplary embodiment.
9 is a waveform diagram of sensing data according to a method of driving an organic light emitting display device according to an embodiment of the present invention.

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The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless specifically stated otherwise.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described as 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

"X-axis direction", "Y-axis direction", and "Z-axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is vertical, and is wider than the range in which the configuration of the present invention can function functionally. It may mean having a direction.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an organic light emitting display device according to an exemplary embodiment. FIG. 2 is a circuit diagram illustrating the pixel of FIG. 1 in detail. 3 is a plan view illustrating a lower substrate, a data driver, source drive ICs, flexible films, a timing control circuit, a control printed circuit board, and sensing lines of a display panel of an organic light emitting diode display according to an embodiment of the present invention; . 1 to 3 , an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 100 , a gate driver 110 , a data driver 120 , and a source drive integrated circuit (SD-IC). IC) 121, a timing control circuit (Timing Controller, T-CON) 130, a scan driver (not shown), a sensing driver (not shown), a control printed circuit board (C-PCB) 140 and the flexible films 150 .

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area in which pixels P are provided to display an image. The display panel 100 is provided with gate lines GL1 to GLp, where p is a positive integer greater than or equal to 2), data lines DL1 to DLq, q is a positive integer greater than or equal to 2), and sensing lines SL1 to SLq. do. The data lines DL1 to DLq and the sensing lines SL1 to SLq may cross the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate 101 on which the pixels P are provided and an upper substrate (not shown) performing an encapsulation function.

Each of the pixels P may be connected to any one of the gate lines GL1 to GLp, any one of the data lines DL1 to DLq, and any one of the sensing lines SE1 to SEm. Each of the pixels P may include an organic light emitting diode (OLED) and a pixel driver PD supplying current to the organic light emitting diode (OLED) as shown in FIG. 2 . In FIG. 2, for convenience of explanation, a jth (j is a positive integer satisfying 1≤j≤q) data line DLj, a jth sensing line SLj, and kth (k is 1≤k≤p) Only the pixel P connected to the (satisfactory positive integer) scan line Sk and the k-th sensing signal line SSk is illustrated.

Referring to FIG. 2 , the pixel P includes an organic light emitting diode OLED, an organic light emitting diode OLED, and a pixel driver PD supplying current to a j-th sensing line SLj.

The organic light emitting diode OLED emits light according to a current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to the low potential voltage line ELVSSL to which a low potential voltage lower than the high potential voltage is supplied.

An organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In an organic light emitting diode (OLED), when a voltage is applied to an anode electrode and a cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and the holes and electrons are combined with each other in the organic light emitting layer to emit light.

The pixel driver PD includes a driving transistor DT, a first transistor ST1 controlled by a scan signal of a scan line Sk, and a second transistor ST1 controlled by a sensing signal of a sensing signal line SSk. It may include a transistor ST2 and a capacitor C. When a scan signal is supplied from the scan line Sk connected to the pixel P in the display mode, the pixel driver PD receives the data voltage of the data line DLj connected to the pixel P, and receives the data voltage. A current of the driving transistor DT is supplied to the organic light emitting diode OLED. The pixel driver PD receives the sensing voltage of the data line DLj connected to the pixel P when a scan signal is supplied from the scan line Sk connected to the pixel P in the sensing mode, and the driving transistor ( DT) flows through the sensing line SLj connected to the pixel P.

The driving transistor DT is provided between the high potential voltage line ELVDDL and the organic light emitting diode OLED. The driving transistor DT adjusts a current flowing from the high potential voltage line ELVDDL to the organic light emitting diode OLED according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1 , the source electrode is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode is a high potential to which a high potential voltage is supplied. It may be connected to the voltage line ELVDDL.

The first transistor ST1 is turned on by the k-th scan signal of the k-th scan line Sk to supply the voltage of the j-th data line DLj to the gate electrode of the driving transistor DT. The gate electrode of the first transistor T1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the driving transistor DT, and the second electrode is connected to the j-th data line DLj. can be The first transistor ST1 may be collectively referred to as a scan transistor.

The second transistor ST2 is turned on by the k-th sensing signal of the k-th sensing signal line SSk to connect the j-th sensing line SLj to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the k-th sensing signal line SSk, the first electrode is connected to the j-th sensing line SLj, and the second electrode is connected to the source electrode of the driving transistor DT. can be connected. The second transistor ST2 may be collectively referred to as a sensing transistor.

The capacitor C is provided between the gate electrode and the source electrode of the driving transistor DT. The capacitor C stores a difference voltage between the gate voltage and the source voltage of the driving transistor DT.

In FIG. 2 , the driving transistor DT and the first and second transistors ST1 and ST2 are mainly described as being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it should be noted that the present invention is not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In addition, the first electrode may be a source electrode and the second electrode may be a drain electrode, but it should be noted that the present invention is not limited thereto. That is, the first electrode may be a drain electrode and the second electrode may be a source electrode.

In the display mode, when a scan signal is supplied to the k-th scan line Sk, the data voltage of the j-th data line DLj is supplied to the gate electrode of the driving transistor DT, and is applied to the k-th sensing signal line SSk. When the sensing signal is supplied, the initialization voltage of the j-th sensing line SEj is supplied to the source electrode of the driving transistor DT. Accordingly, in the display mode, the current of the driving transistor DT flowing according to the voltage difference between the voltage of the gate electrode and the voltage of the source electrode of the driving transistor DT is supplied to the organic light emitting diode OLED, and the organic light emitting diode OLED ) emits light according to the current of the driving transistor DT. In this case, since the data voltage is a voltage that compensates for the threshold voltage and electron mobility of the driving transistor DT, the current of the driving transistor DT does not depend on the threshold voltage and electron mobility of the driving transistor DT.

In the sensing mode, when a scan signal is supplied to the k-th scan line Sk, the sensing voltage of the j-th data line is supplied to the gate electrode of the driving transistor DT, and the sensing signal is applied to the k-th sensing signal line SSk. When supplied, the initialization voltage of the j-th sensing line SLj is supplied to the source electrode of the driving transistor DT. In addition, when a sensing signal is supplied to the k-th sensing signal line SSk, the second transistor ST2 is turned on and the driving transistor DT flows according to a voltage difference between the voltage of the gate electrode and the voltage of the source electrode of the driving transistor DT. The current of the transistor DT flows to the j-th sensing line SLj.

The gate driver 120 receives the gate control signal GCS from the timing control circuit 130 , generates gate signals according to the gate control signal GCS, and supplies them to the gate lines GL1 to GLp.

The data driver 120 may include a plurality of source drive ICs 121 as shown in FIG. 3 . Each of the source drive ICs 121 may be mounted on each of the flexible films 150 . Each of the flexible films 150 may be provided as a chip on film (COF). The chip-on-film may include a base film such as polyimide and a plurality of conductive lead wires provided on the base film. Each of the flexible films 150 may be bent or bent. Each of the flexible films 150 may be attached to the lower substrate 101 and the Control Printed Circuit Board (C-PCB) 140 of the display panel 100 . In particular, each of the flexible films 150 may be attached to the lower substrate 101 using an anisotropic conductive film (ACF) using a tape automated bonding (TAB) method, and thus the source drive IC 121 ) may be connected to the data lines DL1 to DLq.

The control printed circuit board 140 may be attached to the flexible films 150 . The control printed circuit board 140 may mount the timing control circuit 130 as shown in FIG. 3 .

Each of the source drive ICs 121 may include a data voltage supply unit 210 , an initialization voltage supply unit 220 , and a switching unit 230 as shown in FIG. 4 . In addition, each of the source drive ICs 121 may mount the sensing data output circuit 160 as shown in FIG. 4 , and as many sensing data output circuits 160 as the number of the source drive ICs 121 may be mounted. , it should be noted that the present invention is not limited thereto. The sensing data output circuit 160 may be mounted in the timing control circuit 130 or provided on a separate chip in the control printed circuit board 140 .

Each of the sensing data output circuits 160 is connected to the sensing lines SE1 to SEp by the switching unit 220 to sense currents flowing through the respective sensing lines SL1 to SLq. Each of the sensing data output circuits 160 converts currents flowing through each of the sensing lines SL1 to SLq into sensing voltages. Each of the sensing data output circuits 160 generates sensing data SEN by converting sensing voltages into digital data using an analog-to-digital converter (ADC). Each of the sensing data output circuits 160 outputs the sensing data SEN to the timing control circuit 130 .

Also, before outputting the sensing data SEN to the timing control circuit 130 , any one of the sensing data output circuits 160 among the plurality of sensing data output circuits 160 informs that the sensing data SEN is supplied. The transfer signal may be output to the timing control circuit 130 . For example, the sensing data output circuit 160 that first outputs the sensing data SEN among the plurality of sensing data output circuits 160 outputs the sensing data SEN to the timing control circuit 130 before outputting the sensing data SEN. The transfer signal may be output to the timing control circuit 130 .

When the sensing data output circuit 160 is mounted on each of the source drive ICs 121 , the sensing data SEN output may be individually performed for each of the source drive ICs 121 , and the output of the sensing data SEN may be performed separately from the source drive ICs 121 . less affected by the generated data. In addition, when the sensing data output circuit 160 is mounted on each of the source drive ICs 121 , there is no need to provide a separate chip in the control printed circuit board 140 , thereby reducing manufacturing costs.

The data voltage supply unit 210 is connected to the data lines DL1 to DLq to supply data voltages. The data voltage supply unit 210 receives digital video data DATA and a data driver control signal DCS from the timing control circuit 130 . The data voltage supply unit 210 converts the digital video data DATA into data voltages according to the data driver control signal DCS in the display mode and supplies the data voltages to the data lines DL1 to DLq.

The data voltage is a voltage for emitting light with a predetermined luminance of the organic light emitting diode (OLED) of the pixel (P). For example, when the digital video data DATA supplied to the data driver 120 is 8 bits, the data voltage may be supplied as any one of 256 voltages. The data voltage supply unit 210 converts the digital video data DATA into a sensing voltage according to the data driver control signal DCS in the sensing mode and supplies it to the data lines DL1 to DLq. The sensing voltage is a voltage for sensing the current of the driving transistor DT of the pixel P.

The initialization voltage supply unit 220 is connected to the sensing lines SL1 to SLq to supply an initialization voltage. The initialization voltage supply unit 220 may include initialization switches SWR1 to SWRq as shown in FIG. 4 . In this case, the initialization voltage supply unit 220 switches the initialization switches SWR1 to SWRq in response to an initialization signal input from the timing control circuit 130 to initialize the sensing lines SL1 to SLq to which the initialization voltage is supplied. It can be connected to the voltage line VREFL.

The switching unit 230 is connected to the sensing lines SL1 to SLq and the sensing data output circuit 160 . The switching unit 230 connects the sensing lines SL1 to SLq to the sensing data output circuit 160 in a predetermined order. For example, the predetermined order may be a sequential order. In this case, the switching unit 230 sequentially connects the sensing data output circuit 160 from the first sensing line SL1 to the qth sensing line SLq. can do it

The switching unit 230 may include switches S1 to Sq connected to the sensing lines SL1 to SLq as shown in FIG. 4 . In this case, the switching unit 230 switches the switches S1 to Sq according to switch signals input from the timing control circuit 130 , thereby outputting the sensing data in a predetermined order to the sensing lines SL1 to SLq. It can be connected to the circuit 160 .

The reference voltage supply unit 300 generates an initialization voltage. The reference voltage supply unit 300 is connected to the initialization voltage line VREFL to transmit the initialization voltage to the initialization voltage supply unit 220 .

The scan driver (not shown) is connected to the scan line Sk. The scan driver supplies the scan signal to the scan line Sk according to the scan timing control signal input from the timing control circuit 130 . The scan timing control signal in the display mode and the scan timing control signal in the sensing mode may be different from each other. For this reason, the scan signal waveform of the scan driver in the display mode and the scan signal waveform of the scan driver in the sensing mode may be different from each other.

The sensing driver (not shown) is connected to the sensing signal line SSk. The sensing driver supplies the sensing signal to the sensing signal line SSk according to the sensing timing control signal input from the timing control circuit 130 . The sensing timing control signal in the display mode and the sensing timing control signal in the sensing mode may be different from each other. For this reason, the sensing signal waveform of the sensing driver in the display mode and the sensing signal waveform of the sensing driver in the sensing mode may be different from each other.

Each of the scan driver and the sensing driver may include a plurality of transistors and may be directly formed in the non-display area of the display panel 100 in a gate driver in panel (GIP) method. Alternatively, each of the scan driver and the sensing driver may be formed in the form of a driving chip and mounted on the flexible film 150 connected to the display panel 100 .

The timing control circuit 130 receives digital video data DATA and a timing signal TS from an external system board (not shown). The timing signal TS includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DCLK). may include The timing control circuit 130 receives the sensing data SEN from the plurality of sensing data output circuits 160 .

The timing control circuit 130 compensates the digital video data DATA based on the sensing data SEN. The timing control circuit 130 generates compensation digital video data DATA`. A method of compensating for digital video data DATA of the timing control circuit 130 will be described later with reference to FIGS. 5 and 6 .

Also, the timing control circuit 130 masks the input of the sensing data SEN between periods in which the sensing data SEN is received from the plurality of sensing data output circuits 160 . The plurality of sensing data output circuits 160 sequentially output the sensing data SEN according to a predetermined order. After one sensing data output circuit 160 outputs the sensing data SEN, a predetermined time exists before the next sensing data output circuit 160 outputs the sensing data SEN. The timing control circuit 130 does not receive the sensing data SEN input for a predetermined time.

That is, in a normal case, there is no input of the sensing data SEN between the periods in which the sensing data SEN from the plurality of sensing data output circuits 160 are received, and the sensing data SEN is output between the periods in which the sensing data SEN is received. The sensed data SENs are abnormal sensing data SENs. When the timing control circuit 130 receives the abnormal sensing data SEN, the timing control circuit 130 erroneously compensates the digital video data DATA based on the abnormal sensing data SEN. The timing control circuit 130 masks the input of the sensing data SEN between the periods in which the sensing data SEN is received from the plurality of sensing data output circuits 160 , based on the abnormal sensing data SEN. Accordingly, it is possible to prevent erroneous compensation for the digital video data DATA.

The timing control circuit 130 generates timing control signals for controlling operation timings of the gate driver 110 , the data driver 120 , the scan driver, and the sensing driver. The timing control signals are the gate timing control signal GCS for controlling the operation timing of the gate driver 110 , the data timing control signal DCS for controlling the operation timing of the data driver 120 , and the operation timing of the scan driver. and a scan timing control signal for controlling the sensing timing control signal and a sensing timing control signal for controlling the operation timing of the sensing driver.

The timing control circuit 130 operates the data driver 120 , the scan driver, and the sensing driver in any one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixels P of the display panel 100 display an image, and the sensing mode is a mode in which the current of the driving transistor DT of each of the pixels P of the display panel 100 is sensed. When the waveform of the scan signal supplied to each of the pixels P and the waveform of the sensing signal are changed in each of the display mode and the sensing mode, the data timing control signal DCS, the scan timing control signal and the The sensing timing control signal may also be changed. Accordingly, the timing control circuit 130 generates the data timing control signal DCS, the scan timing control signal, and the sensing timing control signal corresponding to the corresponding mode according to which mode is the display mode and the sensing mode.

The timing control circuit 130 outputs the gate timing control signal GCS to the gate driver 110 . The timing control circuit 130 outputs the compensated digital video data DATA` and the data timing control signal DCS to the data driver 120 . The timing control circuit 60 outputs the scan timing control signal to the scan driver. The timing control circuit 60 outputs the sensing timing control signal to the sensing driver.

The timing control circuit 130 may supply an initialization signal for controlling the initialization switches SWR1 to SWRq of the initialization voltage supply unit 220 to the initialization voltage supply unit 220 . The timing control circuit 130 may output switching control signals for controlling the switches S1 to Sq of the switching unit 230 to the switching unit 230 .

Also, the timing control circuit 130 generates a mode signal for driving the data driver 120 , the scan driver, and the sensing driver according to which mode of the display mode and the sensing mode is driven. The timing control circuit 130 operates the data driver 120 , the scan driver, and the sensing driver in any one of a display mode and a sensing mode according to a mode signal.

5 is a block diagram illustrating the timing control circuit 130 of the organic light emitting diode display according to the first embodiment of the present invention.

The timing control circuit 130 according to the first embodiment of the present invention includes a sensing voltage input unit 131 , an internal clock generation unit 132 , a data timing control signal output unit 133 , and a gate timing control signal output unit 134 . and a digital data compensator 135 .

The sensing voltage input unit 131 receives the sensing data SEN from the sensing data output circuit 160 and receives the internal clock CLK generated from the internal clock generation unit 132 . The sensing voltage input unit 131 starts to count the number of pulses of the internal clock CLK after receiving the sensing data SEN. To this end, the sensing voltage input unit 131 counts the number of rising edges or falling edges of the pulses of the internal clock CLK.

The sensing voltage input unit 131 includes a sensing period, which is a period in which any one sensing data output circuit 160 supplies the sensing data SEN, and a sensing period in which all sensing data output circuits 160 supply the sensing data SEN. It is possible to set a masking period, which is a period not to be performed.

In the sensing period, one sensing data output circuit 160 supplies sensing data SEN according to a preset order. The sensing voltage input unit 131 receives sensing data SEN in the sensing period.

In the masking period, all of the sensing data output circuits 160 do not supply the sensing data SEN. The sensing voltage input unit 131 does not receive data during the masking period. In order to prevent data from being input from the sensing data output circuit 160 in the masking period, the sensing voltage input unit 131 connects portions connected to the sensing data output circuit 160 in the masking period to have a high resistance or a logic circuit. Maintain the high impedance (Hi-Z) state, which is an open floating state.

When the number of rising or falling edges of the pulse of the internal clock CLK is m (m is a positive integer greater than or equal to 2) after starting to receive the sensing data SEN, the sensing voltage input unit 131 performs masking in the sensing period. switch to period

The sensing voltage input unit 131 switches from the masking period to the sensing period when the number of rising edges or falling edges of the pulse of the internal clock CLK is n (n is a positive integer greater than or equal to 2) after switching to the masking period. . Through this, it is possible to set the length of the masking period without externally supplying a separate signal.

The internal clock generator 132 generates an internal clock CLK. The internal clock generator 132 inputs the internal clock CLK to the sensing voltage inputter 132 .

The data timing control signal output unit 133 receives a timing signal TS from an external system board (not shown) and receives digital compensation data DATA′ from the digital data compensator 135 . The data timing control signal output unit 133 outputs the compensation digital data DATA` and the data timing control signal DCS to the data driver 120 . The data timing control signal output unit 133 outputs the horizontal synchronization signal Hsync to the gate timing control signal output unit 134 for synchronization with the gate timing control signal output unit 134 .

The gate timing control signal output unit 134 receives the timing signal TS from an external system board (not shown) and receives the horizontal synchronization signal Hsync from the data timing control signal output unit 133 . The gate timing control signal output unit 134 outputs the gate timing control signal GCS to the gate driver 110 .

The digital data compensator 135 receives digital video data DATA from an external system board (not shown), and receives sensing data SEN from the sensing voltage input unit 131 . The digital data compensator 135 may store the received sensing data SEN in a memory (not shown). Also, the digital data compensator 135 receives the mode signal.

The digital data compensator 135 compensates the digital video data DATA with the compensation digital data DATA` based on the sensed data SEN in the display mode, thereby increasing the threshold voltage and electron mobility of the driving transistor DT. may be compensated externally.

Specifically, the sensing data SEN is data sensed by a current flowing through the driving transistor DT when a predetermined data voltage is supplied to the gate electrode of the driving transistor DT of the pixel P. The compensation digital data DATA` is data obtained by compensating for the threshold voltage and electron mobility of the driving transistor DT of each of the pixels P. The digital data compensator 135 may calculate data for compensating for the threshold voltage and electron mobility of the driving transistor DT from the sensing data SEN using a predetermined algorithm, and converts the calculated data into digital video data. Compensation digital data DATA` can be calculated by applying to (DATA).

The digital data compensator 135 transmits the compensation digital data DATA` to the data timing control signal output unit 133 in the display mode. The compensation digital data DATA` is data obtained by compensating the digital video data DATA so as to reduce distortion caused by the characteristics of the driving transistor DT. 133), it is possible to reduce distortion according to the characteristics of the driving transistor DT compared to the case of directly supplying it.

The timing control circuit 130 according to the first embodiment of the present invention starts receiving the sensing data SEN and then when the number of rising edges or falling edges of the pulse of the internal clock CLK is m, the masking period in the sensing period and a sensing voltage input unit 131 for preventing data from being input by switching to . Accordingly, the timing control circuit according to the first embodiment of the present invention prevents abnormal sensing data (SEN) or data other than the sensing data (SEN) from being input during the masking period, and thus abnormal sensing data (SEN) or sensing data It is possible to prevent erroneous digital data compensation by determining data other than (SEN) as sensing data (SEN).

6 is a block diagram illustrating a timing control circuit 130 of an organic light emitting diode display according to a second exemplary embodiment of the present invention.

The timing control circuit 130 according to the second embodiment of the present invention includes a sensing voltage input unit 131 , a data timing control signal output unit 133 , a gate timing control signal output unit 134 , and a digital data compensator 135 . includes

The sensing voltage input unit 131 receives sensing data SEN from the sensing data output circuit 160 and receives a dot clock DCLK from an external system board (not shown). The sensing voltage input unit 131 starts to receive the sensing data SEN and then starts counting the number of pulses of the dot clock DCLK. To this end, the sensing voltage input unit 131 counts the number of rising edges or falling edges of the pulse of the dot clock DCLK.

The sensing voltage input unit 131 includes a sensing period, which is a period in which any one sensing data output circuit 160 supplies the sensing data SEN, and a sensing period in which all sensing data output circuits 160 supply the sensing data SEN. It is possible to set a masking period, which is a period not to be performed. The sensing period and the masking period of the sensing voltage input unit 131 according to the second embodiment of the present invention are the same as the sensing period and the masking period of the sensing voltage input unit 131 according to the first embodiment of the present invention. A description is omitted.

When the number of rising edges or falling edges of the pulse of the dot clock DCLK is m (m is a positive integer greater than or equal to 2) after starting to receive the sensing data SEN, the sensing voltage input unit 131 performs masking in the sensing period. switch to period

The sensing voltage input unit 131 switches from the masking period to the sensing period when the number of rising or falling edges of the pulse of the dot clock DCLK is n (n is a positive integer greater than or equal to 2) after switching to the masking period . Accordingly, the length of the masking period may be set using the dot clock DCLK input to the existing timing control circuit 130 without inputting a separate external signal.

The data timing control signal output unit 133 receives the compensation digital data DATA′, the compensation vertical synchronization signal Vsync′, and the compensation data enable signal DE′ from the digital data compensation unit 135 . The data timing control signal output unit 133 outputs the compensation digital data DATA` and the data timing control signal DCS to the data driver 120 .

The gate timing control signal output unit 134 receives the compensation horizontal synchronization signal Hsync′ from the digital data compensator 135 . The gate timing control signal output unit 134 outputs the gate timing control signal GCS to the gate driver 110 .

The digital data compensator 135 receives and senses digital video data DATA, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE from an external system board (not shown). The sensing data SEN is received from the voltage input unit 131 . The digital data compensator 135 may store the received sensing data SEN in a memory (not shown). Also, the digital data compensator 135 receives the mode signal.

The digital data compensator 135 compensates the digital video data DATA with the compensation digital data DATA` based on the sensed data SEN in the display mode, thereby increasing the threshold voltage and electron mobility of the driving transistor DT. may be compensated externally.

Specifically, the sensing data SEN is data sensed by a current flowing through the driving transistor DT when a predetermined data voltage is supplied to the gate electrode of the driving transistor DT of the pixel P. The compensation digital data DATA` is data obtained by compensating for the threshold voltage and electron mobility of the driving transistor DT of each of the pixels P. The digital data compensator 135 may calculate data for compensating for the threshold voltage and electron mobility of the driving transistor DT from the sensing data SEN using a predetermined algorithm, and converts the calculated data into digital video data. Compensation digital data DATA` can be calculated by applying to (DATA).

In addition, the digital data compensator 135 compensates the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, respectively, the compensation vertical synchronization signal Vsync' and the compensated horizontal synchronization signal Hsync'. and a compensation data enable signal DE`. The compensation vertical synchronization signal Vsync′, the compensation horizontal synchronization signal Hsync′, and the compensation data enable signal DE′ are signals that are synchronized with the sensing data SEN.

The digital data compensator 135 transmits the compensation digital data DATA`, the compensation vertical synchronization signal Vsync`, and the compensation data enable signal DE` to the data timing control signal output unit 133 in the display mode, , the compensated horizontal synchronization signal Hsync` is transmitted to the gate timing control signal output unit 134 . The compensation digital data DATA` is data obtained by compensating the digital video data DATA so as to reduce distortion caused by the characteristics of the driving transistor DT. 133), it is possible to reduce distortion according to the characteristics of the driving transistor DT compared to the case of directly supplying it. In addition, since the compensation vertical synchronization signal (Vsync`), the compensation horizontal synchronization signal (Hsync`), and the compensation data enable signal (DE`) are signals synchronized with the sensing data SEN, more accurate compensation digital data ( DATA`) can be printed.

The timing control circuit 130 according to the second embodiment of the present invention starts to receive the sensing data SEN and then when the number of rising or falling edges of the pulse of the dot clock DCLK is m, the masking period in the sensing period and a sensing voltage input unit 131 for preventing data from being input by switching to . Accordingly, the timing control circuit according to the second embodiment of the present invention prevents abnormal sensing data (SEN) or data other than the sensing data (SEN) from being input during the masking period, and thus abnormal sensing data (SEN) or sensing data It is possible to prevent erroneous digital data compensation by determining data other than (SEN) as sensing data (SEN).

7 is a waveform diagram of each of the sensing data output circuit 160 of the organic light emitting diode display according to an exemplary embodiment of the present invention.

In FIG. 7 , five sensing data output circuits 160 include first sensing data SD1 , third sensing data SD3 , fifth sensing data SD5 , second sensing data SD2 , and fourth sensing data ( SD1 ). SD4), the case in which the sensing data output circuits 160 output the sensing data SEN has been exemplified, but it should be noted that the present invention is not limited thereto. That is, the number of the sensing data output circuits 160 may be greater or less than this, and the sensing data output circuits 160 sequentially or non-sequentially output the sensing data SEN. Accordingly, the sensing data SEN may be output.

In the following description, the first sensing data output circuit outputs the first sensing data SD1 , the second sensing data output circuit outputs the second sensing data SD2 , and the third sensing data output circuit outputs the third sensing data It is defined that the data SD3 is output, the fourth sensing data output circuit outputs the fourth sensing data SD4 , and the fifth sensing data output circuit outputs the fifth sensing data SD5 .

Before outputting the first sensing data SD1 , the first sensing data output circuit supplies a transmission signal TSP for informing the timing control circuit 130 that the first sensing data SD1 is output. A period in which the transmission signal TSP is supplied may be defined as a start period ST. The length of the start period ST may be set in consideration of a time until the timing control circuit 130 completes preparation for receiving the first sensing data SD1 . When the timing control circuit 130 prepares to receive the first sensing data SD1 only when the transmission signal TSP is supplied, the timing control circuit 130 senses abnormal sensing data or data that is not sensed data. It is possible to reduce the case of making judgments based on data and performing wrong compensation.

A period during which the first sensing data output circuit outputs the first sensing data SD1 may be defined as a first sensing period SEP1 . From the start time of the first sensing period SEP1 , the timing control circuit 130 according to the first embodiment has the internal clock CLK, and the timing control circuit 130 according to the second embodiment pulses the dot clock DCLK. Start counting. When the number of rising or falling edges of the pulse of the internal clock CLK or dot clock DCLK is m (m is a positive integer greater than or equal to 2), the first sensing period SEP1 is switched to the masking period MAP. . The value of m may be set in consideration of a period during which the first sensing data output circuit completes the output of the first sensing data SD1 .

In this case, after the sensing data output circuit of one of the plurality of sensing data output circuits completes the output of the sensed data, the other sensing data output circuit outputs the sensed data during the period in which the rising edge or the falling edge of the n pulses appears. It can be set to be the same as the masking period MAP, which is a period before starting . Accordingly, it is possible to block the input of data during the period in which the rising edge or the falling edge of the n pulses appear, thereby preventing incorrect sensing data or digital data other than the sensing data from being input during a period in which sensing data is not received. .

When the first sensing data output circuit finishes outputting the first sensing data SD1 , the masking period MAP starts. In the masking period MAP, the sensing data SEN is not supplied from all sensing data output circuits. From the start time of the masking period MAP, the timing control circuit 130 according to the first embodiment controls the internal clock CLK, and the timing control circuit 130 according to the second embodiment controls the number of pulses of the dot clock DCLK. start counting When the number of rising or falling edges of the pulse of the internal clock CLK or dot clock DCLK is n (n is a positive integer greater than or equal to 2), the masking period is switched to the sensing period. The value of n is set in consideration of a period from when the first sensing data output circuit finishes outputting the first sensing data SD1 until the third sensing data output circuit starts outputting the third sensing data SD3. Preferably, the period in which the rising edge or the falling edge of the n pulses appears may be set as the masking period MAP.

When the masking period MAP after completing the output of the first sensing data SD1 ends, the third sensing period SEP3 in which the third sensing data output circuit outputs the third sensing data SD3 begins. From the start time of the third sensing period SEP3 , the timing control circuit 130 according to the first embodiment has the internal clock CLK, and the timing control circuit 130 according to the second embodiment pulses the dot clock DCLK. Start counting. When the number of rising edges or falling edges of the pulses of the internal clock CLK or dot clock DCLK is m, the third sensing period SEP3 is switched to the masking period MAP. The value of m may be set in consideration of the time when the third sensing data output circuit completes the output of the third sensing data SD3, and preferably, the period during which the rising edge or the falling edge of the m pulses appears is the third sensing period. It can be set as a period (SEP3).

When the third sensing data output circuit finishes outputting the third sensing data SD3 , the masking period MAP starts. Since the masking period MAP after the output of the third sensing data SD3 is completed is the same as the masking period MAP after the output of the first sensing data SD1 is completed, a detailed description thereof will be omitted.

When the masking period MAP after completing the output of the third sensing data SD3 ends, a fifth sensing period SEP5 in which the fifth sensing data output circuit outputs the fifth sensing data SD5 starts. From the start of the fifth sensing period SEP5 , the timing control circuit 130 according to the first embodiment has the internal clock CLK, and the timing control circuit 130 according to the second embodiment pulses the dot clock DCLK. Start counting. When the number of rising edges or falling edges of the pulses of the internal clock CLK or dot clock DCLK is m, the fifth sensing period SEP5 is switched to the masking period MAP. The value of m may be set in consideration of the time when the fifth sensing data output circuit completes the output of the fifth sensing data SD5 , and preferably, the period during which the rising edge or the falling edge of the m pulses appears is the fifth sensing period. It can be set as a period (SEP5).

When the fifth sensing data output circuit finishes outputting the third sensing data SD5 , the masking period MAP starts. Since the masking period MAP after completing the output of the fifth sensing data SD5 is the same as the masking period MAP after completing the output of the first sensing data SD1 and the third sensing data SD3, this A detailed description thereof will be omitted.

When the masking period MAP after completing the output of the fifth sensing data SD5 ends, the second sensing period SEP2 in which the second sensing data output circuit outputs the second sensing data SD2 begins. From the start time of the second sensing period SEP3 , the timing control circuit 130 according to the first embodiment has the internal clock CLK, and the timing control circuit 130 according to the second embodiment pulses the dot clock DCLK. Start counting. When the number of rising edges or falling edges of the pulses of the internal clock CLK or dot clock DCLK is m, the second sensing period SEP2 is switched to the masking period MAP. The value of m may be set in consideration of the time when the second sensing data output circuit completes the output of the second sensing data SD2, and preferably, the period during which the rising edge or the falling edge of the m pulses appears is determined by the second sensing. It can be set as the period (SEP2).

When the second sensing data output circuit finishes outputting the second sensing data SD2 , the masking period MAP starts. The masking period MAP after completing the output of the second sensing data SD3 is the masking period after completing the output of the first sensing data SD1 , the third sensing data SD3 and the fifth sensing data SD5 . Since it is the same as (MAP), a detailed description thereof will be omitted.

When the masking period MAP after completing the output of the second sensing data SD2 ends, the fourth sensing period SEP4 in which the fourth sensing data output circuit outputs the fourth sensing data SD4 begins. From the start time of the fourth sensing period SEP4 , the timing control circuit 130 according to the first embodiment has the internal clock CLK, and the timing control circuit 130 according to the second embodiment pulses the dot clock DCLK. Start counting. When the number of rising edges or falling edges of the pulses of the internal clock CLK or dot clock DCLK is m, the fourth sensing period SEP4 is switched to the masking period MAP. The value of m may be set in consideration of the time when the fourth sensing data output circuit completes the output of the fourth sensing data SD4, and preferably, the period during which the rising edge or the falling edge of the m pulses appears is determined by the fourth sensing. It can be set as a period (SEP4).

When the fourth sensing data output circuit finishes outputting the fourth sensing data SD4 , the masking period MAP starts. The masking period MAP after the output of the fourth sensing data SD4 is completed is the first sensing data SD1 , the third sensing data SD3 , the fifth sensing data SD5 , and the second sensing data SD2 . Since it is the same as the masking period MAP after completing the output of , a detailed description thereof will be omitted.

Hereinafter, a method of driving an organic light emitting display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 8 and 9 . 8 is a flowchart of a method of driving an organic light emitting display device according to an exemplary embodiment. 9 is a waveform diagram of sensing data SEN according to a method of driving an organic light emitting display device according to an embodiment of the present invention.

First, the timing control circuit 130 prepares to receive the sensing data SEN. To this end, each of the plurality of source drive ICs 212 senses the sensing voltage of the pixels P provided in the display panel 100 . The sensing data output circuits 160 convert the sensing voltage into digital data to generate sensing data SEN. The sensing data output circuits 160 may be mounted on each of the source drive ICs 121 . (S101 in FIG. 8)

Second, it is checked whether a transmission signal TSP informing the timing control circuit 130 that the sensing data SD1 is output is supplied. First, the arbitrary sensing data output circuit 160 for supplying the sensed data to the timing control circuit 130 outputs the sensing data SEN before outputting the first sensing data SD1 to the timing control circuit ( 130) is supplied by a transmission signal TSP. A period in which the transmission signal TSP is supplied may be defined as a start period ST. The length of the start period ST may be set in consideration of a time until the timing control circuit 130 completes preparation for receiving the first sensing data SD1 .

Accordingly, among the plurality of sensing data output circuits 160 , any sensing data output circuit 160 that first supplies the sensing data SEN to the timing control circuit performs timing control on the first sensing data SD1 . Step S101 of FIG. 8 is continuously maintained until the transmission signal TSP indicating that the first sensing data SD1 is supplied before being supplied to the circuit 130 is supplied to the timing control circuit 130 . In addition, when the transmission signal TSP is supplied to the timing control circuit 130 , the following step is performed. (S102 in FIG. 8)

Third, the arbitrary sensing data output circuit 160 supplies the first sensing data SD1 to the timing control circuit 130 . From a start point at which the first sensing data SD1 is supplied, the timing control circuit 130 according to the first embodiment has an internal clock CLK, and the timing control circuit 130 according to the second embodiment has a dot clock DCLK. Start counting the number of pulses. (S103 in FIG. 8)

Fourth, it is checked whether the supply of the first sensing data SD1 is completed. When the number of rising edges or falling edges of the pulses of the internal clock CLK or dot clock DCLK is m, the fourth sensing period SEP4 is switched to the masking period MAP. The value of m may be set in consideration of the time when an arbitrary sensing data output circuit completes the output of the first sensing data SD1, and preferably, the period during which the rising edge or the falling edge of the m pulses appears is first sensed. It can be set as the period (SEP1). (S104 in FIG. 8)

Fifth, the timing control circuit 130 maintains the masking period MA in which data is not received for a preset period from the time when the supply of the first sensing data SD1 is completed. That is, when the output of any sensing data is completed, the input of the sensing data is masked until the output of the next sensing data is started. From the start time of the masking period MA, the timing control circuit 130 according to the first embodiment controls the internal clock CLK, and the timing control circuit 130 according to the second embodiment controls the number of pulses of the dot clock DCLK. start counting

When the number of rising or falling edges of the pulse of the internal clock CLK or dot clock DCLK is n (n is a positive integer greater than or equal to 2), the masking period is switched to the sensing period. In the masking period MA, all of the sensing data output circuits 160 do not supply the sensing data SEN. The sensing voltage input unit 131 does not receive data during the masking period MA. Accordingly, even if abnormal sensing data or non-sensing data is supplied in the masking period MA, it is possible to prevent erroneous digital data compensation by recognizing abnormal sensing data or data not sensing data as sensing data. The value of n may be set in consideration of a time from when the output of the first sensing data SD1 is completed until the supply of the second sensing data SD3 is started.

In this case, after the sensing data output circuit of one of the plurality of sensing data output circuits completes the output of the sensed data, the other sensing data output circuit outputs the sensed data during the period in which the rising edge or the falling edge of the n pulses appears. It can be set to be the same as the masking period MAP, which is a period before starting . Accordingly, it is possible to block the input of data during the period in which the rising edge or the falling edge of the n pulses appear, thereby preventing incorrect sensing data or digital data other than the sensing data from being input during a period in which sensing data is not received. .

In order to prevent data from being inputted from the sensing data output circuit 160 in the masking period MA, in the masking period MA, portions connected to the sensing data output circuit 160 are formed to have a high resistance or a logic circuit. The high impedance (Hi-Z) state, which is an open floating state, is maintained. Through this, the masking period MA can be implemented without adding a separate chip or driving circuit inside the timing control circuit 130 or on the control printed circuit board 140 . (S105 in FIG. 8)

Sixth and second, another sensing data output circuit 160 that supplies the sensing data SD3 to the timing control circuit supplies the second sensing data SD3 to the timing control circuit. From a start point at which the second sensing data SD3 is supplied, the timing control circuit 130 according to the first embodiment has an internal clock CLK, and the timing control circuit 130 according to the second embodiment uses a dot clock DCLK. Start counting the number of pulses.

In FIGS. 8 and 9 , the five sensing data output circuits 160 are the first sensing data SD1 , the third sensing data SD3 , the fifth sensing data SD5 , the second sensing data SD2 and the fourth A case in which the sensing data output circuits 160 output the sensing data SEN in the order of the sensing data SD4 is exemplified. In addition, although the case where the first sensing data output circuit is mounted on the first source drive IC and the third sensing data output circuit is mounted on the third source drive IC has been exemplified, it should be noted that the present invention is not limited thereto. That is, the number of the sensing data output circuits 160 may be greater or less than this, and the sensing data output circuits 160 sequentially or non-sequentially output the sensing data SEN. Accordingly, the sensing data SEN may be output. In addition, each sensing data output circuit 160 may be mounted on the control printed circuit board 140 or mounted on the timing control circuit 130 . (S106 in FIG. 8)

Seventh, it is checked whether the supply of the second sensing data SD3 is completed. When the number of rising edges or falling edges of the pulses of the internal clock CLK or dot clock DCLK is m, the third sensing period SEP3 is switched to the masking period MA. The value of m may be set in consideration of a time for which an arbitrary sensing data output circuit completes the output of the second sensing data SD3 . (S107 in FIG. 8)

In FIG. 8 , from the start of the supply of the first sensing data SD1 to the stage of confirming whether the supply of the second sensing data SD3 is completed, the same as in the case after the supply of the first sensing data SD1 is completed, each A masking period (MA) during which the supply of sensing data of This is set Since the masking period MA after completing the output of each sensing data is the same as the masking period MA after completing the output of the first sensing data SD1, a detailed description thereof will be omitted.

The embodiment of the present invention includes a timing control circuit 130 for masking the input of the sensing data SEN between the periods in which the sensing data SEN is received from the plurality of sensing data output circuits 160 . do. Accordingly, according to the embodiment of the present invention, the input of the sensing data SEN is masked between the periods in which the sensing data SEN are received from the plurality of sensing data output circuits 160 to generate abnormal sensing data SEN. It is possible to prevent erroneous compensation of the digital video data DATA based on .

The method of driving an organic light emitting display device according to an embodiment of the present invention includes, when output of any sensed data is completed, masking input of the sensed data until output of the next sensed data is started. . Accordingly, in the method of driving an organic light emitting display device according to an embodiment of the present invention, even when abnormal sensing data or non-sensing data is supplied during the masking period, the abnormal sensing data or data that is not the sensing data is recognized as sensing data. It is possible to prevent digital data compensation from being performed.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 101: lower substrate
110: gate driver 120: data driver
121: source drive IC 130: timing control circuit
140: control printed circuit board 150: flexible film
160: sensing data output circuit 210: data voltage supply unit
220: initialization voltage supply unit 230: switching unit
300: reference voltage supply GL1 to GLP: gate lines
DL1 to DLq: data lines SL1 to SLq: sensing lines
Sk: scan line SSk: sensing signal line
SENL1~SENL5: sensing data (SEN) lines
SEN: sensed data P: pixel

Claims (9)

a display panel including pixels displaying an image and sensing lines connected to the pixels;
a plurality of sensing data output circuits sensing sensing voltages from the pixels through the sensing lines and converting the sensing voltages into digital data to generate sensing data; and
a timing control circuit for receiving digital video data and the sensing data, and compensating for and outputting the digital video data based on the sensing data;
The timing control circuit is configured to mask the input of the sensing data between periods in which the sensing data is received from the plurality of sensing data output circuits. The method of claim 1,
Further comprising a plurality of source drive ICs for supplying data voltages to data lines connected to the pixels,
Each of the sensing data output circuits is mounted on each of the plurality of source drive ICs. The method of claim 1,
The sensing data output circuit of any one of the plurality of sensing data output circuits outputs a transmission signal for notifying the output of the sensing data to the timing control circuit before outputting the sensing data to the timing control circuit. display device. The method of claim 1,
The period for masking the input of the sensing data is set to be the same as the period in which the rising edge or the falling edge of n (n is a positive integer greater than or equal to 2) pulses of the internal clock generated in the timing control circuit appears. Device. The method of claim 1,
The period for masking the input of the sensing data is set to be the same as a period in which a rising edge or a falling edge of n pulses of the dot clock supplied to the timing control circuit appear. 6. The method of any one of claims 4 or 5,
During the period in which the rising edge or the falling edge of the n pulses appear, one sensing data output circuit among the plurality of sensing data output circuits completes outputting the sensed data, and then the other sensing data output circuit outputs the sensed data. An organic light emitting display device set to be the same as the period before starting. generating sensing data by sensing sensing voltages of pixels and converting the sensing voltages into digital data;
outputting a transmission signal for notifying the output of the sensed data;
outputting arbitrary sensing data;
masking the input of the sensing data until output of the next sensing data is started when the output of the arbitrary sensing data is completed; and
and outputting the next sensed data. 8. The method of claim 7,
In the masking of the input of the sensed data, a rising edge or a falling edge of n (n is a positive integer greater than or equal to 2) pulses of an internal clock generated within the timing control circuit or a dot clock supplied to the timing control circuit appears. A method of driving an organic light emitting diode display maintained for a period of time. 9. The method of claim 8,
The period in which the rising edge or the falling edge of the n pulses appears is set to be the same as a period after the output of the arbitrary sensed data is completed and before the output of the next sensed data is started.

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