KR20180074896A - Display device and timing controller - Google Patents

Abstract

Embodiments of the present invention relate to a display device and a controller for providing a scheme for previously monitoring a situation in which a panel burnt phenomenon occurs, and a structure thereof, thereby preventing the panel burnt phenomenon. The display device includes a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of subpixels are arranged, a controller for transmitting data, a data driving unit for converting the data into a data voltage and outputting the data voltage to the data line, and a cable for connecting the controller and the data driving unit.

Description

DISPLAY DEVICE AND TIMING CONTROLLER [0001]

The present invention relates to a display device and a controller for displaying an image.

2. Description of the Related Art [0002] With the development of an information society, demands for a display device for displaying an image have increased in various forms. Recently, a liquid crystal display device (LCD), a plasma display panel (PDP) Various display devices such as an organic light emitting display device (OLED) and the like are being utilized.

Such a display device includes a display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged, a data driver for driving the plurality of data lines, a gate driver for driving the plurality of gate lines, A controller for controlling the data driver and the gate driver, and the like.

On the other hand, when a defect such as a malfunction of the source driver ICs included in the data driver occurs or a connection failure of a flexible flat cable (FFC) occurs, The voltage may not be supplied or an abnormal data voltage may be supplied.

In the case where the normal supply of the data voltage to the sub-pixel occurs, the display panel may not be normally driven.

In this case, an abnormal overcurrent flows to the corresponding sub-pixel, resulting in abnormal excessive light emission. In severe cases, a burst phenomenon of the display panel may occur.

It is an object of the present embodiments to provide a method and structure for monitoring in advance a situation in which a panel bunting phenomenon may occur and thereby provide a display device and a controller for preventing panel bunting phenomenon.

Another object of the present invention is to provide a display device and a controller for detecting cable opening when a cable between a control board and a source board is not connected in a display device in which a control board and a source board are separately developed, .

Another object of the present invention is to provide a display device and a controller in which a system shutdown does not occur when a plurality of cables are not fastened between a control board and a source board, There is.

One embodiment includes a display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged, a controller that transmits data, a data driver that converts data into data voltages and outputs the data voltages to a data line, And a cable connecting the data driver.

The data driver may transmit to the controller a first lock signal indicating a data reception state of the first interface and a second lock signal indicating a data reception state of the second interface.

The controller may execute the panel bunching prevention process based on the first lock signal and the second lock signal received from the data driving unit or may not execute the panel bunching prevention process.

According to another embodiment of the present invention, there is provided an information processing apparatus comprising: a transmitter for transmitting data to a data driver; a first lock signal indicating a data reception state of the first interface received from the data driver and a second lock signal indicating a data reception state of the second interface; And a panel bunch preventing unit that executes the panel bunching prevention process based on the first lock signal and the second lock signal received from the data driving unit or does not execute the panel bunching prevention process.

As described above, according to the embodiments of the present invention, it is possible to provide a method and structure for monitoring in advance a situation in which a panel bunting phenomenon may occur, thereby providing a display device and a controller capable of preventing a panel bunting phenomenon There is an effect to provide.

In addition, according to the embodiments, there is an effect that a cable opening can be detected when a cable between a control board and a source board is not connected in a display device in which a control board and a source board are separately developed.

According to the embodiments of the present invention, a display device in which a control board and a source board are separately developed has an effect that system shutdown does not occur when a plurality of cables are not connected between the control board and the source board. Accordingly, it is possible to prevent cost and quality loss caused by a service engineer visiting the external system and resetting the external system.

1 is a schematic system configuration diagram of a display apparatus according to the present embodiments.
2 is a block diagram of a controller of a display device according to the present embodiments.
3 is a block diagram showing the configuration of the display device 100 according to the present embodiment in which the first lock signal is separately provided between the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # FIG. 4 is a diagram exemplarily showing a transmission method. FIG.
4 is a block diagram showing a configuration of a display device 100 according to the present embodiment in which a cascade-based first lock signal (SDIC # 0) between a source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # FIG. 4 is a diagram exemplarily showing a transmission method. FIG.
5 is a system configuration diagram of a display device when the panel bust prevention process is performed using only the first lock signal.
6 is a system configuration diagram of a display apparatus according to another embodiment.
FIG. 7 shows the states of various signals in the display device of FIG.
8 is a system configuration diagram of a display apparatus according to still another embodiment.
Figs. 9 to 11 show states of various signals in the display device of Fig.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display apparatus according to the present embodiments.

1, the display device 100 according to the present embodiment includes a display panel 110 having a plurality of data lines and a plurality of gate lines, a data driver 120 driving a plurality of data lines, A gate driving unit 130 for driving a plurality of gate lines, a controller 140 for controlling the data driving unit 120 and the gate driving unit 130, and the like.

In the display panel 110, a plurality of sub pixels (SP: Sub Pixel) are arranged, each sub pixel being arranged at a point where one data line intersects with one or more gate lines.

The controller 140 starts scanning according to the timing implemented in each frame, switches the image data input from the interface according to the data signal format used by the data driver 120, and outputs the converted image data Data And controls the data driving at a suitable time according to the scan.

The controller 140 outputs various control signals such as a data control signal (DCS) and a gate control signal (GCS) in order to control the data driver 120 and the gate driver 130 can do.

The gate driver 130 sequentially drives the plurality of gate lines by sequentially supplying the scan signals of the On voltage or the Off voltage to the plurality of gate lines under the control of the controller 140.

The data driver 120 stores the input image data Data in a memory (not shown) under the control of the controller 140 and, when a specific gate line is opened, converts the image data Data into analog data To a voltage (Vdata), and supplies the data to a plurality of data lines, thereby driving a plurality of data lines.

The data driver 120 includes a plurality of source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7), also referred to as a data driver IC SDIC # 0, SDIC # 1,..., SDIC # 7) may be formed by a tape automated bonding (TAB) method or a chip on glass (COG) May be connected to the bonding pad of the display panel 110 or may be directly disposed on the display panel 110 and may be integrated and disposed on the display panel 110 as occasion demands. In FIG. 1, the number of source driver integrated circuits is eight. However, this is only an example for convenience of explanation, and the number of source driver integrated circuits may be one or two or more.

The gate driver 130 may be located on one side of the display panel 110 as shown in FIG. 1 or on both sides of the display panel 110 divided into two, depending on the driving method.

Also, the gate driver 130 may include a plurality of gate driver ICs (GDIC # 0, GDIC # 1, ..., GDIC # 4) The circuits GDIC # 1 to GDIC # 4 are connected to bonding pads of the display panel 110 by tape automated bonding (TAB) or chip on glass (COG) Or may be implemented in a GIP (Gate In Panel) type and directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110, as the case may be. In FIG. 1, the number of gate driver integrated circuits is eight. However, the number of gate driver integrated circuits may be variously designed, and the number of gate driver integrated circuits may be as many as the number of gate lines.

One end and the other end of each of the plurality of source driver integrated circuits SDIC # 0, SDIC # 1, ..., and SDIC # 7 may be connected to the display panel 110 and one or more source boards 150 . The controller 140 may be disposed on the control board 160.

The control board 160 and one or more source boards 150 may be connected to each other through a flexible printed circuit (FPC), a flexible flat cable (FFC) 170, or the like. Hereinafter, the control board 160 and the source board 150 are connected to each other through a cable such as a flexible flat cable (FFC) 170, but the present invention is not limited thereto.

1, SDIC # 0, SDIC # 1, SDIC # 2, and SDIC # 3 are connected together to a first source board 170a SDIC # 4, SDIC # 5, SDIC # 6, and SDIC # 7 are included in the second group because they are connected to the second source board 170b together. There may be one source board and the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) may be included in one source board.

The display device 100 shown in FIG. 1 may include, for example, a liquid crystal display device (LCD), a plasma display device, an organic light emitting display device (OLED) ) Or the like.

In each of the subpixels arranged in the display panel 110, circuit elements such as transistors and capacitors are arranged. For example, when the display panel 110 is an organic light emitting display panel, circuit elements such as organic light emitting diodes, two or more transistors, and one or more capacitors are disposed in each pixel. Hereinafter, when the display panel 110 is an organic light emitting display panel, a subpixel structure will be exemplarily described.

Here, the external system 190 functions to control the function of the product to which the display apparatus 100 is applied. For example, when the product is a computer, the external system 190 may be a main board that controls functions of the computer. If the product is a television, the external system 190 may include a main board . Also, when the product is a smart phone, the external system 190 may be a main board for controlling functions of the smart phone. The external system 190 and the control board 160 may be connected to each other via a connector.

If the connection failure of the flexible flat cable 170, the failure or malfunction of the source driver integrated circuit, or the like occurs, the data voltage may not be supplied to the subpixel.

As described above, due to various factors such as the data voltage undesirable output of the source driver integrated circuit (SDIC) or the malfunction of the flexible flat cable, the data voltage is not supplied to the subpixel, A current leaking phenomenon occurs in the display panel 110 and heat may be generated in a portion where the current leaning phenomenon occurs on the display panel 110. [

The heat generated on the display panel 110 may cause other structural changes such as a polarizing plate, and in a severe case, a burnt phenomenon of the display panel 110 may occur.

Accordingly, the embodiments disclose various methods and structures for preventing a panel-bunching phenomenon that may occur when a data voltage in a source driver integrated circuit (SDIC) is low.

The controller 140 included in the display device 100 according to the present embodiment transmits data to the data driver 120. The panel driver 140 includes a data driver 120,

The controller 140 and the data driver 120 are connected by data communication interfaces IF1 and IF2. The controller 140 transmits various control signals such as a data control signal (DCS) and a gate control signal (GCS) through the first interface unit IF1 of the controller 140 to the video data Data . The data driver 120 receives image data Data in addition to various control signals transmitted from the controller 140 through the second interface unit IF2.

The controller 140 and the data driver 120 are connected to the data driver 120 based on two or more interfaces such as an embedded clock point to point interface (EPI) interface standard, a low voltage differential signal (LVDS) interface standard, and a V- Signals and data.

In this case, when an EPI (Embedded Clock Point to Point Interface) interface standard is used, a clock signal can be transmitted in a signal representing data. That is, the signal may include data and a clock. In this case, no clock signal wiring is required. If a low voltage differential signal (LVDS) interface standard is used, clock signal wiring may be separately required.

The V-by-One HS interface specification is one of the interfaces for transmitting electrical signals, developed by THine Electronics. V-by-One HS can add 3.75Gbps high-speed transmission per pair by adding technologies such as clock data recovery.

Hereinafter, the controller 140 and the data driver 120 will be referred to as a first interface of an embedded clock point to point interface (EPI) interface standard and a second interface of a V-by-one HS interface standard But it is not limited to this.

The data driver 120 transmits a first lock signal indicating the data reception state of the first interface and a second lock signal indicating the data reception state of the second interface to the controller 140, It is possible to execute the panel bust prevention process based on the first lock signal and the second lock signal received from the driving unit 120 or not to execute the panel bust prevention process.

Here, the data reception state refers to whether or not a signal including data and a clock is received, or whether the data is normally acquired using a clock even if a signal is received. A state indicating whether data that can be output to the data lines is prepared and a state indicating whether a normal data voltage or an abnormal data voltage is output even if the data voltage is output. Such a data reception state includes a normal state in which a signal is normally received, data can be normally acquired, and a normal data voltage can be output through a digital-analog conversion procedure, and an abnormal state in which the data can not be output.

First, a controller 140 that performs various control functions for preventing panel bunting will be described with reference to FIG.

2 is a block diagram of a controller of a display device according to the present embodiments.

2, the controller 140 transmits a signal including data and a clock to the data driver 120, and then outputs a first lock signal indicating a data reception state and a second lock signal indicating a data reception state from the data driver 120. [ And monitors whether there is a source driver integrated circuit that can not output the data voltage or outputs an abnormal data voltage in the data driver 120 based on the received first and second lock signals, Monitoring Result).

The controller 140 outputs the monitoring result and stores it in the memory 148. [

The controller 140 outputs a power shutdown control signal to the power management unit 180 based on the monitoring result.

According to the above description, in order to prevent the occurrence of the panel bunting phenomenon in advance, it is preferable that at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # Or the like.

The controller 140 includes a transmitting unit 142, a receiving unit 144, and a panel-bust preventing unit 146.

The transmission unit 142 transmits a signal including data and a clock to each of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7).

The receiving unit 144 receives from the at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) receiving the signal including the data and the clock, Signal and a second lock signal.

The panel-bust preventing unit 146 is configured to prevent the panel-bust preventing unit 146 from determining the first and second lock signals based on the first lock signal and the second lock signal received from at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # Quot; panel bang prevention process "

The panel bang preventing section 146 may perform the panel bang prevention process based on the first lock signal and the second lock signal received from the data driving section 120 as described later or may not execute the panel bang prevention process have.

The controller 140 monitors the data reception state of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) It is possible to prevent the panel-bunching phenomenon according to the data reception state.

The panel bang preventing section 146 described above is configured to prevent the panel bang preventing section 146 based on the first lock signal and the second lock signal received from one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # , The source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7), or the source driver ICs SDIC # 7, SDIC # 1, ..., SDIC # 7 based on the first and second lock signals received from the source driver ICs # , And store the monitoring result in the memory 148. The monitoring result may be stored in the memory 148. [

The panel-bust prevention unit 146 may execute the panel-bust prevention process by outputting the power-off control signal to the power management unit 180, for example.

The panel-bust prevention unit 146 refers to the monitoring result stored in the memory 148 in determining whether to execute the power-down process corresponding to the panel-bust prevention process, and determines whether or not to substantially execute the power-off process.

As described above, if it is determined that there is a possibility that the panel bunting phenomenon may occur based on the first lock signal and the second lock signal, the power shutoff control signal is outputted to the power management unit 180 to prevent the panel bunting phenomenon .

The controller 140 must receive the first lock signal from at least one of the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # 7) .

3 is a block diagram showing the configuration of the display device 100 according to the present embodiment in which the first lock signal is separately provided between the source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # FIG. 4 is a diagram exemplarily showing a transmission method. FIG.

3, the source driver ICs SDIC # 0, SDIC # 1, ..., SDIC # 7 are connected to the individual lock signal interconnects ILSL # 0, ILSL # LS # 1, ..., LS # 7) representing the data reception state thereof to the controller 140 via the first and second buses 7 to 7, respectively.

The controller 140 receives the first lock signals LS # 0, LS # 1, ..., LS # 7 received from the source driver integrated circuits SDIC # 0, SDIC # , The panel bang prevention process can be executed by having the state voltage level corresponding to the abnormal state.

4 is a block diagram showing a configuration of a display device 100 according to the present embodiment in which a cascade-based first lock signal (SDIC # 0) between a source driver ICs (SDIC # 0, SDIC # 1, ..., SDIC # FIG. 4 is a diagram exemplarily showing a transmission method. FIG.

In the following description, the source driver integrated circuits SDIC # 0, SDIC # 1, ..., SDIC # 7 are connected to the first group (or the left group) and the second group SDIC # 1, SDIC # 2 and SDIC # 3 (representative SDIC) are included in the first group, and SDIC # 4, SDIC # 5, SDIC # 6 and SDIC # (SDIC) are included in the second group.

4, at least one representative source driver integrated circuit (SDIC # 3, SDIC # 7) of the source driver integrated circuits (SDIC # 0, SDIC # 1, Only the representative source driver integrated circuits SDIC # 3 and SDIC # 7 transmit the first lock signal to the controller 140.

Between the representative source driver integrated circuit (SDIC # 3, SDIC # 7) and the controller 140 of at least one of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # (Representative Lock Signal Line (RLSL) # 3, RLSL # 7) are connected to each other one by one.

Only the SDIC # 3 and the SDIC # 7 corresponding to the representative source driver integrated circuits of the first group and the second group transmit the first lock signals LS # G1 and LS # G2 to the controller 140. That is, in the first group, the SDIC # 3 corresponding to the representative source driver integrated circuit of the first group transfers the first lock signal LS # G1 to the controller 140. [ In the second group, the SDIC # 7 corresponding to the representative source driver IC of the second group transfers the first lock signal LS # G2 to the controller 140.

The transmitted first lock signal is a signal indicating whether the data reception state of all of the source driver integrated circuits (SDIC # 0, SDIC # 1, ..., SDIC # 7) is normal or at least one of the source driver integrated circuits Is a state voltage level indicating whether the data reception state is abnormal or not.

The controller 140 sets the state voltage level corresponding to the abnormal state in the first lock signals LS # G1 and LS # G2 received from the representative source driver integrated circuits SDIC # 3 and SDIC # The panel bang prevention process can be executed.

As described with reference to FIGS. 3 and 4, the display apparatus 100 can perform the panel bunching prevention process based only on the first lock signal indicating the data reception state. In this case, burst detection may occur due to external influences other than the display panel 110 such as a cable open or an EPI data signal. However, in general, cable open is a major cause of the manufacturing process, and there is little or no possibility of a cable open phenomenon occurring in customers and end users.

5 is a system configuration diagram of a display device when the panel bust prevention process is performed using only the first lock signal.

5, the display apparatus 100 includes a first interface unit IF1 connected to the controller 140, a second interface unit IF1 connected to the data driver 120 and transmitting and receiving signals to and from the first interface unit IF1, And may further include a second interface unit IF2. The controller 140 and the first interface unit IF1 may be disposed on the control board 160. [ The data driver 120 and the second interface unit IF2 may be disposed on the source board 150. [

The first interface unit IF1 and the second interface unit IF2 can transmit and receive various signals and data through the EPI interface. The first interface unit IF1 and the second interface unit IF2 can transmit various signals and data based on two or more interfaces such as an EPI interface standard, an LVDS interface standard, and a V-by-one HS interface standard. When the first interface is the EPI interface, the two first lock signals LS # G1 and LS # G2 in FIG. 4 are denoted by EPI LOCK_L and EPI LOCK_L, which are the first lock signals for the EPI interface in FIG. The controller 140 has the state voltage level corresponding to the abnormal state in the first lock signals EPI LOCK_L and EPI LOCK_L received from the representative source driver ICs SDIC # 3 and SDIC # 7 The panel bang prevention process can be executed.

As shown in FIG. 5, the controller 140 and the first interface unit IF1 can transmit and receive various signals and data through the Vx1 interface and the B-LVDS interface, but are not limited thereto. Also, the data driver 120 and the second interface unit IF2 can transmit and receive various signals and data through the EPI interface and the B-LVDS interface, but are not limited thereto. The external system 190 and the controller 140 may transmit and receive various signals and data through the Vx1 interface, but are not limited thereto.

The display device 100 in which the control board 160 and the source board 150 are separately developed can be installed by moving the control board 160 and the source board 150 by the end user when the product is installed and moved.

Particularly, when the display apparatus 100 performs the panel bunting prevention process only on the basis of the first lock signal (EPI LOCK_L, EPI LOCK_L) indicating the data reception state, the external system 190 can prevent the cable 170 from being damaged more than three times. A shutdown of the system occurs and a service engineer visits the external system 190 to reset the external system 190. This may result in cost and quality loss of the customer.

In this case, if the cable 170 is pulled out or fastened while power is applied to the display device 100, the display device 100 may be seriously damaged, and fire and safety may be externally affected.

In the present embodiment, when only the panel burst prevention process is performed based only on the first lock signal (EPI LOCK_L, EPI LOCK_L) used for proceeding the panel bunting prevention process, the control board 160 The display device 100 in which the source board 150 is separately developed can not distinguish between true burst detection and bunt detection by cable open.

In the present embodiment, the display device 100 in which the control board 160 and the source board 150 are separately developed together with the first lock signals EPI LOCK_L and EPI LOCK_L used for proceeding the panel bunting prevention process And may or may not perform the panel bust prevention process based on the second lock signal for detecting the cable open.

Hereinafter, a process of performing the panel bunching prevention process based on the first lock signal and the second lock signal will be described in detail. 6 and 7, the process of the panel apparatus performing the panel bust prevention process based on the status voltage level of the first lock signal and the second lock signal will be described in detail.

6 is a system configuration diagram of a display apparatus according to another embodiment. FIG. 7 shows the states of various signals in the display device of FIG.

6, a display device 200 according to another embodiment includes a first interface unit IF1 connected to a controller 240, a first interface unit IF1 connected to the data driver 220, And a second interface unit IF2 for transmitting and receiving signals.

The controller 240 and the first interface unit IF1 may be disposed on the control board 260. [ The data driver 220 and the second interface unit IF2 may be disposed on the source board 250. [ In the display device 200 according to another embodiment, the control board 260 and the source board 250 are separately developed so that the cable 270 can be fastened and unfastened.

As described above, the first interface may be an EPI interface and the second interface may be a Vby1 HS interface. Hereinafter, it is described that the first lock signal indicating the data reception state of the first interface is the EPI lock signal (EPI Lock) and the second lock signal indicating the data reception state of the second interface is the Vby1 lock signal (Vby1 Lock) But is not limited thereto.

The control board 260 further includes a logic circuit or logic block 162 for receiving and processing the first lock signal EPI Lock and the second lock signal Vby1 Lock received by the first interface unit IF1 can do. The logic circuit or logic block 262 may be included in the controller 240 or included in the first interface unit IF1 and may be provided between the controller 240 and the first interface unit IF1, And may be disposed on the control portion 260. The logic circuit or logic block 262 may be implemented in hardware or in software.

Hereinafter, it is assumed that the logic circuit or logic block 262 is included in the controller 240 so that the controller 240 receives and processes the first lock signal EPI Lock and the second lock signal Vby1 Lock.

The controller 240 receives the first lock signal EPI Lock, which is the state voltage level at which the data reception state of the first interface corresponds to the normal state and the abnormal state. For example, in the first lock signal EPI Lock, the state of the data reception state of the first interface may be H (High), the state voltage level corresponding to the abnormal state may be L (Low) It may be the opposite.

The controller 240 receives the second lock signal Vby1 Lock, which is the state voltage level at which the data reception state of the second interface corresponds to the normal state. For example, in the second lock signal Vby1Lock, the state of the data reception state of the second interface may be H (High), the state voltage level corresponding to the abnormal state may be L (Low) It may be the opposite.

Referring to FIG. 7 and Table 1, when the controller 240 receives the first lock signal EPI Lock of the state voltage level H corresponding to the steady state, Is not detected, and the panel bust prevention process is not executed.

On the other hand, when the controller 240 receives the first lock signal EPI Lock of the state voltage level L at which the first lock signal EPI Lock corresponds to the abnormal state, the controller 240 determines, based on the second lock signal Vby1 Lock The real bunt detection and cable opening are distinguished, and the panel bunt prevention process is executed only in the case of true bunt detection.

For example, the controller 240 receives the first lock signal EPI Lock, which is the status voltage level L of which the data reception state of the first interface corresponds to an abnormal state, and the data reception state of the second interface is normal When receiving the second lock signal Vby1 Lock which is the state voltage level H corresponding to the state, the cable open state is defined and the panel bust prevention process is not executed.

On the other hand, the controller 240 receives the first lock signal EPI Lock which is the state voltage level L at which the data reception state of the first interface corresponds to the abnormal state, and the data reception state of the second interface is in the abnormal state And when the second lock signal Vby1 Lock, which is the corresponding state voltage level L, is received, it is defined as true burst detection and the panel bust prevention process is executed.

The display device according to another embodiment of the present invention is a display device in which the control board 260 and the source board 250 are separately developed. The cable opening can be detected only by the type of the lock signal EPI Lock and the second lock signal Vby1 Lock.

 Hereinafter, the process of performing the panel bunching prevention process based on the period of the second lock signal (EPI Lock), which is the state voltage level corresponding to the steady state, will be described in detail with reference to FIGS. 8 to 11 .

8 is a system configuration diagram of a display apparatus according to still another embodiment. Figs. 9 to 11 show states of various signals in the display device of Fig.

8, a display device 300 according to another embodiment of the present invention includes a first interface unit IF1 connected to a controller 340, a second interface unit IF1 connected to the data driver 320, And a second interface unit IF2 for transmitting and receiving signals.

The controller 340 and the first interface unit IF1 may be disposed on the control board 360. [ The data driver 320 and the second interface unit IF2 may be disposed in the source board 350. [ In the display device 300 according to yet another embodiment, the control board 360 and the source board 350 are separately developed so that the cable 370 can be fastened and unfastened.

The control board 360 further includes a logic circuit or a logic block 362 for receiving and processing the first lock signal EPI Lock and the second lock signal Vby1 Lock received by the first interface unit IF1 can do. The logic circuit or logic block 362 may be included in the controller 340 or included in the first interface unit IF1 and may be provided between the controller 340 and the first interface unit IF1, And may be disposed on the control portion 360. The logic circuit or logic block 362 may be implemented in hardware or in software.

The logic circuit or logic block 362 is included in the first interface unit IF1 so that the first interface unit IF1 receives the first lock signal EPI Lock and the second lock signal Vby1 Lock, .

The first interface unit IF1 outputs the output signal EPI Lock to the external system 390 through the controller 340 and directly outputs the output signal AMout to the external system 390 without passing through the controller 340 Output.

The first interface unit IF1 executes the panel bunting prevention process according to the period of the second lock signal EPI Lock which is the state voltage level corresponding to the abnormal state or the output signal AM Out which does not execute the panel bunching prevention process, To the controller 340 or the external system 390. The output signal AM Out is output to the external system 390 as shown in FIG. 8 but is output to the controller 340 and the controller 340 outputs the output signal AM Out to the external system 390. [ (390).

As shown in FIG. 9, the first interface unit IF1 is configured to receive a first lock signal (H) having a state voltage level H corresponding to an abnormal state in which the data reception state of the first interface is in an abnormal state, EPI Lock) and receives a second lock signal (Vby1 Lock), which is a state voltage level (L) corresponding to a normal data reception state of the second interface, And outputs the output signal AM Out of the output signal H.

For example, in the first lock signal (EPI Lock), the state of the data reception state of the first interface may be L (low) and the state voltage level corresponding to the abnormal state may be H (high) It may be the opposite. In the second lock signal Vby1Lock, the state of the data reception state of the second interface may be L (low) and the state voltage level corresponding to the abnormal state may be H (high) or vice versa have.

As shown in FIG. 10, the first interface unit IF1 receives a first lock signal (H) which is a state voltage level H corresponding to an abnormal state in which the data reception state of the first interface is in a state in which power is applied, EPI Lock). In this state, the first interface unit IF1 is turned on so that the period T of the second lock signal Vby1, which is the state voltage level L corresponding to the abnormal state, is equal to or less than the threshold value Tth It is possible to output to the external system 390 an output signal AM Out for executing the panel bunting prevention process in a long period.

The threshold value Tth may be several hundred milliseconds, for example, 500 milliseconds, but is not limited thereto. When the period T of the second lock signal Vby1 which is the state voltage level L corresponding to the abnormal state is equal to or more than 500 msec or longer than 500 msec, the first interface unit IF1 executes the panel- It is possible to output to the external system 390 an output signal AM Out indicating an abnormal state, that is, a bunt detection. The output signal AM Out indicating the burst detection means a signal whose output period is equal to or longer than the threshold value Tth.

10, the first interface unit IF1 receives a first lock signal having a state voltage level H corresponding to an abnormal state when the data reception state of the first interface is in a state in which power is applied, (EPI Lock). In this state, when the period T of the second lock signal Vby1, which is the state voltage level L corresponding to the abnormal state, is shorter than the threshold value Tth, the first interface unit IF1 performs the panel- It is possible to output to the external system 390 an output signal AM Out indicating that the cable not to be operated is opened. The output signal AM Out, which means that the cable is open, is a signal shorter than the threshold value Tth.

The above-described embodiments are applicable to a first method in which the display apparatus 100 executes the panel bunching prevention process based on the first lock signal and a second method in which the display apparatus 200 and 330 perform the panel bunching prevention process based on the first lock signal and the second lock signal, Although the second scheme for executing the bunting prevention process has been described, the first scheme and the second scheme can be selectively applied. For example, the display device may operate in the first mode or in the second mode depending on the changeable setting value.

The display device 300 according to another embodiment of the present invention is a display device in which a control board 360 and a source board 350 are developed separately from each other and a cable 370 between the control board 360 and the source board 350 The cable opening can be detected only during the period of the second lock signal (Vby1 Lock) at the time of engagement.

As described above, according to the embodiments of the present invention, it is possible to provide a method and structure for monitoring in advance a situation in which a panel bunting phenomenon may occur, thereby providing a display device and a controller capable of preventing a panel bunting phenomenon There is an effect to provide.

In addition, according to the embodiments, there is an effect that a cable opening can be detected when a cable between a control board and a source board is not connected in a display device in which a control board and a source board are separately developed.

According to the embodiments of the present invention, a display device in which a control board and a source board are separately developed has an effect that system shutdown does not occur when a plurality of cables are not connected between the control board and the source board. Accordingly, it is possible to prevent cost and quality loss caused by a service engineer visiting the external system and resetting the external system.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Display panel
120: Data driver
130: Gate driver
140: controller

Claims (12)

A display panel in which a plurality of data lines and a plurality of gate lines are arranged and in which a plurality of subpixels are arranged;
A controller for transmitting data;
A data driver for converting the data into a data voltage and outputting the data voltage to a data line; And
And a cable connecting the controller and the data driver,
The data driver transmits a first lock signal indicating a data reception state of the first interface and a second lock signal indicating a data reception state of the second interface to the controller,
Wherein the controller executes a panel bunching prevention process based on the first lock signal and the second lock signal received from the data driver and does not execute the panel bunching prevention process. The method according to claim 1,
Wherein the data driver comprises at least two source driver integrated circuits,
Wherein each of the source driver integrated circuits individually transmits the first lock signal to the controller. 3. The method of claim 2,
The controller comprising:
And performs the panel bunch prevention process so as to have a state voltage level corresponding to an abnormal state among first lock signals received from the source driver integrated circuits. The method according to claim 1,
Wherein the data driver comprises at least two source driver integrated circuits,
Wherein one or more representative source driver integrated circuits of the source driver integrated circuits are coupled to the controller,
Only the representative source driver integrated circuit transmits the first lock signal to the controller. 5. The method of claim 4,
Wherein the first lock signal transmitted through the representative lock signal wiring comprises:
Wherein the source driver integrated circuits are at a state voltage level indicating whether the data reception state of all of the source driver integrated circuits is normal or at least one of the source driver integrated circuits is abnormal. The method according to claim 1,
Wherein the first interface is an EPI interface and the second interface is a Vby1 HS interface. The method according to claim 1,
Wherein the controller is configured to receive the first lock signal having a state voltage level corresponding to an abnormal state of the data reception state of the first interface and to receive the first lock signal when the data reception state of the second interface is a state voltage level And the panel-bust prevention process is not executed when a two-lock signal is received. The method according to claim 1,
A first interface unit connected to the controller and a second interface unit connected to the data driver and transmitting and receiving signals to and from the first interface unit,
Wherein the first interface unit executes the panel bust prevention process according to a period of the second lock signal that is a state voltage level corresponding to an abnormal state or outputs an output signal that does not execute the panel bust prevention process to the controller or the external system / RTI > 9. The method of claim 8,
Wherein the first interface unit outputs the output signal for executing the panel bust prevention process to the controller or the external system when the duration of the second lock signal which is a state voltage level corresponding to an abnormal state is equal to or longer than a threshold value Display device. 9. The method of claim 8,
Wherein the first interface unit is configured to output the output signal to the controller or the external system that does not execute the panel bust prevention process when the period of the second lock signal, which is the state voltage level corresponding to the abnormal state, Device. The method according to claim 1,
The controller comprising:
And outputs the power-off control signal of the display device to the power management unit, thereby executing the panel-bust prevention process. A transmitter for transmitting data to a data driver;
A receiving unit receiving a first lock signal indicating a data reception state of the first interface received from the data driver and a second lock signal indicating a data reception state of the second interface; And
And a panel-bust prevention unit that performs a panel-bust prevention process based on the first lock signal and the second lock signal received from the data driver and does not execute the panel bust prevention process.

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