KR20160040783A - nitride-based semiconductor diode - Google Patents

nitride-based semiconductor diode Download PDF

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KR20160040783A
KR20160040783A KR1020140134102A KR20140134102A KR20160040783A KR 20160040783 A KR20160040783 A KR 20160040783A KR 1020140134102 A KR1020140134102 A KR 1020140134102A KR 20140134102 A KR20140134102 A KR 20140134102A KR 20160040783 A KR20160040783 A KR 20160040783A
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layer
semiconductor
electrode layer
nitride
semiconductor layer
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KR1020140134102A
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Korean (ko)
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모토노부 타케야
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서울반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Abstract

The nitride-based semiconductor diode according to an embodiment includes a semiconductor structure including a first nitride-based semiconductor layer doped with a first type and a second nitride-based semiconductor layer doped with a second type, which are stacked alternately to each other; A first electrode layer in contact with a side surface of the first semiconductor layer and forming a Schottky junction with the first semiconductor layer and a second electrode layer electrically connected to the other side surface of the semiconductor structure opposite to the one side surface.

Figure P1020140134102

Description

A nitride-based semiconductor diode

This disclosure relates to a nitride based semiconductor diode.

BACKGROUND ART Due to the development of information and communication technology, there is an increasing demand for devices operating in a high-speed switching environment or a high-voltage environment. In particular, a power semiconductor device must withstand a high voltage in the reverse direction as a switching device and must flow a high current in the forward operation. Conventionally, silicon semiconductor devices have been widely used in the market as such power semiconductor devices. However, since the 2000s, since the material limitations of silicon have been encountered since the 2000s, there has been no significant improvement in the technology of achieving reduction in power loss or increasing cell density .

On the other hand, in order to overcome the material limitations, there has been an attempt to introduce gallium nitride (GaN) instead of silicon into a power semiconductor device. Specifically, a gallium nitride semiconductor device employing a III-V semiconductor material is capable of high-speed switching operation as compared with a conventional silicon semiconductor device, and is suitable for high-speed signal processing as well as being applied to a high voltage environment through high- It has attracted the attention of the industry because of its advantages.

Semiconductor devices such as Schottky barrier diodes, pn junction diodes, and MIS (Metal-Insulator-Semiconductor) transistors using GaN substrates have been proposed as examples of gallium nitride devices. In Korean Patent Publication No. 2010-007822, A Schottky barrier diode having improved withstand voltage is disclosed.

The embodiment of the present disclosure provides a nitride-based semiconductor diode having improved high-voltage characteristics when a reverse bias is applied between a first electrode layer and a second electrode layer.

An embodiment of the present disclosure provides a nitride based semiconductor diode with improved charge mobility when forward bias is applied.

A nitride based semiconductor diode according to one aspect is disclosed. Wherein the nitride semiconductor diode comprises a semiconductor structure including a first nitride semiconductor first layer doped with a first type and a second nitride semiconductor layer doped with a second type,

A first electrode layer in contact with one side surface of the semiconductor structure and forming a Schottky junction with the first semiconductor layer and a second electrode layer electrically connected to the other side surface of the semiconductor structure opposite to the one side surface, .

A nitride-based semiconductor diode according to another aspect is disclosed. The nitride based semiconductor diode includes a substrate, an insulating buffer layer formed on the substrate, a first nitride semiconductor first semiconductor layer doped with a first type staggeredly stacked on the buffer layer, and a second nitride semiconductor layer doped with a second type A first electrode layer formed in a first trench that penetrates at least a portion of the semiconductor structure toward a substrate and a second electrode layer disposed laterally spaced from the first electrode layer, And a second electrode layer formed inside the second trench penetrating in the direction of the first electrode. The first electrode layer is Schottky-bonded to the first semiconductor layer, and the second electrode layer is ohmic-bonded to the first semiconductor layer.

According to an embodiment of the present disclosure, a nitride-based first semiconductor layer doped with a first type and a nitride-based second semiconductor layer doped with a second type, which are stacked alternately, are applied between the first electrode layer and the second electrode layer . The depletion layer can be formed in the boundary region between the first semiconductor layer and the second semiconductor layer by performing the p-n junction between the first semiconductor layer and the second semiconductor layer.

The depletion layer can alleviate the concentration of an electric field in the nitride semiconductor diode when an electric field due to reverse bias is formed from the first electrode layer to the second electrode layer through the semiconductor structure. This makes it possible to provide a nitride semiconductor diode having higher breakdown voltage characteristics.

According to an embodiment of the present disclosure, a nitride-based third semiconductor layer having a different work function from that of the first semiconductor layer is interposed in the first semiconductor layer, and a nitride semiconductor layer between the first electrode layer and the second electrode layer The 2DEG layer can be formed in the semiconductor layer. The nitride semiconductor diode having improved charge mobility can be provided by allowing charge to be conducted through the 2DEG layer at the time of forward bias application.

The effects of the disclosed techniques described above are to illustrate any of the various effects derived from the configuration of one embodiment of the present disclosure and not to preclude other various effects that may be apparently derived from the configuration of the presented embodiments.

1 is a schematic diagram schematically showing a nitride-based semiconductor diode according to one comparative example of the present disclosure.
2 is a schematic diagram schematically showing a nitride-based semiconductor diode according to the first embodiment of the present disclosure;
3 is a schematic diagram schematically showing a depletion layer in a nitride semiconductor diode according to the first embodiment of the present disclosure;
4 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a second embodiment of the present disclosure;
5 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a third embodiment of the present disclosure;
6 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a fourth embodiment of the present disclosure;
7 is a partial enlarged view of the nitride-based semiconductor diode of Fig.
8 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a fifth embodiment of the present disclosure;

Embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, the techniques disclosed in this disclosure are not limited to the embodiments described herein but may be embodied in other forms. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device.

Where an element is referred to herein as being located on another element "above" or "below", it is to be understood that the element is directly on the other element "above" or "below" It means that it can be intervened. In this specification, the terms 'upper' and 'lower' are relative concepts set at the observer's viewpoint. When the viewer's viewpoint is changed, 'upper' may mean 'lower', and 'lower' It may mean.

Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Herein, the interfacial region between the first layer and the second layer means not only the interface between the first layer and the second layer but also the interfacial region between the first layer and the second layer adjacent to the interface, And the like.

In the present specification, the doping types of the first type and the second type mean different doping types, respectively. That is, the first type or the second type may be classified depending on the type of the dopant introduced into the semiconductor material layer. Specifically, the first type or the second type may be any one of n-type and p-type. When the first type is n-type, the second type may be p-type, and when the first type is p-type, the second type may be n-type. For example, when doping to n-type, silicon (Si) may be applied as a dopant, and dopant may be beryllium (Be), magnesium (Mg), calcium (Ca) , Iron (Fe), manganese (Mn), and the like.

In this specification, the n-type or p-type doping means that the p-type dopant is doped into the nitride-based semiconductor at a concentration of 1E17 / cm 3 or more, and the n-type dopant is implanted at a dose of about 1E16 / cm 3 or more. In addition, 'is doped with a high concentration of n-type or p-type' means by being in the nitride-based semiconductor, in the case of a p-type of about 1E20 / cm 3 or more, in the case of n-type dopant is about 1E19 / cm 3 or more is injected, a high concentration Lt; / RTI >

In this specification, the nitride-based semiconductor layer may include, for example, a nitride such as Al x In y Ga 1-xy N (0? X? 1, 0? Y? The nitride based semiconductor layer may be formed by a method such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy or Hydride Vapor Phase Epitaxy Can be formed.

In this specification, the nitride-based semiconductor diode may be, for example, a Schottky barrier diode.

1 is a schematic diagram schematically showing a nitride-based semiconductor diode according to one comparative example of the present disclosure. More specifically, FIG. 1A schematically shows a depletion layer 110 'that occurs when the first semiconductor layer 110 and the first electrode layer 130 are Schottky-coupled between the metal and the semiconductor. FIG. 1B schematically shows an electric field distribution in the interface region between the first semiconductor layer 110 and the first electrode layer 130. FIG. FIG. 1 (c) schematically shows the voltage distribution inside the first semiconductor layer 110.

One comparative example related to FIG. 1 was invented by the inventor of the present disclosure, but has a disadvantage relative to the embodiment of the present disclosure described later. The inventor of the present disclosure has completed the technique of the embodiment of the present disclosure in order to overcome the disadvantages of this comparative example. Hereinafter, first, the configuration of this comparative example will be described in detail.

Referring to FIG. 1, the nitride semiconductor diode 10 includes a first nitride semiconductor layer 110 doped with a first type, a first electrode layer 130 having a Schottky junction with the first semiconductor layer 110, And an upper electrode layer 140 on the first electrode layer 130. In one embodiment, the first semiconductor layer 110 is an n-type doped GaN layer, the first electrode layer 130 may be a nickel (Ni) layer, and the upper electrode layer 140 may be a gold (Au) layer.

The nitride based semiconductor diode 10 includes a lower nitride based semiconductor layer 120 which is in contact with the first semiconductor layer 110 on the opposite side of the first electrode layer 130 and is doped with a high concentration of the first type. The second nitride semiconductor layer 120 may be disposed on the lower surface of the second nitride semiconductor layer 120. The second nitride semiconductor layer 120 may have a second electrode layer 130 formed on the lower surface thereof. In one embodiment, the lower nitride based semiconductor layer 120 is a high concentration n-type doped GaN layer and the second electrode layer 130 is formed of a Cr (Cr) layer, a Ti (titanium) layer, an Al , Or a laminated structure of two or more thereof. Although not shown, a gold (Au) layer may be further stacked on the lower surface of the second electrode layer 130.

1 (a), a depletion layer is formed in the interface region between the first electrode layer 130 and the first semiconductor layer 110 by Schottky junctions between the metal and the semiconductor, . 1 (b), the depletion layer has a first electrode layer 130 and a second electrode layer 150 when a bias is not applied between the first electrode layer 130 and the second electrode layer 150 (Vr 0 ) May be formed from the interface of the first semiconductor layer 110 to the first distance r 0 in the inner direction of the first semiconductor layer 110. When a reverse bias (Vr 1 ) is applied between the first electrode layer 130 and the second electrode layer 150, the depletion layer is less than the first distance r 0 in the inward direction of the first semiconductor layer 110 Can be formed up to a large second distance r 1 . 1 (a) shows a depletion layer 110 'formed in the first semiconductor layer 110 when a reverse bias Vr 1 is applied.

On the other hand, the electric field generated by the Schottky junction between the metal and the semiconductor may have a peak value at the interface between the first semiconductor layer 110 and the first electrode layer 130. At this time, when the bias is not applied (Vr 0 ), the peak value is relatively high when the reverse bias is applied (Vr 1 ).

Referring to FIG. 1 (c), the voltage distribution in the first semiconductor layer 110 can be confirmed by the distance from the interface between the first semiconductor layer 110 and the third electrode layer 130. The voltage may correspond to a value obtained by integrating the electric field of FIG. 1 (b) from the interface between the first semiconductor layer 110 and the third electrode layer 130 according to the distance. Specifically, when the reverse bias is applied (Vr 1 ), the voltage increases from the interface to the distance r 1 at which the internal electric field disappears.

In the internal field distribution of the nitride semiconductor diode as shown in FIG. 1, as the reverse bias value increases, the peak electric field value increases at the interface of the Schottky barrier between the first semiconductor region 110 and the first electrode layer 130 . When the peak electric field value reaches a threshold electric field value equal to or greater than a predetermined value, an electric breakdown phenomenon of the nitride semiconductor diode can occur from the interface.

2 is a schematic diagram schematically showing a nitride-based semiconductor diode according to the first embodiment of the present disclosure; 2 (a) schematically shows a structure in which the first and second semiconductor layers 112 and 114 and the first electrode layer 130 are Schottky junctions between the metal and the semiconductor. 2 (b) schematically shows the electric field distribution in the interface region between the first semiconductor layer 112 and the first electrode layer 130. As shown in FIG. FIG. 2 (c) schematically shows the voltage distribution inside the first semiconductor layer 112. 3 is a schematic diagram schematically showing a depletion layer in a nitride semiconductor diode according to the first embodiment of the present disclosure; The nitride based semiconductor diode shown in FIGS. 2 and 3 may be a Schottky barrier diode forming a Schottky junction between the first semiconductor layer 112 and the first electrode layer 130.

2 and 3, the nitride semiconductor diode 20 includes a first nitride semiconductor first semiconductor layer 112 doped with a first type and a second nitride semiconductor layer doped with a second type 114). ≪ / RTI > In one embodiment, the first semiconductor layer 112 may be doped with n-type and the second semiconductor layer 114 may be doped with p-type. The nitride based semiconductor diode 20 includes a first electrode layer 130 and a lower nitride based semiconductor layer 120 on both side portions of the semiconductor structure.

The nitride based semiconductor diode 20 may include a first electrode layer 130 which is in Schottky contact with the first semiconductor layer 112 and an upper electrode layer 140 on the first electrode layer 130. In one embodiment, the first semiconductor layer 110 is an n-type doped GaN layer, the first electrode layer 130 may be a nickel (Ni) layer, and the upper electrode layer 140 may be a gold (Au) layer. The nitride semiconductor diode 20 includes a lower nitride based semiconductor layer 120 which is in contact with the first semiconductor layer 112 on the opposite side of the first electrode layer 130 and is doped with a high concentration of the first type. The second nitride semiconductor layer 120 may be disposed on the lower surface of the second nitride semiconductor layer 120. The second nitride semiconductor layer 120 may have a second electrode layer 130 formed on the lower surface thereof. In one embodiment, the lower nitride based semiconductor layer 120 is a high concentration n-type doped GaN layer and the second electrode layer 130 is formed of a Cr (Cr) layer, a Ti (titanium) layer, an Al , Or a laminated structure of two or more thereof. Although not shown, a gold (Au) layer may be further stacked on the lower surface of the second electrode layer 130.

Referring to FIG. 2 (a), the first semiconductor layer 112 and the second semiconductor layer 114 can generate a depletion layer by p-n junction. Depletion layers 112 'and 114' may be formed in the first semiconductor layer 112 and the second semiconductor layer 114, respectively, as shown in FIG. In one embodiment, depletion layers 112 'and 114' may be formed in the entire region of the first semiconductor layer 112 and the second semiconductor layer 114. When the depletion layer 112 '114' is formed over the entire area of the first semiconductor layer 112 and the second semiconductor layer 114 as described above, the electric field distribution can be obtained in a graph shown in FIG. 2 (b) Can appear together.

An electric field generated by the Schottky junction between the first semiconductor layer 112 and the first electrode layer 130 is formed between the first semiconductor layer 112 and the first electrode layer 130, Based semiconductor layer 120 to the interface between the first semiconductor layer 112 and the lower nitride-based semiconductor layer 120 from the interface between the first semiconductor layer 112 and the lower nitride- The first electrode layer 130 and the lower nitride-based semiconductor layer 130 are formed between the first electrode layer 130 and the second electrode layer 150 irrespective of the case where the bias is not applied (Vr 0 ) and the case where the reverse bias is applied (Vr 1 ) An electric field of a uniform value can be maintained between the layers 120, respectively. Referring to FIG. 2 (c), from the interface between the first electrode layer 130 and the first semiconductor layer 112, a lower nitride (Vr 0 ) and a lower nitride (Vr 1 ) The voltage increases linearly up to the distance of r 1 ', which is the interface between the semiconductor layer 120 and the first semiconductor layer 112.

In the internal electric field distribution of the nitride semiconductor diode as shown in FIG. 2, the electric field value increases as the reverse bias value increases. However, the electric field value does not have an extreme peak value in the nitride based semiconductor region. Thus, even when the reverse bias value increases, the resistance against the electric breakdown phenomenon can be larger than that of the nitride based semiconductor diode 10 of the comparative example shown in FIG. Accordingly, it is possible to provide a nitride-based semiconductor diode having an improved withstand voltage characteristic.

2 and 3, an operation method of the nitride semiconductor diode 20 of the present embodiment will be described. As described above, the first semiconductor layer 112 may be an n-type doped nitride based semiconductor layer, and the first electrode layer 130 may be a metal layer that forms a Schottky junction with the first semiconductor layer 112. The lower nitride based semiconductor layer 120 may form an ohmic contact with the first semiconductor layer 112 and may form a p-n junction with the second semiconductor layer 114.

When no bias is applied or a reverse bias is applied between the first electrode layer 130 and the second electrode layer 150, all of the first semiconductor layer 112 and the second semiconductor layer 114 are depleted ) State can be maintained. In FIG. 3, depletion layers 112 'and 114' are shown.

At least a portion of the first semiconductor layer 112 and the second semiconductor layer 114 can be recovered from the depleted state when a forward bias is applied between the first electrode layer 130 and the second electrode layer 150 have. At this time, a charged carrier can be conducted along a part of the first semiconductor layer 112 recovered from the depleted state. The nitride-based semiconductor diode can generate a forward current by conducting the carrier across the Schottky barrier lowered by the forward bias at the interface between the first semiconductor layer 112 and the first electrode layer 130. [

4 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a second embodiment of the present disclosure; Referring to FIG. 4, the nitride semiconductor diode 30 includes a substrate 410, an insulating buffer layer 420, a semiconductor structure 430, a first electrode layer 460, and a second electrode layer 470.

As the substrate 410, various well-known substrates such as a sapphire substrate, a GaN substrate, a silicon substrate, and a SiC substrate may be used. The insulating buffer layer 420 may be a nitride-based semiconductor layer that serves to alleviate a lattice constant difference between the substrate 410 and the nitride-based semiconductor layer located on the substrate 410.

The semiconductor structure 430 may be disposed on the insulating buffer layer 420. The semiconductor structure 430 may include a first nitride-based semiconductor layer 431 doped with a first type and a second nitride-based semiconductor layer 432 doped with a second type, which are stacked alternately. The semiconductor structure 430 may include a plurality of pairs of the first semiconductor layer and the second semiconductor layer stacked alternately. The first semiconductor layer 431 and the second semiconductor layer 432 may have a thickness of, for example, about 10 nm to 200 nm.

In one embodiment, the first semiconductor layer 431 may be doped with n-type and the second semiconductor layer 432 may be doped with p-type. The first semiconductor layer 431 and the second semiconductor layer 432 form a p-n junction so that a depletion layer can be formed on the entire first semiconductor layer 431 and the second semiconductor layer 432.

An insulating buffer layer 440 and an upper insulating layer 450 may be disposed on the semiconductor structure 430. The insulating buffer layer 440 may be a nitride based semiconductor layer, and the upper insulating layer 450 may include an oxide, a nitride, or an oxynitride.

The first electrode layer 460 may be formed in a trench that penetrates at least a portion of the semiconductor structure 430 toward the substrate 410. The first electrode layer 460 may be Schottky junctioned with the first semiconductor layer 431. As an example, the first electrode layer 460 may be a nickel (Ni) layer or a stacked structure of a nickel (Ni) layer and a gold (Au) layer. As illustrated, the first electrode layer 460 may be formed to fill the trench, but it is not limited thereto, and may be formed in the form of a thin film along the inner wall of the trench.

The second electrode layer 470 may be spaced laterally from the first electrode layer 460 and may be formed within the trench that penetrates at least a portion of the semiconductor structure 430 toward the substrate. The second electrode layer 470 may be ohmic-bonded to the first semiconductor layer 431. The second electrode layer 470 may be a chromium (Cr) layer, a titanium layer (Ti), an aluminum (Al) layer, or a laminated structure of two or more thereof. The second electrode layer 470 may further include a gold (Au) layer stacked on the metal thin film layer. As illustrated, the second electrode layer 470 may be formed to fill the trench, but it is not limited thereto, and may be formed in the form of a thin film along the inner wall of the trench.

In the nitride semiconductor diode 30, when no voltage is applied between the first electrode layer 460 and the second electrode layer 470 or when a reverse bias is applied, the first semiconductor layer 431 and the second semiconductor layer 432, All of the pn junction 432 may remain depleted by the pn junction. At least a portion of the first semiconductor layer 460 and the second semiconductor layer 470 is recovered from the depleted state when a forward bias is applied between the first electrode layer 460 and the second electrode layer 470, A charged carrier can conduct between the first electrode layer 460 and the second electrode layer 470 along a part of the recovered first semiconductor layer 431. [ The nitride semiconductor diode 30 then generates a forward current through the carrier across the Schottky barrier lowered by the forward bias at the interface between the first semiconductor layer 460 and the first electrode layer 130 .

5 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a third embodiment of the present disclosure; 5, the nitride-based semiconductor diode 40 includes an insulating buffer layer 420 formed on the surface of the insulating buffer layer 420 for an epitaxial lateral overgrowth (ELO) process, as compared with the nitride-based semiconductor diode 30 according to the second embodiment of FIG. And the nitride-based seed layer 421 is provided. That is, the insulating buffer layer 420 can be manufactured by a known ELO process using the nitride-based seed layer 421. [

In one embodiment, if the substrate 410 is a sapphire substrate and the semiconductor structure 430 comprises a doped GaN layer, a GaN pattern layer may be applied as the nitride based seed layer 421. The first nitride layer 422 may grow from the nitride based seed layer 421 and the second nitride layer 423 may grow from the first nitride layer 422. [ By applying the known ELO process, the density of the actual potential (TD) caused by the lattice constant difference between the substrate 410 and the insulating buffer layer 420 can be reduced. This makes it possible to suppress the occurrence of a leakage current generated based on the actual potential (TD) or deterioration in electric resistance that may occur at a high temperature.

6 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a fourth embodiment of the present disclosure; 7 is a partial enlarged view of the nitride-based semiconductor diode of Fig. 6 and 7, the nitride-based semiconductor diode 50 is further inserted into the first semiconductor layer 431, as compared with the nitride-based semiconductor diode 30 according to the second embodiment of FIG. Based third semiconductor layer 610 formed on the nitride-based semiconductor layer 610.

The nitride-based third semiconductor layer 610 may include a nitride having a different work function from the nitride of the first semiconductor layer 431. In one embodiment, when the first semiconductor layer 431 is a GaN layer, the nitride based third semiconductor layer 610 may include InN, AlGaN, InGaN, or AlGaInN. The nitride-based third semiconductor layer 610 may have a thickness of about 10 to 50 nm, for example.

An energy banding phenomenon due to a difference in work function between the nitride constituting the first semiconductor layer 431 and the third semiconductor layer 610 or an energy banding phenomenon due to a difference in work function between the first semiconductor layer 431 and the third semiconductor layer 610 The 2DEG layer 710 can be formed by the piezoelectric effect generated by the difference in lattice constant between the nitride layers. 7, the 2DEG layer 710 may extend laterally between the first electrode layer 460 and the second electrode layer 470 and may have a relatively higher electron density than the first semiconductor layer 431 Lt; / RTI > Thus, in a nitride based semiconductor diode 50 in which electrons are applied as carriers, electrons can conduct through the 2DEG layer 710 to a higher degree of travel.

On the other hand, the 2DEG layer 710 can be controlled to be disconnected in the interface region between the first electrode layer 460 and the semiconductor structure 630. The first electrode layer 460 and the first semiconductor layer 431 are controlled so that the force for forming the Schottky barrier due to the difference in work function affects the energy band structure of the 2DEG layer 710, The 2DEG layer 710 can be partially removed in the boundary region between the semiconductor structure 630 and the semiconductor structure 630. [

When no bias is applied between the first electrode layer 460 and the second electrode layer 470 or a reverse bias is applied, the length of the 2DEG layer 710 that can be cut off and disconnected from the 2DEG layer 710 is applied And may be related to the magnitude of the bias. When a forward bias is applied between the first electrode layer 460 and the second electrode layer 470, the disconnected 2DEG layer 710 may be recovered and the electrons may conduct through the 2DEG layer 710 to a higher travel .

8 is a schematic diagram schematically showing a nitride-based semiconductor diode according to a fifth embodiment of the present disclosure; 8, the nitride-based semiconductor diode 60 has a structure in which the insulating buffer layer 420 is formed of a nitride-based semiconductor material for an epitaxial lateral overgrowth (ELO) process, as compared with the nitride-based semiconductor diode 50 of the fourth embodiment shown in Fig. And the seed layer 421 is provided. That is, the insulating buffer layer 420 can be manufactured by a known ELO process using the nitride-based seed layer 421. [

In one embodiment, when the substrate 410 is a sapphire substrate and the semiconductor structure 630 comprises a doped GaN layer, a GaN pattern layer may be applied as the nitride based seed layer 421. The first nitride layer 422 may grow from the nitride based seed layer 421 and the second nitride layer 423 may grow from the first nitride layer 422. [ By applying the known ELO process, the density of the actual potential (TD) caused by the lattice constant difference between the substrate 410 and the insulating buffer layer 420 can be reduced. This makes it possible to suppress the occurrence of a leakage current generated based on the actual potential (TD) or deterioration in electric resistance that may occur at a high temperature.

On the other hand, the constituent points of the third and fourth embodiments of the present disclosure can be applied to the second embodiment described above with reference to Fig. That is, the ELO process configuration using the nitride-based seed layer in the third embodiment or another nitride-based semiconductor layer insertion structure for forming the 2DEG layer in the fourth embodiment can be applied substantially the same as the second embodiment have.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

10 20 30 40 50 60: nitride semiconductor diodes,
110 112: first semiconductor layer, 110'112 ': depletion layer of the first semiconductor layer,
114: second semiconductor layer, 114 ': depletion layer of the second semiconductor layer
120: lower nitride based semiconductor layer, 130: first electrode layer,
140: upper electrode layer, 150: second electrode layer,
410: substrate, 420: insulating buffer layer,
421: a nitride-based seed layer
430: semiconductor structure, 431: first semiconductor layer, 432: second semiconductor layer,
440: insulating buffer layer, 450: insulating layer,
460: a first electrode layer, 470: a second electrode layer,
610: a nitride-based third semiconductor layer, 630: a semiconductor structure,
710: 2DEG layer.

Claims (18)

A semiconductor structure including a first nitride semiconductor layer doped with a first type and a second nitride semiconductor layer doped with a second type;
A first electrode layer in contact with a side surface of the semiconductor structure and forming a Schottky junction with the first semiconductor layer; And
And a second electrode layer electrically connected to the other side portion of the semiconductor structure located on the opposite side of the one side portion
Nitride based semiconductor diode.
The method according to claim 1,
The first semiconductor layer and the second semiconductor layer form a depletion layer by pn junction
Nitride based semiconductor diode.
3. The method of claim 2,
When a bias is not applied between the first electrode layer and the second electrode layer, or when a reverse bias is applied,
Wherein all of the first semiconductor layer and the second semiconductor layer remain depleted
Nitride based semiconductor diode.
3. The method of claim 2,
When a forward bias is applied between the first electrode layer and the second electrode layer, at least a part of the first semiconductor layer and the second semiconductor layer is recovered from the depleted state
Nitride based semiconductor diode.
5. The method of claim 4,
The charge is conducted along a portion of the first semiconductor layer recovered from the depleted state
Nitride based semiconductor diode.
The method according to claim 1,
And a nitride-based third semiconductor layer interposed in the first semiconductor layer and having a work function different from that of the first semiconductor layer
Nitride based semiconductor diode.
The method according to claim 6,
Wherein the first semiconductor layer is a GaN layer,
The third semiconductor layer may be any one selected from an InN layer, an AlGaN layer, an InGaN layer, and an AlInGaN layer
Nitride based semiconductor diode.
The method according to claim 6,
And a 2DEG layer formed in an interface region between the first semiconductor layer and the third semiconductor layer
Nitride based semiconductor diode.
9. The method of claim 8,
When no voltage is applied between the first electrode layer and the second electrode layer or when a reverse bias is applied, the 2DEG layer is disconnected from the interface region of the first electrode layer and the semiconductor structure
Nitride based semiconductor diode.
10. The method of claim 9,
When a forward bias is applied between the first electrode layer and the second electrode layer,
The 2DEG layer disconnected in the interface region of the first electrode layer and the semiconductor structure is recovered and a charge is transferred between the first electrode layer and the second electrode layer
Nitride based semiconductor diode.
Board;
An insulating buffer layer formed on the substrate;
A semiconductor structure including a first nitride-based semiconductor layer doped with a first type and a second nitride-based semiconductor layer doped with a second type, the first nitride-based first semiconductor layer being staggered on the buffer layer;
A first electrode layer formed in a first trench penetrating at least a part of the semiconductor structure in a direction of a substrate; And
And a second electrode layer disposed in the second trench, the second electrode layer being spaced laterally from the first electrode layer and penetrating at least a portion of the semiconductor structure toward the substrate,
Wherein the first electrode layer is Schottky-bonded to the first semiconductor layer, and the second electrode layer is ohmic-bonded to the first semiconductor layer
Nitride based semiconductor diode.
12. The method of claim 11,
The semiconductor structure
A plurality of pairs of the first semiconductor layer and the second semiconductor layer stacked alternately,
Nitride based semiconductor diode.
12. The method of claim 11,
When no voltage is applied between the first electrode layer and the second electrode layer or when a reverse bias is applied,
All of the first semiconductor layer and the second semiconductor layer are maintained in a depleted state by the pn junction
Nitride based semiconductor diode.
14. The method of claim 13,
At least a portion of the first semiconductor layer and the second semiconductor layer is recovered from the depleted state and a charged carrier is recovered from the recovered state when a forward bias is applied between the first electrode layer and the second electrode layer Wherein the first electrode layer and the second electrode layer are electrically connected to each other.
Nitride based semiconductor diode.
12. The method of claim 11,
And a nitride-based third semiconductor layer inserted in the first semiconductor layer and having a different work function from the first semiconductor layer
Nitride based semiconductor diode.
16. The method of claim 15,
And a 2DEG layer formed in an interface region between the first semiconductor layer and the third semiconductor layer
Nitride based semiconductor diode.
17. The method of claim 16,
When no voltage is applied between the first electrode layer and the second electrode layer or when a reverse bias is applied, the 2DEG layer is disconnected from the interface region of the first electrode layer and the semiconductor structure
Nitride based semiconductor diode.
18. The method of claim 17,
When a forward bias is applied between the first electrode layer and the second electrode layer,
The 2DEG layer disconnected in the interface region with the first electrode layer is recovered and a charge is transferred between the first electrode layer and the second electrode layer
Nitride based semiconductor diode.

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