KR20150129316A - 명령 프로세싱 회로들에서의 리던던트 동기화 베리어들의 제거 및 관련 프로세서 시스템들, 방법들 및 컴퓨터-판독가능 매체 - Google Patents

명령 프로세싱 회로들에서의 리던던트 동기화 베리어들의 제거 및 관련 프로세서 시스템들, 방법들 및 컴퓨터-판독가능 매체 Download PDF

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Publication number
KR20150129316A
KR20150129316A KR1020157028544A KR20157028544A KR20150129316A KR 20150129316 A KR20150129316 A KR 20150129316A KR 1020157028544 A KR1020157028544 A KR 1020157028544A KR 20157028544 A KR20157028544 A KR 20157028544A KR 20150129316 A KR20150129316 A KR 20150129316A
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South Korea
Prior art keywords
synchronization
instruction
barrier
synchronization event
event
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Korean (ko)
Inventor
멜린다 제이. 브라운
제임스 노리스 다이펜더퍼
마이클 스코트 맥클베인
브라이언 마이클 스템펠
다렌 유진 스트리트
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
KR1020157028544A 2013-03-14 2014-03-10 명령 프로세싱 회로들에서의 리던던트 동기화 베리어들의 제거 및 관련 프로세서 시스템들, 방법들 및 컴퓨터-판독가능 매체 Withdrawn KR20150129316A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/829,315 2013-03-14
US13/829,315 US20140281429A1 (en) 2013-03-14 2013-03-14 Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media
PCT/US2014/022457 WO2014159195A1 (en) 2013-03-14 2014-03-10 Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media

Publications (1)

Publication Number Publication Date
KR20150129316A true KR20150129316A (ko) 2015-11-19

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KR1020157028544A Withdrawn KR20150129316A (ko) 2013-03-14 2014-03-10 명령 프로세싱 회로들에서의 리던던트 동기화 베리어들의 제거 및 관련 프로세서 시스템들, 방법들 및 컴퓨터-판독가능 매체

Country Status (6)

Country Link
US (1) US20140281429A1 (enExample)
EP (1) EP2972787B1 (enExample)
JP (1) JP2016515262A (enExample)
KR (1) KR20150129316A (enExample)
CN (1) CN105009074B (enExample)
WO (1) WO2014159195A1 (enExample)

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KR20180048251A (ko) * 2016-11-02 2018-05-10 삼성전자주식회사 다중-스트림 스킴에서 희생 스트림 선택 알고리즘들

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US9146741B2 (en) 2012-04-26 2015-09-29 Qualcomm Incorporated Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media
US9304940B2 (en) * 2013-03-15 2016-04-05 Intel Corporation Processors, methods, and systems to relax synchronization of accesses to shared memory
US20160224398A1 (en) * 2015-01-29 2016-08-04 Intellisis Corporation Synchronization in a Multi-Processor Computing System
US9552327B2 (en) 2015-01-29 2017-01-24 Knuedge Incorporated Memory controller for a network on a chip device
US10061531B2 (en) 2015-01-29 2018-08-28 Knuedge Incorporated Uniform system wide addressing for a computing system
US10027583B2 (en) 2016-03-22 2018-07-17 Knuedge Incorporated Chained packet sequences in a network on a chip architecture
US10346049B2 (en) 2016-04-29 2019-07-09 Friday Harbor Llc Distributed contiguous reads in a network on a chip architecture
US10437593B2 (en) * 2017-04-27 2019-10-08 Nvidia Corporation Techniques for comprehensively synchronizing execution threads
US11249766B1 (en) 2020-09-14 2022-02-15 Apple Inc. Coprocessor synchronizing instruction suppression
US11550649B2 (en) * 2021-03-17 2023-01-10 Qualcomm Incorporated System-on-chip timer failure detection and recovery using independent redundant timers
US11656796B2 (en) * 2021-03-31 2023-05-23 Advanced Micro Devices, Inc. Adaptive memory consistency in disaggregated datacenters
US12045615B1 (en) * 2022-09-16 2024-07-23 Apple Inc. Processing of synchronization barrier instructions
US12229561B1 (en) 2022-09-16 2025-02-18 Apple Inc. Processing of data synchronization barrier instructions

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JPH11259437A (ja) * 1998-03-12 1999-09-24 Hitachi Ltd 不要バリア命令の削減方式
US7100021B1 (en) * 2001-10-16 2006-08-29 Cisco Technology, Inc. Barrier synchronization mechanism for processors of a systolic array
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US7065596B2 (en) * 2002-09-19 2006-06-20 Intel Corporation Method and apparatus to resolve instruction starvation
JP3896087B2 (ja) * 2003-01-28 2007-03-22 松下電器産業株式会社 コンパイラ装置およびコンパイル方法
US7278014B2 (en) * 2004-12-02 2007-10-02 International Business Machines Corporation System and method for simulating hardware interrupts
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US8316194B2 (en) * 2009-12-15 2012-11-20 Intel Corporation Mechanisms to accelerate transactions using buffered stores
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180048251A (ko) * 2016-11-02 2018-05-10 삼성전자주식회사 다중-스트림 스킴에서 희생 스트림 선택 알고리즘들

Also Published As

Publication number Publication date
EP2972787A1 (en) 2016-01-20
CN105009074A (zh) 2015-10-28
JP2016515262A (ja) 2016-05-26
EP2972787B1 (en) 2018-11-14
WO2014159195A1 (en) 2014-10-02
US20140281429A1 (en) 2014-09-18
CN105009074B (zh) 2018-12-07

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PA0105 International application

Patent event date: 20151012

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid