JP2016515262A - 命令処理回路における冗長同期バリアの削除と、関連プロセッサシステム、方法、およびコンピュータ可読媒体 - Google Patents

命令処理回路における冗長同期バリアの削除と、関連プロセッサシステム、方法、およびコンピュータ可読媒体 Download PDF

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JP2016515262A
JP2016515262A JP2016500974A JP2016500974A JP2016515262A JP 2016515262 A JP2016515262 A JP 2016515262A JP 2016500974 A JP2016500974 A JP 2016500974A JP 2016500974 A JP2016500974 A JP 2016500974A JP 2016515262 A JP2016515262 A JP 2016515262A
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instruction
synchronization
next instruction
event
stream
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JP2016515262A5 (enExample
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メリンダ・ジェイ・ブラウン
ジェームズ・ノリス・ディーフェンダーファー
マイケル・スコット・マッキルヴェイン
ブライアン・マイケル・ステンペル
ダレン・ユージン・ストリート
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
JP2016500974A 2013-03-14 2014-03-10 命令処理回路における冗長同期バリアの削除と、関連プロセッサシステム、方法、およびコンピュータ可読媒体 Pending JP2016515262A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/829,315 2013-03-14
US13/829,315 US20140281429A1 (en) 2013-03-14 2013-03-14 Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media
PCT/US2014/022457 WO2014159195A1 (en) 2013-03-14 2014-03-10 Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media

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JP2016515262A true JP2016515262A (ja) 2016-05-26
JP2016515262A5 JP2016515262A5 (enExample) 2017-03-23

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JP2016500974A Pending JP2016515262A (ja) 2013-03-14 2014-03-10 命令処理回路における冗長同期バリアの削除と、関連プロセッサシステム、方法、およびコンピュータ可読媒体

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US (1) US20140281429A1 (enExample)
EP (1) EP2972787B1 (enExample)
JP (1) JP2016515262A (enExample)
KR (1) KR20150129316A (enExample)
CN (1) CN105009074B (enExample)
WO (1) WO2014159195A1 (enExample)

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JP2024514502A (ja) * 2021-03-31 2024-04-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 分散型データセンタにおける適応型メモリ一貫性

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US9146741B2 (en) 2012-04-26 2015-09-29 Qualcomm Incorporated Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media
US9304940B2 (en) * 2013-03-15 2016-04-05 Intel Corporation Processors, methods, and systems to relax synchronization of accesses to shared memory
US20160224398A1 (en) * 2015-01-29 2016-08-04 Intellisis Corporation Synchronization in a Multi-Processor Computing System
US9552327B2 (en) 2015-01-29 2017-01-24 Knuedge Incorporated Memory controller for a network on a chip device
US10061531B2 (en) 2015-01-29 2018-08-28 Knuedge Incorporated Uniform system wide addressing for a computing system
US10027583B2 (en) 2016-03-22 2018-07-17 Knuedge Incorporated Chained packet sequences in a network on a chip architecture
US10346049B2 (en) 2016-04-29 2019-07-09 Friday Harbor Llc Distributed contiguous reads in a network on a chip architecture
US10108345B2 (en) * 2016-11-02 2018-10-23 Samsung Electronics Co., Ltd. Victim stream selection algorithms in the multi-stream scheme
US10437593B2 (en) * 2017-04-27 2019-10-08 Nvidia Corporation Techniques for comprehensively synchronizing execution threads
US11249766B1 (en) 2020-09-14 2022-02-15 Apple Inc. Coprocessor synchronizing instruction suppression
US11550649B2 (en) * 2021-03-17 2023-01-10 Qualcomm Incorporated System-on-chip timer failure detection and recovery using independent redundant timers
US12045615B1 (en) * 2022-09-16 2024-07-23 Apple Inc. Processing of synchronization barrier instructions
US12229561B1 (en) 2022-09-16 2025-02-18 Apple Inc. Processing of data synchronization barrier instructions

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JPH11259437A (ja) * 1998-03-12 1999-09-24 Hitachi Ltd 不要バリア命令の削減方式

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JP3896087B2 (ja) * 2003-01-28 2007-03-22 松下電器産業株式会社 コンパイラ装置およびコンパイル方法
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Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
JPH11259437A (ja) * 1998-03-12 1999-09-24 Hitachi Ltd 不要バリア命令の削減方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024514502A (ja) * 2021-03-31 2024-04-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 分散型データセンタにおける適応型メモリ一貫性
JP7660704B2 (ja) 2021-03-31 2025-04-11 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 分散型データセンタにおける適応型メモリ一貫性

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EP2972787A1 (en) 2016-01-20
CN105009074A (zh) 2015-10-28
KR20150129316A (ko) 2015-11-19
EP2972787B1 (en) 2018-11-14
WO2014159195A1 (en) 2014-10-02
US20140281429A1 (en) 2014-09-18
CN105009074B (zh) 2018-12-07

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