JP2016515262A5 - - Google Patents

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Publication number
JP2016515262A5
JP2016515262A5 JP2016500974A JP2016500974A JP2016515262A5 JP 2016515262 A5 JP2016515262 A5 JP 2016515262A5 JP 2016500974 A JP2016500974 A JP 2016500974A JP 2016500974 A JP2016500974 A JP 2016500974A JP 2016515262 A5 JP2016515262 A5 JP 2016515262A5
Authority
JP
Japan
Prior art keywords
instruction
synchronization
next instruction
event
barrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016500974A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016515262A (ja
Filing date
Publication date
Priority claimed from US13/829,315 external-priority patent/US20140281429A1/en
Application filed filed Critical
Publication of JP2016515262A publication Critical patent/JP2016515262A/ja
Publication of JP2016515262A5 publication Critical patent/JP2016515262A5/ja
Pending legal-status Critical Current

Links

JP2016500974A 2013-03-14 2014-03-10 命令処理回路における冗長同期バリアの削除と、関連プロセッサシステム、方法、およびコンピュータ可読媒体 Pending JP2016515262A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/829,315 US20140281429A1 (en) 2013-03-14 2013-03-14 Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media
US13/829,315 2013-03-14
PCT/US2014/022457 WO2014159195A1 (en) 2013-03-14 2014-03-10 Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media

Publications (2)

Publication Number Publication Date
JP2016515262A JP2016515262A (ja) 2016-05-26
JP2016515262A5 true JP2016515262A5 (enExample) 2017-03-23

Family

ID=50543653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016500974A Pending JP2016515262A (ja) 2013-03-14 2014-03-10 命令処理回路における冗長同期バリアの削除と、関連プロセッサシステム、方法、およびコンピュータ可読媒体

Country Status (6)

Country Link
US (1) US20140281429A1 (enExample)
EP (1) EP2972787B1 (enExample)
JP (1) JP2016515262A (enExample)
KR (1) KR20150129316A (enExample)
CN (1) CN105009074B (enExample)
WO (1) WO2014159195A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9146741B2 (en) 2012-04-26 2015-09-29 Qualcomm Incorporated Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media
US9304940B2 (en) * 2013-03-15 2016-04-05 Intel Corporation Processors, methods, and systems to relax synchronization of accesses to shared memory
US10061531B2 (en) 2015-01-29 2018-08-28 Knuedge Incorporated Uniform system wide addressing for a computing system
US20160224398A1 (en) * 2015-01-29 2016-08-04 Intellisis Corporation Synchronization in a Multi-Processor Computing System
US9552327B2 (en) 2015-01-29 2017-01-24 Knuedge Incorporated Memory controller for a network on a chip device
US10027583B2 (en) 2016-03-22 2018-07-17 Knuedge Incorporated Chained packet sequences in a network on a chip architecture
US10346049B2 (en) 2016-04-29 2019-07-09 Friday Harbor Llc Distributed contiguous reads in a network on a chip architecture
US10108345B2 (en) * 2016-11-02 2018-10-23 Samsung Electronics Co., Ltd. Victim stream selection algorithms in the multi-stream scheme
US10437593B2 (en) * 2017-04-27 2019-10-08 Nvidia Corporation Techniques for comprehensively synchronizing execution threads
US11249766B1 (en) * 2020-09-14 2022-02-15 Apple Inc. Coprocessor synchronizing instruction suppression
US11550649B2 (en) * 2021-03-17 2023-01-10 Qualcomm Incorporated System-on-chip timer failure detection and recovery using independent redundant timers
US11656796B2 (en) * 2021-03-31 2023-05-23 Advanced Micro Devices, Inc. Adaptive memory consistency in disaggregated datacenters
US12045615B1 (en) * 2022-09-16 2024-07-23 Apple Inc. Processing of synchronization barrier instructions
US12229561B1 (en) 2022-09-16 2025-02-18 Apple Inc. Processing of data synchronization barrier instructions

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430740A (en) * 1992-01-21 1995-07-04 Nokia Mobile Phones, Ltd. Indication of data blocks in a frame received by a mobile phone
JP3532037B2 (ja) * 1996-07-31 2004-05-31 富士通株式会社 並列計算機
JPH11259437A (ja) * 1998-03-12 1999-09-24 Hitachi Ltd 不要バリア命令の削減方式
US7100021B1 (en) * 2001-10-16 2006-08-29 Cisco Technology, Inc. Barrier synchronization mechanism for processors of a systolic array
GB2392742B (en) * 2002-09-04 2005-10-19 Advanced Risc Mach Ltd Synchronisation between pipelines in a data processing apparatus
US7065596B2 (en) * 2002-09-19 2006-06-20 Intel Corporation Method and apparatus to resolve instruction starvation
JP3896087B2 (ja) * 2003-01-28 2007-03-22 松下電器産業株式会社 コンパイラ装置およびコンパイル方法
US7278014B2 (en) * 2004-12-02 2007-10-02 International Business Machines Corporation System and method for simulating hardware interrupts
US7984202B2 (en) * 2007-06-01 2011-07-19 Qualcomm Incorporated Device directed memory barriers
US20090073101A1 (en) * 2007-09-19 2009-03-19 Herz William S Software driven display restore mechanism
US8316194B2 (en) * 2009-12-15 2012-11-20 Intel Corporation Mechanisms to accelerate transactions using buffered stores
US8402218B2 (en) * 2009-12-15 2013-03-19 Microsoft Corporation Efficient garbage collection and exception handling in a hardware accelerated transactional memory system
GB2478328B (en) * 2010-03-03 2015-07-01 Advanced Risc Mach Ltd Method, apparatus and trace module for generating timestamps

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