KR20150056166A - Level shifter circuit and organic light emitting display device including the same - Google Patents

Abstract

An organic light emitting display device according to the present invention includes a pixel part which includes a plurality of pixels and a control driving unit which simultaneously applies a control signal for driving the pixel part to the pixels. The control driving unit includes a plurality of input channels, a plurality of output channels corresponding to the input channels, and a level shifter circuit which includes a plurality of level shifter parts which are formed between the input channel and the output channel and convert the voltage level of the control signal. Two or more level shifter parts are selectively connected to any one input channel.

Description

TECHNICAL FIELD [0001] The present invention relates to a level shifter circuit and an organic light emitting diode (OLED)

An embodiment of the present invention relates to a level shifter circuit and an organic light emitting display device including the same. More particularly, the present invention relates to a level shifter circuit capable of preventing circuit damage due to an overcurrent and an organic light emitting display including the same.

Of the display devices, an organic light emitting display (OLED) displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. Such an organic light emitting display device is fast becoming a next generation display because it has a fast response speed and is controlled with low power consumption.

The organic light emitting display includes a driver for generating various control signals for driving and outputting the control signals to the pixels. The driver may include a level shifter circuit for converting a control signal into a voltage level suitable for driving a pixel have.

It is required that the amount of current of the control signal be increased for smooth driving in an organic light emitting display device in which a control signal is simultaneously applied to a plurality of pixels. There has been proposed a level shifter circuit having a wiring structure in which a plurality of input and output channels are grouped so as to increase the amount of control signal and the grouped channels are connected to each other.

In this level shifter circuit, the same signal is input to the grouped input channel, and the same signal is output to the grouped output channel, and the amount of current is increased by the superimposed signal.

However, when different signals are inputted to the level shift circuit due to damage of the input channel or open / short of wiring, an overcurrent is generated through a current path formed between the high potential drive power supply and the low potential drive power supply of the level shift circuit There is a problem that the circuit is damaged and a fire may occur.

Accordingly, it is an object of the present invention to provide a level shifter circuit capable of preventing circuit damage due to an overcurrent and an organic light emitting display device including the same.

An organic light emitting display according to an embodiment of the present invention includes a pixel portion including a plurality of pixels; And a control driver for simultaneously applying a control signal for driving the pixel unit to the plurality of pixels, wherein the control driver includes: a plurality of input channels; a plurality of output channels corresponding to the input channels; And a level shifter circuit which is provided between the input channel and the output channel and converts a voltage level of the control signal, and a level shifter circuit in which two or more level shifter parts are selectively connected to one of the input channels .

In one embodiment, the level shifter circuit may include a switching unit that selectively connects the two or more level shifter units to one input channel in accordance with a switching control signal.

In one embodiment, the apparatus may further include a timing driver for outputting the switching control signal.

In one embodiment, the plurality of level shifter sections are divided into two or more grouped blocks, and the switching control signal may be applied to each block.

In one embodiment, the level shifter may include a pair of p-channel transistors and an n-channel transistor connected between the first driving power supply and the second driving power supply.

In one embodiment, the control driver supplies a first control signal to a first control line during a first period of one frame, a second control signal to a second control line during a second period, The emission control signal can be supplied to the emission control line.

In one embodiment, the scan driver may further include a scan driver for sequentially supplying scan signals to the scan lines during the third period.

In one embodiment, the data driver may further include a data driver for supplying a data signal in synchronization with the scan signal to the data lines during the third period.

A level shifter circuit according to an embodiment of the present invention includes a plurality of input channels, a plurality of output channels corresponding to the input channels, And a plurality of level shifters provided between the input channel and the output channel for converting a voltage level of the input signal, wherein at least two level shifter units are selectively connected to any one of the input channels.

In one embodiment, the switching unit may include a switching unit that selectively connects the two or more level shifter units to one of the input channels according to the switching control signal.

In one embodiment, the level shifter circuit may be implemented in one integrated circuit chip (IC).

According to the present invention, since two or more level shifter units are selectively connected to any one of the input channels, it is possible to prevent circuit damage and fire caused by an error of the input signal.

FIG. 1 is a schematic diagram showing an organic light emitting display according to an embodiment of the present invention. Referring to FIG.
2 is a configuration diagram showing an embodiment of the level shifter circuit shown in FIG.
3A and 3B are diagrams for explaining the operation of the level shifter circuit shown in FIG.
4 is a circuit diagram showing one embodiment of the pixel shown in Fig.
FIG. 4B is a waveform diagram for explaining a method of driving the pixel shown in FIG. 4A.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing an organic light emitting display according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 1, the organic light emitting display includes a pixel portion 10, a timing controller 20, a data driver 30, a scan driver 40, and a control driver 50.

The pixel portion 10 includes a plurality of scan lines S1 to Sn formed in a row direction to transmit a scan signal and a plurality of data lines D1 to Sn formed in a column direction, Dm and a plurality of pixels PX arranged in a matrix form. In one embodiment, the pixels PX are controlled by the organic light emitting device OLED, which receives the first power ELVDD and the second power ELVSS and emits light with a brightness corresponding to the data signal, And may include a plurality of switching elements.

The timing controller 20 receives input control signals such as a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync and a clock signal CLK ). The timing controller 20 may process the inputted image data DATA to generate corrected image data DATA 'suitable for image display of the pixel unit 10, and the corrected image data DATA' To the data driver (30). The timing controller 20 includes a data control signal DCS for controlling the driving of the data driver 30 based on the input control signals and a scan control signal SCS for controlling the driving of the scan driver 40, Can be generated and output.

The data driver 30 is connected to the plurality of data lines D1 to Dm and generates a data signal (or a data voltage) in response to the data control signal DCS of the timing controller 20, And outputs them to the data lines D1 to Dm. At this time, the data driver 30 converts the digital image data DATA 'provided from the timing controller 20 into analog data voltages and outputs them to the data lines D1 through Dm. The data driver 30 receives gamma reference voltages from a gamma reference voltage generator (not shown), and generates a data signal based on the gamma reference voltages.

The scan driver 40 is connected to the scan lines S1 to Sn and generates a scan signal in response to the scan control signal SCS of the timing controller 20 and supplies the generated scan signal to the scan lines S1 to Sn, . The pixels PX of one row may be sequentially selected in accordance with the scan signal so that the data signal may be provided. The scan driver 40 sequentially supplies the scan signals according to a predetermined scan frequency, and the scan frequency can be controlled by the timing controller 20. [

The control driver 50 simultaneously applies a control signal for driving the pixel unit 10 to the pixels PX. The control signal is used to compensate the threshold voltage of the transistor included in the pixels PX and the first control signal for initializing the pixels PX, the light emission control signal for light emission and data writing of the pixels PX, Lt; / RTI > Specifically, the control driver 50 supplies a light emission control signal to the emission control line E commonly connected to the pixels PX, a first control line CL1 commonly connected to the pixels PX, And supplies the second control signal to the second control line CL2 commonly connected to the pixels PX. The emission control signal, the first control signal, and the second control signal may be output at different timings.

In addition, the control driver 50 includes a level shifter circuit 53 for raising the voltage level of the control signal. As described above, since the control signal is simultaneously applied to the pixels PX, it is required that the high output, that is, the amount of current is increased. For this purpose, it is possible to increase the amount of control signal current by using a plurality of grouped channels, rather than outputting a control signal through a single channel. A detailed description of the level shifter circuit 53 will be given with reference to Figs. 2, 3A and 3B.

1, the light emission control line E and the first and second control lines CL1 and CL2 are connected to the control driver 50 for convenience of explanation. However, the light emission control line E, the first And the second control lines CL1 and CL2 may be connected to various driving parts. For example, the emission control line E and the first and second control lines CL1 and CL2 may be commonly connected to the scan driver 40, respectively.

2 is a configuration diagram showing an embodiment of the level shifter circuit shown in FIG.

The level shifter circuit 53 of this embodiment assumes the case where the level shifter circuit of the control driver 50 and the level shifter circuit of the scan driver 40 are integrally mounted on one integrated circuit chip (IC).

2, the level shifter circuit 53 includes a plurality of input channels IN_1 to IN_12, a plurality of output channels OUT_1 to OUT_12 corresponding to the input channels IN_1 to IN_12, And a plurality of level shifter units 55 connected to the output channels OUT_1 to OUT_12 one at a time.

Signals input through the input channels IN_1 to IN_12 are output via the output channels OUT_1 to OUT_12 via the level shifter unit 55 with the voltage level raised. Specifically, when the low-voltage scan signals SCLK1_I to SCLK3_I are input to the level shifter circuit 53, the scan signals SCLK1 to SCLK3 whose voltage levels are increased are output. When the low-voltage emission control signal GE_I is input to the level shifter circuit 53, the emission control signal GE whose voltage level is raised is output. When the first control signal GI_I of low voltage is input to the level shifter circuit 53, the first control signal GI whose voltage level is raised is outputted. When the second control signal GW_I of low voltage is input to the level shifter circuit 53, the second control signal GW whose voltage level is raised is outputted.

The level shifter circuit 53 includes a plurality of input channels IN_1 to IN_12 and output channels OUT_1 to OUT_12 grouped to increase the amount of control signals GE, GI and GW, and the grouped channels are connected to each other Wiring structure. To this end, the level shifter circuit 53 may include first through fourth blocks B1 through B4. Specifically, the first block B1 individually receives and outputs the scan signals SCLK1_I to SCLK3_I of different low voltages. The second block B2 is inputted along the wiring branched from the emission control signal GE_I of the same low voltage and the plurality of emission control signals GE passing through the level shifter section 55 in the block are merged into one wiring . The third block B3 is inputted along the wiring branched from the first control signal GI_I of the same low voltage and the plurality of first control signals GI passing through the level shifter section 55 in the block are inputted to one wiring And output. The fourth block B4 is input along the wiring where the second control signal GW_I of the same low voltage is branched and the plurality of second control signals GW which have passed through the level shifter section 55 in the block are inputted to one wiring And output.

The plurality of level shifter portions 55 included in each of the first to fourth blocks B1 to B4 are selectively controlled to be connected to any one of the input channels. For control of the first to fourth blocks B1 to B4, switching control signals SC1 to SC4 may be inputted for each block. Here, the switching control signals SC1 to SC4 may be provided from the timing driver 20. For example, when the first switching control signal SC1 is low, the first block B1 is connected to the level shifter unit (not shown) in the block so as to correspond to the first to third input channels IN_1 to IN_3, 55). When the second switching control signal SC2 is high, the second block B2 is a one-to-many correspondence with the fourth input channel IN_4 which is any one of the fourth to sixth input channels IN_4 to IN_6 The level shifter section 55 in the block is connected.

The switching control method of the grouped blocks in the level shifter circuit 53 can be freely set according to the characteristics of the signal. For example, when the emission control signal GE is processed in the first block B1, the first switching control signal SC1 can be set high. The level shifter circuit 53 is not limited to the above structure and may be modified into various structures in which a plurality of level shifter portions 55 can be selectively controlled to be connected to any one of the input channels.

3A and 3B are diagrams for explaining the operation of the level shifter circuit shown in FIG.

3A and 3B, each of the plurality of blocks Bx included in the level shifter circuit 53 selectively outputs the first and second level shifter sections 55a and 55b according to the switching control signal SC And switching units SW1 and SW2 for connecting to the first input channel IN_1 or the second input channel IN_2. It should be noted that one block Bx may include two or more level shifter portions. For convenience of description, in the present embodiment, a case in which two level shifter portions 55a and 55b are included in the block Bx is explained .

The first level shifter 55a includes a pair of p-channel transistors T1 and n-channel transistors T2, which are connected between the high potential first driving power supply VGH and the low potential second driving power supply VGL, ≪ / RTI > The first input channel IN_1 is branched and connected to the gate terminals of the p-channel transistor T1 and the n-channel transistor T2 of the first level shifter 55a. The first output channel OUT1 is connected to the p- Is connected between the source electrode of the first transistor T1 and the drain electrode of the n-channel transistor T2. An inverter 58 may be provided between the first input channel IN_1 and the first level shifter 55a.

The second level shifter section 55b includes a pair of p-channel transistors T3 and n-channel transistors T4 connected between the high potential first driving power supply VGH and the low potential second driving power supply VGL, ≪ / RTI > The second input channel IN_2 is branched and connected to the gate terminals of the p-channel transistor T3 and the n-channel transistor T4 of the second level shifter section 55b, The switching units SW1 and SW2 may be provided.

When the switching control signal SC is low, the p-channel transistor T3 and the n-channel transistor T4 of the second level shifter section 55b are connected to the second input channel IN_2, respectively. That is, the first and second level shifter units 55a and 55b receive signals through different input channels. The signal inputted through the first input channel IN_1 is converted in voltage level by the first level shifter 55a and outputted through the first output channel OUT_1 and inputted through the second input channel IN_2 The voltage level of the signal is converted by the second level shifter 55b and output through the second output channel OUT_2.

When the switching control signal SC is high, the p-channel transistor T3 and the n-channel transistor T4 of the second level shifter section 55b are connected to the first input channel IN_1, respectively. At this time, the first switching unit SW1 may be connected to the first node SN1, and the second switching unit SW2 may be connected to the second node SN2. Signals input through the first input channel IN_1 are converted in voltage levels by the first and second level shifter units 55a and 55b and output through the first and second output channels OUT_1 and OUT_2. That is, the first and second level shifters 55a and 55b receive the same signal through the first input channel IN_1, and the output signal is also the same. Therefore, even if an error occurs in the input signal due to damage to the second input channel IN_2 or open / short of the wiring, circuit damage and fire can be prevented.

FIG. 4A is a circuit diagram showing an embodiment of the pixel shown in FIG. 1, and FIG. 4B is a waveform diagram illustrating a method of driving the pixel shown in FIG. 4A.

Referring to FIG. 4A, a pixel PX according to an embodiment of the present invention may include a first transistor M1, a first capacitor C1, a pixel circuit 14, and an organic light emitting diode (OLED). The anode electrode of the organic light emitting diode (OLED) is connected to the pixel circuit 14, and the cathode electrode is connected to the second power source ELVSS. The organic light emitting diode (OLED) emits light at a predetermined luminance corresponding to the amount of current supplied from the pixel circuit 14.

The pixel circuit 14 charges a predetermined voltage corresponding to the voltage supplied from the first capacitor C1, that is, the voltage of the data signal. The pixel circuit 14 controls the amount of current supplied from the first power source ELVDD to the organic light emitting diode OLED in response to the charged voltage. In the exemplary embodiment of the present invention, the pixel circuit 144 may include the second to eighth transistors M8 to M8 and the storage capacitor Cst.

Referring to FIG. 4B, one frame period of the pixel driving method according to the embodiment of the present invention is divided into a first period T1, a second period T2, and a third period T3.

The first period T1 is a period for supplying the voltage of the initializing power source Vint to the gate electrode of the second node N2, that is, the driving transistor M2 as an initializing period. The second period T2 is a period for compensating the threshold voltage of the second transistor M2 as a compensation period. In the third period T3, a voltage corresponding to the data signal is charged in the first capacitor C1 and the storage capacitor Cst as a light emission and data write period, and at the same time, the organic light emitting diode OLED generates light of a predetermined luminance Period.

First, the emission control signal GE is supplied to the emission control line E during the first period T1 and the second period T2, and the emission control signal GE is not supplied during the third period T3 . The seventh transistor M7 and the eighth transistor M8 are turned off when the emission control signal GE is supplied to the emission control line E during the first period T1 and the second period T2. Then, the second transistor M2 and the organic light emitting diode OLED are electrically disconnected from each other, and thus the organic light emitting diode OLED is set to the non-light emitting state during the first period T1 and the second period T2. do.

The first control signal GI is supplied to the first control line CL1 during the first period T1. When the first control signal GI is supplied to the first control line CL1, the fifth transistor M5 and the sixth transistor M6 are turned on. When the fifth transistor M5 is turned on, the voltage of the initializing power source Vint is supplied to the second node N2. When the sixth transistor M6 is turned on, the voltage of the first power ELVDD is supplied to the third node N3. Here, since the initialization power source Vint is set to a lower voltage than the data signal, the first transistor M1 is set to the on-bias state during the first period T1.

And the second control signal GW is supplied to the second control line CL2 during the second period T2. When the second control signal GW is supplied to the second control line CL2, the third transistor M3 and the fourth transistor M4 are turned on. When the fourth transistor M4 is turned on, the second transistor M2 is connected in a diode form. When the third transistor M3 is turned on, the voltage of the data signal stored in the first capacitor C1 is supplied to the third node N3. At this time, the second transistor M2 is turned on because the voltage of the second node N2 is initialized to the voltage of the initialization power source Vint lower than the data signal. When the second transistor M2 is turned on, the voltage applied to the third node N3 is supplied to the second node N2 via the second transistor M2 connected in a diode form. At this time, the storage capacitor Cst stores the data signal and the voltage corresponding to the threshold voltage of the second transistor M2.

The supply of the emission control signal CL3 to the emission control line E is interrupted during the third period T3. The seventh transistor M7 and the eighth transistor M8 are turned on when the supply of the emission control signal GE to the emission control line E is interrupted. When the seventh transistor M7 is turned on, the first power ELVDD and the third node N3 are electrically connected. When the eighth transistor M8 is turned on, the fourth node N4 is electrically connected to the organic light emitting diode OLED. The second transistor M2 controls the amount of current flowing from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED corresponding to the voltage applied to the second node N2 . At this time, the organic light emitting diode OLED generates light of a predetermined luminance corresponding to the amount of current supplied to the organic light emitting diode OLED.

Meanwhile, the scan signals SCLK are sequentially supplied to the scan lines S1 to Sn during the third period T3. When the scan signal SCLK is sequentially supplied to the scan lines S1 to Sn, the first transistor M1 included in each of the pixels PX is turned on for each horizontal line. When the first transistor M1 is turned on, the data signal DATA from the data lines D1 to Dm is supplied to the first node N1 included in each of the pixels PX. In this case, the first capacitor C1 charges the voltage corresponding to the data signal DATA.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications may be made without departing from the scope of the present invention.

10: Pixel unit PX:
20: timing control unit 30: data control unit
40: scan control unit 50:
53: level shifter circuit 55: level shifter section
Bx: Block

Claims (11)

A pixel portion including a plurality of pixels;
And a control driver for simultaneously applying a control signal for driving the pixel portion to the plurality of pixels,
The control driver includes:
A plurality of input channels; a plurality of output channels corresponding to the input channels; And
And a plurality of level shifter units provided between the input channel and the output channel for converting a voltage level of the control signal,
And a level shifter circuit in which two or more level shifter portions are selectively connected to any one of the input channels. The semiconductor memory device according to claim 1, wherein the level shifter circuit comprises:
And a switching unit for selectively connecting the two or more level shifter units to one input channel according to a switching control signal. 3. The method of claim 2,
And a timing driver for outputting the switching control signal. 3. The method of claim 2,
Wherein the plurality of level shifter sections are divided into at least two groups of blocks, and the switching control signal is applied to each of the plurality of level shifter sections. The semiconductor memory device according to claim 1,
And a pair of p-channel transistors and an n-channel transistor connected between the first driving power supply and the second driving power supply. 2. The apparatus of claim 1, wherein the control driver
Supplies a first control signal to a first control line during a first period of one frame, supplies a second control signal to a second control line during a second period, and supplies an emission control signal to the emission control line during a third period And the organic electroluminescent display device. The method according to claim 6,
And a scan driver sequentially supplying scan signals to the scan lines during the third period. 8. The method of claim 7,
And a data driver for supplying a data signal in synchronization with the scan signal to the data lines during the third period. A plurality of input channels; a plurality of output channels corresponding to the input channels; And
And a plurality of level shifters provided between the input channel and the output channel for converting a voltage level of the input signal,
Wherein at least two level shifter portions are selectively connected to any one of the input channels. 10. The method of claim 9,
And a switching unit for selectively connecting the two or more level shifter units to one of the input channels according to the switching control signal. 10. The method of claim 9,
Characterized in that the level shifter circuit is mounted on one integrated circuit chip (IC)

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