JP2004046054A - Displaying device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-definition, multi-gradation, and low-cost displaying device with small power consumption. <P>SOLUTION: A driving circuit integrated type active matrix display device is equipped with a display panel, a controller IC 102 having a display memory 111, an output buffer 12 reading data out of the display memory and outputting them to a display panel part, and a controller 113 communicating with a host device and performing control. The display panel part is equipped with a DAC circuit 106 which constitutes a portion of a data line driving circuit and converts display data of a digital signal into an analog signal; and a bus for data transfer between the controller IC 102 and the data line driving circuit of the display panel part has a wider width than a bus between the controller and host device so that more bit data are transferred in parallel at each time, thereby lowering the operation frequency of the data line driving circuit. <P>COPYRIGHT: (C)2004,JPO

Description

【０２６７】
図４５に示した本発明の実施例に係る表示装置は、表示デバイス基板（図４５ではガラス基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ））が、複数のデータ線（Ｎ本）と複数の走査線（Ｍ本）の交点にマトリクス状にＭ行Ｎ列に配置された画素群を有する表示部表示領域（Ｄｉｓｐｌａｙ　Ａｒｅａ）を備え、Ｂビット（図４５では６ビット）の階調の表示データを（Ｍ×Ｎ）画素分（すなわち（Ｍ×Ｎ×Ｂ）ビット）格納する表示メモリ（Ｆｒａｍｅ　Ｍｅｍｏｒｙ）と、表示メモリからデータ（Ｄｉｇｉｔａｌ　Ｉｍａｇｅ　Ｄａｔａ）を読み出し前記表示パネル基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）側へ出力する出力バッファと、前記表示メモリおよび前記出力バッファを制御し上位装置との通信並びに制御を司るコントローラと、を有するコントローラ装置（Ｃｏｎｔｒｏｌｌｅｒ　Ｆｒａｍｅ　Ｍｅｍｏｒｙ）を備えており、コントローラ装置において前記出力バッファは、前記メモリの（Ｍ×Ｎ×Ｂ）ビットの内の１行分に相当する（Ｎ×Ｂ）ビットを、ブロック分割数Ｓの数とＰ相で分割した｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝個配置されている。
【０２６８】
図４５に示す例では、Ｎ＝１７６×３（ＲＧＢ分）＝５２８、Ｍ＝２３４、Ｓ＝８、Ｐ＝２である。表示領域（Ｄｉｓｐｌａｙ　Ａｒｅａ）のデータ線（信号線）の本数はＳ００１〜Ｓ５２８の計５２８本であり、データバスのデータ線の本数（コントローラ装置の出力バッファの個数）は、｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝＝５２８×６／（８×２）＝６６×３＝１９８であり、コントローラＩＣ（Ｃｏｎｔｒｏｌｌｅｒ　Ｆｒａｍｅ　Ｍｅｍｏｒｙ）と、ガラス基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）との間にはデジタル映像データ（Ｄｉｇｉｔａｌ　Ｉｍａｇｅ　Ｄａｔａ）転送用のデータバスがＤ００１〜Ｄ１９８の１９８ビット設けられ、１２５ＫＨｚの転送レートで駆動される。
【０２６９】
ガラス基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）上の表示領域のデータ線を駆動するデータ線駆動回路（Ｄａｔａ　Ｄｒｉｖｅｒ）には、｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝ビット幅のデータバスを介して、表示データ（デジタル映像データ）が転送される。１水平期間には、｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝ビットのデジタル映像データが、（Ｐ×Ｓ）回に分割されて、１ライン分の表示データが転送される。図４５に示す例では、１９８ビット幅のデータ（Ｄ００１〜Ｄ１９８）が、２×８回に分割されて１ライン分の表示データが転送される。
【０２７０】
ガラス基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）上のデータ線駆動回路（Ｄａｔａ　Ｄｒｉｖｅｒ）は、データバスのうちの１本のデータ線に対して共通に接続されるＰ個のレベルシフト回路（ＬＳ）であって、コントローラ装置側の出力バッファより出力され、データ線を介して順次受け取ったＰ相の信号の振幅をそれぞれより高い振幅の信号にレベルシフトするレベルシフト回路と、Ｐ個の前記レベルシフト回路の出力を駆動クロックにしたがってそれぞれラッチし、Ｐ相のシリアルビットデータを、Ｐ個のパラレルビットに展開してＰビットパラレルデータとしてラッチ出力するラッチ回路（ＬＡＴｓ）を備えたＰ相展開回路（ＳＰＣ）を備え、｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝本のデータ線のデータバスに対して、このＰ相展開回路（ＳＰＣ）を｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝個備えている。｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝個のＰ相展開回路（ＳＰＣ）からは、｛（Ｎ×Ｂ）／Ｓ｝ビットのデータがパラレルに出力される、このうちのＢビットの出力を入力してアナログ信号を出力するデジタル・アナログ変換回路（「ＤＡＣ回路」という）を（Ｎ／Ｓ）個備え、（Ｎ／Ｓ）個の前記ＤＡＣ回路の出力を入力を受け、表示部のＮ本のデータ線に出力するセレクタとを含む。
【０２７１】
図４５に示した構成においては、レベルシフト回路（ＬＳ）を２つと複数のラッチ回路（ＬＡＴｓ）よりなる２相展開回路（ＳＰＣ）が、｛（Ｎ×Ｂ）／（Ｐ×Ｓ）｝個、すなわち、｛（５２８×６）／（２×８）｝＝６６×３＝１９８個、並設されている。当然のことながら、この数は、データ信号線Ｄ００１〜Ｄ１９８の本数と等しい。１９８個の２相展開回路（ＳＰＣ）からは、｛（５２８×６）／８｝＝６６×６＝３９６ビット（Ｇ００１〜Ｇ３９６）のデータが出力される。さらに、６ビットのＤＡＣ回路（６ｂ−ＤＡＣ）を、（Ｎ／Ｓ）＝５２８／８＝６６個備えており、６６個のＤＡＣ回路（６ｂ−ＤＡＣ）の出力（６６のアナログ電圧出力）を入力に受け、表示部（Ｄｉｓｐｌａｙ　Ａｒｅａ）のＮ本（５２８本）のデータ線（Ｓ００１〜Ｓ５２８）に出力するセレクタは、１対８のデマルチプレクサとして構成される。１対８のデマルチプレクサは、１本の信号を８本の出力に分割する。このデマルチプレクサ（１−ｔｏ−８ＤＥＭＵＸ）を（Ｎ／Ｓ）＝６６個備えている。セレクタ回路（１−ｔｏ−８ＤＥＭＵＸ×６６）は、６６個のＤＡＣ回路（６ｂ−ＤＡＣ）の出力を受け、セレクタ制御信号に基づき、６６個の各ＤＡＣ回路の出力（６６個のアナログ電圧出力）を、ブロック分割数８に分割された時間で、順次、６６本のデータ線群へデータ信号の供給を行う。さらに、表示部（Ｄｉｓｐｌａｙ　Ａｒｅａ）の複数の走査線に順次電圧を印加する走査線駆動回路（Ｓｃａｎ　Ｌｉｎｅ　Ｄｒｉｖｅｒ）を備えている。
【０２７２】
コントローラ装置は、ガラス基板上のレベルシフト回路（Ｌｅｖｅｌ　Ｓｈｉｆｔｅｒ　（２））に、クロック（ＣＬＫ）（周波数６２．５ｋＨｚ）、水平同期信号（Ｈｓｙｎｃ）、垂直同期信号（Ｖｓｙｎｃ）等の制御信号を供給する。データバスとともにこれらのクロック、制御信号は３．０Ｖインタフェースに従う。レベルシフト回路（Ｌｅｖｅｌ　Ｓｈｉｆｔｅｒ　（２））では、クロック、制御信号を１０Ｖ系にレベル変換し、タイミング回路（Ｔｉｍｉｎｇ　Ｃｉｒｃｕｉｔ）に出力する。タイミング回路（Ｔｉｍｉｎｇ　Ｃｉｒｃｕｉｔ）は、１０Ｖ振幅のクロック（ＣＬＫ）と、クロック（ＣＬＫ）の相補クロックであるＸＣＬＫを、ＳＰＣ等に供給する。また電源回路（Ｐｏｗｅｒ）は、ガラス基板に電源電圧１０Ｖ、−５Ｖ等を供給する。
【０２７３】
このように、ガラス基板上に集積されたデータドライバ（ＤＡＴＡ　Ｄｒｉｖｅｒ）は、３Ｖインターフェイス用サンプリングレベル変換と２相展開回路（ＳＰＣ）、６ｂｉｔ　ＤＡＣ、１−対−８デマルチプレクサ（１　ｔｏ　８　ＤＥＭＵＸ）で構成される。
【０２７４】
図４６は、図４５の２相展開回路（ＳＰＣ）の１つのエレメントの回路（１つのデータ信号Ｄ（ｎ）に接続されるＳＰＣ）の一例を示す図である。この２相展開回路（ＳＰＣ）（１ビットシリアルデータを２ビットパラレルデータに変換する回路）は、データバッファの出力Ｄ（ｎ）（０−３Ｖ）に共通に接続される２つのサンプリングレベルシフト回路（ＬＳ）と、２つのサンプリングレベル変換回路（ＬＳ）の各出力に接続される複数のラッチ回路（ＬＡＴ）を含み、各ラッチ回路は、サンプリングクロックＣＬＫとその相補のクロックＸＣＬＫで入力データをラッチする。
【０２７５】
図４６のＳＰＣ内の上側の第１のサンプリングレベルシフト回路（ＬＳ）は、高位側電源（この例では１０Ｖ）と低位側電源（ＧＮＤ）間に直列形態に接続され、第１乃至第３のスイッチ素子をなす第１乃至第３のＭＯＳトランジスタ（Ｐ１、Ｎ３、Ｎ２）と、第１、第２のＭＯＳトランジスタ（Ｐ１、Ｎ３）の接続点に接続されている容量（Ｃ２）と、Ｄ（ｎ）に接続される入力端子と第３のＭＯＳトランジスタ（Ｎ２）のゲート端子との間に接続され、第４のスイッチ素子をなす第４のＭＯＳトランジスタ（Ｎ１）と、第３のＭＯＳトランジスタ（Ｎ２）のゲートに接続されている容量（Ｃ１）と、を備え、第１、第２のＭＯＳトランジスタ（Ｐ１、Ｎ３）のゲートには第１のサンプリングクロック（ＣＬＫ）（０−１０Ｖ）が共通入力され、第４のＭＯＳトランジスタ（Ｎ１）のゲートには、第１のサンプリングクロック（ＣＬＫ）に相補の第２のサンプリングクロック（ＸＣＬＫ）が入力される。
【０２７６】
このサンプリングレベルシフト回路（ＬＳ）の動作を説明すると、第１のサンプリングクロック（ＣＬＫ）がｌｏｗレベルのとき（セットアップ期間）、第１のスイッチ素子をなすＭＯＳトランジスタ（Ｐ１）がオンし、第２のスイッチ素子をなすＭＯＳトランジスタ（Ｎ３）はオフし、容量（Ｃ２）が高位側電源の電源電圧に充電される。第２のサンプリングクロック（ＸＣＬＫ）がｈｉｇｈレベルのとき第４のスイッチ素子をなす第４のＭＯＳトランジスタ（Ｎ１）がオンし、容量（Ｃ１）は入力信号電圧で充電される。
【０２７７】
第１のサンプリングクロック（ＣＬＫ）がｈｉｇｈレベルのとき（出力期間）、第１のスイッチ素子をなすＭＯＳトランジスタ（Ｐ１）はオフし、第２のスイッチ素子をなすＭＯＳトランジスタ（Ｎ３）がオンし、このときの容量（Ｃ２）の端子電圧が、直接に、又は、間接的に、出力信号として取り出される。サンプリングレベルシフト回路（ＬＳ）は、ガラス基板上に搭載されており、第１のＭＯＳトランジスタＰ１は、Ｐ型ＴＦＴよりなり、第２乃至第４のＭＯＳトランジスタＮ３、Ｎ２、Ｎ１は、Ｎ型ＴＦＴ（Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ）よりなる。
【０２７８】
図４６のＳＰＣの下側の第２のサンプリングレベルシフト回路（ＬＳ）も、構成は同様とされており、サンプリングクロックの接続が、第１のサンプリングレベルシフト回路（ＬＳ）と相違している。第１、第２のＭＯＳトランジスタ（Ｐ１、Ｎ３）のゲートには第２のサンプリングクロック（ＸＣＬＫ）が共通入力され、第４のＭＯＳトランジスタ（Ｎ１）のゲートには、第１のサンプリングクロック（ＣＬＫ）が入力される。この第２のサンプリングレベルシフト回路（ＬＳ）は、第２のサンプリングクロック（ＸＣＬＫ）がｌｏｗレベルのとき（セットアップ期間）、第２のサンプリングクロック（ＸＣＬＫ）がｈｉｇｈレベルのとき（出力期間）となり、第１のサンプリングレベルシフト回路（ＬＳ）と相補の動作を行う。
【０２７９】
図４６に示した、本発明のサンプリングレベルシフト回路（ＬＳ）によれば、以下の作用効果を奏する。
（ａ）定常電流が流れないため、低消費電力である。
（ｂ）単相入力（＝反転データ不要）のため、端子数が少なくてすむ（一般的なレベル変換回路はデータと反転データの２入力を必要とする）。
（ｃ）入力端子に、高電圧側の電位が発生することがなく、低電圧側の回路を破壊する可能性が低い。図４４に示したラッチ型センスアンプをレベルシフタに用いた場合、入力端子に高電圧側の電位が生じる場合がある。
【０２８０】
ポリシリコンＴＦＴ　ＬＣＤの場合、例えば、２００個ほどのデータ入力端子を備える構成とされており、本発明は、このように多数のデータのサンプリングとレベルシフトが必要とされる用途に用いた場合、特に有効である。
【０２８１】
図４６に示すように、２相展開回路（ＳＰＣ）においては、第１、第２のサンプリングレベルシフト回路（ＬＳ）を備え、第１及び第２のサンプリングレベルシフト回路には入力信号Ｄ（ｎ）が共通に入力され、第２のサンプリングレベルシフト回路には、第１のサンプリングレベルシフト回路の第１、第２のサンプリングクロック信号（ＣＬＫ、ＸＣＬＫ）の値が反転された値の信号（すなわちＸＣＬＫ、ＣＬＫ）が第１、第２のサンプリングクロックとして、それぞれ対応するスイッチ素子に入力され、第１のサンプリングレベルシフト回路の出力を前第１のサンプリングクロック信号（ＣＬＫ）に基づき取り込む第１のラッチ（ＬＡＴ）、第１のラッチ（ＬＡＴ）の出力を第２のサンプリングクロック信号（ＸＣＬＫ）に基づきラッチ出力する第２のラッチ（ＬＡＴ）と、第２のラッチ（ＬＡＴ）のラッチの出力を第１のサンプリングクロック信号（ＣＬＫ）に基づき出力する第３のラッチ（ＬＡＴ）と、第２のサンプリングレベルシフト回路の出力を第２のサンプリングクロック信号（ＸＣＬＫ）に基づき取り込む第４のラッチ（ＬＡＴ）と、第４のラッチの出力を第１のサンプリングクロック信号（ＣＬＫ）に基づき出力する第５のラッチ（ＬＡＴ）と、を備えている。第１、第２のラッチは、第１のマスタースレーブ型のラッチを構成しており、第４、第５のラッチは、第２のマスタースレーブ型のラッチを構成している。各ラッチ（ＬＡＴ）は、入力されるクロック信号で活性化が制御され、入力と出力がラッチの入力端子と出力端子に接続された第１のクロックドインバータと、第１のクロックドインバータの出力に入力が接続されたインバータと、インバータの出力に入力が接続され、出力がインバータの入力に接続された第２のクロックドインバータとを備え、第１、第２のクロックドインバータは、それぞれクロックＣＬＫと相補のクロックＸＣＬＫで活性化／非活性化が制御される。
【０２８２】
図４７は、図４６の回路のこの動作波形を示す図である。３段縦続接続されたラッチ出力から、奇数番目の信号（Ｇ（２ｎ−１））が、２段縦続接続されたラッチ出力から、偶数番目の信号（Ｇ（２ｎ））がパラレルに、第１のサンプリングクロック信号（ＣＬＫ）に同期して出力される。
【０２８３】
図４５に示す表示装置において、デジタル映像データ（Ｄｉｇｉｔａｌ　Ｉｍａｇｅ　Ｄａｔａ）は、３Ｖ振幅、１９８ビット幅で外部コントローラＩＣより入力され、デジタル信号処理回路（ＳＰＣのアレイ）により、信号レベルを１０Ｖ振幅に変換し、又所望のタイミングで、ＤＡＣに供給される。１つのＤＡＣの出力はデマルチプレクサ（ＤＥＭＵＸ）を用いて画素アレイ（Ｄｉｓｐｌａｙ　Ａｒｅａ）に接続された８本のデータ線を時分割で駆動する。
【０２８４】
この構成の特徴は、太いバス幅（１９８ｂｉｔ幅）をもつインターフェイスを経由して低速でデータが供給され、このデータは、ガラス基板上で、パラレルに駆動されたレベル変換機能を持つ２相展開回路（ＳＰＣ）で処理される点である。このように、多数の相展開回路を、パラレルに駆動することによって、デジタル信号処理を行うので、この構成を「パラレル・デジタルデータドライバ・アーキテクチャ」と呼ぶ。
【０２８５】
表２に、このパラレル・デジタルデータドライバ・アーキテクチャと、従来のアーキテクチャとを比較し、このパラレルアーキテクチャがなぜ低消費電力なのか考察する。
【０２８６】
表２　アーキテクチャの比較

（）内は比を示す
【０２８７】
本発明のパラレル・ドライバ・アーキテクチャでは、デジタル映像データのインターフェイスのバス幅を広くし、１９８個の２相展開回路（ＳＰＣ）を、パラレルに駆動することで、スループットを維持したまま、クロック周波数を、２．１ＭＨｚから６２．５ｋＨｚに低減している。
【０２８８】
ＤＡＣより手前（ＤＡＣの入力側）に配置されるデジタル信号処理回路について注目すると、本発明のパラレル・ドライバ・アーキテクチャでは、６２．５ｋＨｚで駆動されるクロックラインに、５１４８個のトランジスタが接続され、一方、従来のアーキテクチャでは、２．１ＭＨｚで駆動されるシフトレジスタのクロックラインに３９６個のトランジスタが接続される。
【０２８９】
それぞれのアーキテクチャでクロックラインに接続されるトランジスタ数とクロック周波数との積を計算すると、パラレルアーキテクチャの方が小さい。つまり、クロックラインの充放電に伴う消費電力は、パラレルアーキテクチャの方が小さくなる。
【０２９０】
また、パラレルアーキテクチャでは、デジタルデータバスラインとその支線とのインタラインカップリングが存在しないため、その充放電に関する電力は０である。
【０２９１】
インタラインカップリング、つまり、デジタルデータを伝達するある配線が、他のデジタルデータを伝達するある配線とクロスする場所に生じる容量について説明する。
【０２９２】
図３９に示した例の場合、入力されるデータのバス幅が６ビットで、シフトレジスタ（６６−ｂｉｔ　Ｓｈｉｆｔ−Ｒｅｇｉｓｔｅｒ）とデータラッチ（ＤＡＴＡ−ＲＥＧＩＳＴＥＲ）とロードラッチ（ＬＯＡＤ−ＬＡＴＣＨ）で構成される相展開回路によって展開された、相展開後のデータのバス幅は、６×６６ｂｉｔである。
【０２９３】
このとき、バスラインとその支線との交差点の数は、９７５個である。一般に、入力されるデータのバス幅がｎビット、相展開回路によって出力されるバス幅がｋ×ｎビットの場合、インタラインカップリングの個数Ｃは
Ｃ＝ｎ（ｎ−１）（ｋ−１）／２
で示される。すなわち、
インタラインカップリング（図３９内でＣｉと記述されている）の数は、９７５個であり、一般にこのような構成の場合、入力されるデータのバス幅がｎビット、相展開回路によって出力されるバス幅がｋ×ｎビットの場合、インタラインカップリングの個数Ｃは、すくなくとも
Ｃ＝ｎ（ｎ−１）（ｋ−１）／２
で示される個数存在する。
【０２９４】
上記の例では、ｎ＝６、ｋ＝６６となる。従来の構成である、バスラインとそれに接続されたデータラッチで構成される相展開回路の場合、このインタラインカップリングの個数を減らすことはできない。
【０２９５】
これに対して、本発明では、このインタラインカップリングの個数が０であるため、バスラインの充放電に伴う電力が無くなり、低消費電力化が図れる。
【０２９６】
一般に、パラレルアーキテクチャは回路規模の増大を伴うが（クロック周波数を１／ｎにした場合、同一のスループットを得るためには回路規模はｎ倍必要）、この例で示すデジタルインターフェイス回路の場合、従来のアーキテクチャ（図３９）でトランジスタ数は、約８６００個、パラレル・ドライバ・アーキテクチャ（図４５）で９９００個とそれほど増大を伴わない。
【０２９７】
図５０に、本発明のパラレル・デジタルデータドライバ・アーキテクチャと従来のアーキテクチャにおけるデジタル信号処理回路の消費電力を比較して示す。
【０２９８】
レベル変換回路を除いたロジック部においては、寄生容量の充放電を含めて、５．８ｍＷから、０．８２ｍＷに低減した。
【０２９９】
結局、デジタル信号処理回路の消費電力は、本発明のパラレル・デジタルデータドライバ・アーキテクチャを採用することにより、１パネル当り、１２．５ｍＷから１．０８ｍＷに低減できた。
【０３００】
なお、図４６に示した新規のレベル変換回路（ＬＳ）１エレメントあたり（図４９内の破線内のレベルシフト回路（Ｎｅｗ　Ｌｅｖｅｌ　Ｓｈｉｆｔｅｒ））の電力は、図４９のようになった。新規のレベル変換回路では、データレート２００ＫＨｚで数μＷ程である。図４６に比較して示すように、図４４に示した従来のレベル変換回路では、データレート１００ＫＨｚで２５μＷ、１５０ＫＨｚで３５μＷ、２００ＫＨｚで４７μＷ程度となる。
【０３０１】
また、本発明のアーキテクチャの場合、表示基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）上の最高動作クロックは６２．５ｋＨｚであり、従来の２ＭＨｚと比較して大幅に低減されている。これにより、回路の動作マージンが広がる。
【０３０２】
図４８は、レベル変換機能を持つ２相展開回路（ＳＰＣ）の最高動作周波数（ｍａｘｉｍｕｍ　ｃｌｏｃｋ　ｆｒｅｑｕｅｎｃｙ）を測定したものである。図４８から、入力信号電圧（Ｉｎｐｕｔ　Ｄａｔａ　Ｖｏｌｔａｇｅ）が３Ｖのとき３ＭＨｚ以上で動作していることがわかる。また電源電圧ＶＤＤも、１０Ｖからさらに下げることが可能であることがわかり、このように、電源電圧を下げることで、低消費電力化を図ることができる。
【０３０３】
図４５に示した実施例のＴＦＴ−ＬＣＤの構成について参照してさらに具体的に説明しておくと、基板外部のコントローラ（Ｃｏｎｔｒｏｌｌｅｒ　Ｆｒａｍｅ　Ｍｅｍｏｒｙ）の３．０Ｖインタフェースから並列に供給される１９８ビット（１２５ｋＨｚ）のデジタル映像データ（３Ｖ振幅）は、ガラス基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）上のデータドライバ（Ｄａｔａ　Ｄｒｉｖｅｒ）の端子Ｄ００１からＤ１９８に入力される。Ｄ００１は１ビット入力２ビット出力のシリアル−パラレル変換回路（ＳＰＣ）の入力端子である。シリアル−パラレル変換回路（ＳＰＣ）は、図４６を参照して説明したように、２つのレベルシフタ（Ｌ／Ｓ）と、ラッチ（ＬＡＴ）から構成される。端子Ｄ００２からＤ１９８についても同様であり、それぞれは１ビット入力２ビット出力のシリアル−パラレル変換回路の入力端子である。１ビット入力２ビット出力のシリアル−パラレル変換回路１９８個で、１９８ビット入力３９８ビット出力のシリアル−パラレル変換回路は構成され、３９８ビットの出力ノードは、図のＧ００１からＧ３９６で示されている。これらＧ００１からＧ３９６で示されたノードは、６ビット階調のＤＡコンバータ６６個の入力ノードに接続される。これら６６個のＤＡコンバータの出力はデマルチプレクサアレイ（１　ｔｏ　８　ＤＥＭＵＸ×６６）に入力されてデマルチプレクサアレイの出力Ｓ００１からＳ５２８は、表示エリアのアナログデータラインに接続され、表示エリア部（Ｄｉｓｐｌａｙ　Ａｒｅａ）に配線されたデータバスラインを駆動する。なお、図４５の表示部（Ｄｉｓｐｌａｙ　Ａｒｅａ）は、一例として２．４−インチ、４１Ｋ（１７６×２３４）ピクセルＴＦＴ−ＬＣＤで作製されている。
【０３０４】
図４５において、シリアル−パラレル変換回路（ＳＰＣ）の入力ノードに入力されたデータ（例えばＤ００１）をシリアル−パラレル変換して得られた信号を出力する出力ノード群（例えばＧ００１、Ｇ００２）と、該入力ノード（Ｄ００１）に隣接する入力ノード（例えばＤ００２）に入力されたデータをシリアル−パラレル変換して得られた信号を出力する出力ノード群（Ｇ００３、Ｇ００４）とは、隣接している。また、図４５に示すように、シリアル−パラレル変換回路（ＳＰＣ）を有する回路ユニットはおよそ長方形状にレイアウトされており、長方形の長辺のうち一辺に入力ノード群が設けられ、長辺のもう一辺に出力ノード群が設けられている。
【０３０５】
図４５に示す表示装置は、１９８ビット幅で入力されたデジタルデータを、３９６ビット幅のデジタルデータに変換し、データ線駆動回路であるＤＡＣアレイに入力している。この１９８ビット入力３９６ビット出力のシリアル−パラレル変換回路は、１ビット入力２ビット出力のシリアル−パラレル変換回路（ＳＰＣ）を１９８回路用いて構成されている。また、これら１９８個の１ビット入力２ビット出力のシリアル−パラレル変換回路（ＳＰＣ）は共通に接続されたＣＬＫ、ＸＣＬＫ配線によって同時に駆動されている。このように多数のシリアル−パラレル変換回路を、パラレルに駆動することによって、デジタル信号処理を行うので、この構成を「パラレル・デジタルデータドライバ・アーキテクチャ」と呼ぶ。
【０３０６】
本発明のアーキテクチャの場合、表示基板（Ｇｌａｓｓ　Ｓｕｂｓｔｒａｔｅ）上の最高動作周波数は６２．５ｋＨｚであり、従来の２ＭＨｚと比較して大幅に低減されている。これにより、回路の動作マージンが広がる。さらに、動作周波数が下がっているためＥＭＩノイズが軽減される。さらに加えて、従来例である図３９では、データバスラインが、表示装置の辺の端から端まで配線されているのに対し、本発明である図４５においては、入力端子（パッド）からそれぞれのＳＰＣに配線されるだけである。つまりデータ配線長が極めて短くなっているためＥＭＩノイズは相乗的に低減される。
【０３０７】
従来例の回路の場合（図３９）、６個のデジタルデータバスライン、１つのシフトレジスタ、６６×６のデータレジスタ、１つのロードラッチ、８個の従来型のレベルシフタを備えている。
【０３０８】
図４７は、２相展開回路（ＳＰＣ）の電圧波形の測定結果を示す図であり、３Ｖ振幅の（Ｄ（ｎ））の入力はクロック信号ＣＬＫの立ち上がりと立ち下がりタイミングに同期してサンプルされ、クロック信号ＣＬＫの次の立ち上がりタイミングに同期して１０ＶのデジタルデータＧ（２ｎ−１）、Ｇ（２ｎ）が生成される。クロック信号の周波数は、６２．５ｋＨｚであり、ＬＣＤの実際の駆動周波数である。
【０３０９】
また、前述した図４９を参照すると、本発明では、ソースが共通接続されたｎ−チャネルＴＦＴ対に接続され、交差接続された１対のｐ−チャネルＴＦＴラッチ（図４９参照）を用い（ＣＶＳＬ（Ｃａｓｃｏｄｅ−Ｖｏｌｔａｇｅ　Ｓｗｉｔｃｈ　Ｌｏｇｉｃ）という）ている。
図４９は、新しいレベルシフト（Ｌ／Ｓ）回路と、従来のレベルシフタの電力を対比して示している。１２５ＫＨｚで本発明の回路は、１．４μＷであり、従来例の回路は３０μＷである。従来例の回路では、おおかたの電力消費は、過渡期間に貫通電流として生じる。ｐ−チャネルＴＦＴ、ｎ−チャネルＴＦＴが、ＬＯＷからＨＩＧＨ、ＨＩＧＨからＬＯＷへの遷移時に、＋１０Ｖの電源から、０Ｖグランドにｐ−チャネルＴＦＴ、ｎ−チャネルＴＦＴを介して流れる。
これに対して、本発明に係る新たなレベルシフタ（Ｌ／Ｓ）では、電源からグランドへはほとんど電流は流れない。
【０３１０】
デジタル映像データのインターフェイスのバス幅を広くし、１９８ビット入力を実現することは、従来構成である図３９を参考にして、実現することも可能である。しかしながら、従来構成にある６ビット入力を１９８ビット入力に変更した場合、１９８本のデータバスラインを表示装置の辺の端から端まで配線することとなり、例えば、５ｕｍ幅の配線を１０ｕｍピッチで配線した場合、配線領域の幅だけで約２ｍｍのレイアウト面積を必要としてしまう。
【０３１１】
一方、本発明は、図４５に示すように、１ビット入力２ビット出力のシリアル−パラレル変換回路の入力部にパッドから１対１に配線することで、図４５の水平方向に多数のデータ配線をレイアウトする必要がなく、レイアウト面積の低減が可能となる。図４５の例の場合、レベルシフト機能を含んだ１ビット入力２ビット出力のシリアル−パラレル変換回路（ＳＰＣ）の図の縦方向の高さは、約０．４ｍｍで済んだ。
【０３１２】
図４８では、回路には電源電圧（ＶＤＤ）１０Ｖが供給され、３．０Ｖの入力振幅で３ＭＨｚを超えたクロック周波数範囲で動作している。また、１．５Ｖまたはそれ以下の入力データ電圧でも動作している。これは、コントローラなどの外部のシリコンＩＣに要求される電力を低く抑えている。
【０３１３】
また図５０は、従来型の設計と本発明のアーキテクチャの電力を対比させたものであり、図５０から、従来のアーキテクチャのレベルシフタが６．７ｍＷであるのに対して、本発明のレベル変換回路では、９６％減少させた０．２６ｍＷとされる。これらの電力は、図５０の結果に基づき計、レベルシフタの個数、各アーキテクチャで要求されるデータレートを考慮して計算された。
インターラインカップリングにおける寄生容量を変化（反転）させるために必要な電力を含む論理における電力は、本発明では、０．８２ｍＷであるのに対して、従来型アーキテクチャでは、５．８ｍＷであった。図４５の本発明の回路により全体の電力は、１２．５ｍＷから１．０８ｍＷに減少された。
【０３１４】
低消費デジタルデータドライバ（パラレルデジタルデータドライバ）と、２．４インチ、ポリシリコンＴＦＴ　ＬＣＤ上の３Ｖインタフェース・レベルシフタ（Ｌ／Ｓ）を集積して作成し、ＬＣＤの消費電力を測定した。３０Ｈｚのフレーム周波数で、全体の消費電力は１２ｍＷであった。従来の回路では、２３ｍＷであった。
デジタルデータ転送回路もよって約１．１ｍが消費され、残りの大半がＤＡＣで消費される。
【０３１５】
反射型の表示装置の仕様の一例を示しておく。
表示タイプ：　２．４−インチ、低温ポリシリコンＴＦＴ　反射型ＬＣＤ
ピクセルピッチ：　１７６×ＲＧＢ×２３４
カラーの数：　６ビット（２６２ｋ）
データドライバ周波数：　６２．５ｋＨｚ
消費電力：　１２ｍＷ（２３ｍＷ：　従来型の技術）
入力データ電圧：ＨＩＧＨレベル３Ｖ、ＬＯＷレベル：０Ｖ
電源電圧：　１０Ｖ、０Ｖ、−５Ｖ
【０３１６】
このように、ポリシリコンＴＦＴ　ＬＣＤにおいて、低消費電力化を図るパラレルデジタルデータアーキテクチャが開発され、３Ｖインタフェースのレベルシフタ、６２．５ｋＨｚの低速クロック信号で駆動される１９８個のシリアル・パラレル変換回路を特徴とし、６ｂ　ＤＡＣを集積した２．４−インチ、４１Ｋ（１７６×２３４）ピクセル　ＴＦＴ　ＬＣＤの消費電力は３０−Ｈｚ　フレーム周波数で１２ｍＷであった。この特徴は、本発明のアーキテクチャがモバイルアプリケーション表示システムに好適とされる。以下の文献が参照される（非特許文献１乃至５）。
【０３１７】
【非特許文献１】
Ｔ．Ｎａｋａｍｕｒａ　ｅｔ　ａｌ．，　”Ｌｏｗ　Ｔｅｍｐｅｒａｔｕｒｅ　Ｐｏｌｙ−Ｓｉ　ＴＦＴ−ＬＣＤ　ｗｉｔｈ　Ｉｎｔｅｇｒａｔｅｄ　Ａｎａｌｏｇ　Ｃｉｒｃｕｉｔ，”　Ａｓｉａ　Ｄｉｓｐｌａｙ　’０１　Ｄｉｇｅｓｔ，　ｐｐ１６０３−１６０６（２００１）
【非特許文献２】
Ｙ．Ｍｉｋａｍｉ　ｅｔ　ａｌ．，　”Ａ　５−ｉｎ．　ＳＶＧＡ　ＴＦＴ−ＬＣＤ　ｗｉｔｈ　Ｉｎｔｅｇｒａｔｅｄ　Ｍｕｌｔｉｐｌｅ　ＤＡＣ　Ｕｓｉｎｇ　Ｌｏｗ−Ｔｅｍｐｅｒａｔｕｒｅ　ｐｏｌｙ−Ｓｉ　ＴＦＴｓ，”　Ａｓｉａ　Ｄｉｓｐｌａｙ　’０１　Ｄｉｇｅｓｔ，　ｐｐ１６０７−１６１０（２００１）
【非特許文献３】
Ｈ．Ｋｉｍｕｒａ　ｅｔ　ａｌ．，”Ａ　２．１５　ｉｎｃｈ　ＱＣＩＦ　Ｒｅｆｌｅｃｔｉｖｅ　Ｃｏｌｏｒ　ＴＦＴ−ＬＣＤ　ｗｉｔｈ　Ｄｉｇｉｔａｌ　Ｍｅｍｏｒｙ　ｏｎ　Ｇｌａｓｓ（ＤＭＯＧ），”　ＳＩＤ　’０１　Ｄｉｇｅｓｔ，　ｐｐ２６８−２７１（２００１）
【非特許文献４】
Ｙ．Ｎａｋａｊｉｍａ　ｅｔ　ａｌ．，　”Ａ　３．８　ｉｎｃｈ　ＱＶＧＡ　Ｒｅｆｌｅｃｔｉｖｅ　Ｃｏｌｏｒ　ＬＣＤ　ｗｉｔｈ　Ｉｎｔｅｇｒａｔｅｄ　３ｂ　ＤＡＣ　Ｄｒｉｖｅｒ，”　ＩＳＳＣ２０００　Ｄｉｇｅｓｔ，　ｐｐ１８８−１８９（２０００）
【非特許文献５】
Ｍ．Ａｚａｍｉ　ｅｔ　ａｌ．，”　Ａ　２．６−ｉｎ　ＤＴＶ　ＴＦＴ−ＬＣＤ　ｗｉｔｈ　Ａｒｅａ−Ｒｅｄｕｃｅｄ　ｉｎｔｅｇｒａｔｅｄ　８−ｂｉｔ　Ｄｉｇｉｔａｌ　Ｄａｔａ　Ｄｒｉｖｅｒｓ　Ｕｓｉｎｇ　４００−Ｍｏｂｉｌｉｔｙ　ＣＧＳ　Ｔｅｃｈｎｏｌｏｇｙ，”　ＳＩＤ’９９　Ｄｉｇｅｓｔ，　ｐｐ６−９（１９９９）
【０３１８】
図４５から図４７の実施例では、レベル変換機能を含んだ１ビット入力２ビット出力のシリアル−パラレル変換回路（ＳＰＣ）について述べているが、レベル変換機能は必要に応じて持たせればよく、レベル変換機能が不要な場合には、例えば、図５１に示す１ビット入力２ビット出力のシリアル−パラレル変換回路を用いればよい。
図５１に示す基本構成は、図４６のシリアル−パラレル変換回路（ＳＰＣ）におけるレベル変換機能（ＬＳ）を削除したものであり、論理振幅０−３ＶのデータＤ（ｎ）をサンプリッククロックＣＬＫと、その反転信号ＸＣＬＫでラッチするラッチ回路５１１、５１２を備え、ラッチ回路５１１の出力段に縦続形態に接続され、クロックＸＬＣＫとＣＬＫで前段のラッチ回路の出力をラッチするラッチ回路５１３、５１５を備え、ラッチ回路５１２の出力段に縦続形態に接続され、クロックＣＬＫでラッチ回路５１２の出力をラッチするラッチ回路５１４を備えている。
【０３１９】
また上記実施例では、１ビット入力２ビット出力のシリアル−パラレル変換回路（ＳＰＣ）を多数用いた例を示しているが、例えば１ビット入力６ビット出力のシリアル−パラレル変換回路を用いる場合には、図５２及び図５３に示すような回路を適用してもよい。図５２は、レベルシフト機能を具備しない、２相展開回路であり、論理振幅０−２．５ＶのデータＤ（ｎ）を共通に入力とするＣＭＯＳインバータ（電源電圧＝４．０Ｖ）を２つ備え、一方のＣＭＯＳインバータの出力をインバータで反転した信号を、クロックドインバータとフリップフロップ（インバータとクロックドインバータ）よりなるラッチを２段備えたマスタースレーブラッチとラッチ（クロックドインバータとフリップフロップ）でサンプルして（サンプリングクロックＳＭＰとＸＳＭＰは相補のクロック信号）、ＤＡＴＡＯＤＤを出力し、他方のＣＭＯＳインバータの出力をインバータで反転した信号を、クロックドインバータとフリップフロップ（インバータとクロックドインバータ）よりなるマスタースレーブラッチでサンプルしてＤＡＴＡＥＶＥＮを出力する。
【０３２０】
図５３を参照すると、図５２の２相展開回路において、ＤＡＴＡＯＤＤが伝達されるノード（Ａ）をインバータ８２、８３で遅延させ、入力データ（ＤＡＴＡ）の周波数を６分周した信号ＤＣＬの立ち上がりで出力するラッチ（クロックドインバータ５２、インバータ５３、クロックドインバータ５４）と、ラッチの出力を反転した信号をＤ１として出力するインバータ５５を備えている。
【０３２１】
ノードＡの電位を、信号ＸＳＭＰの立ち下がりで取り込み、信号ＳＭＰの立ち上がりで出力する第１のマスタースレーブ型のラッチ（クロックドインバータ３０、インバータ３１、クロックドインバータ３２、クロックドインバータ３３、インバータ３４、クロックドインバータ３５）と、クロックドインバータ３３の出力（ノードＣ）を信号ＸＳＭＰの立ち下がりで取り込み、信号ＳＭＰの立ち上がりで出力する第２のマスタースレーブ型のラッチ（クロックドインバータ３６、インバータ３７、クロックドインバータ３８、クロックドインバータ３９（出力はノードＥ）、インバータ４０、クロックドインバータ４１）を備え、第１のマスタースレーブ型のラッチのインバータ３４の出力をインバータ４２で反転した信号を、信号ＤＣＬの立ち上がりで出力するラッチ（クロックドインバータ４８、インバータ４９、クロックドインバータ５０）と、このラッチの出力を反転した信号をＤ２として出力するインバータ５１を備えている。第２のマスタースレーブ型のラッチのインバータ４０の出力をインバータ４３で反転した信号を、信号ＤＣＬの立ち上がりで出力するラッチ（クロックドインバータ４４、インバータ４５、クロックドインバータ４６）と、このラッチの出力を反転した信号をＤ３として出力するインバータ４７を備えている。
【０３２２】
ＤＡＴＡＥＶＥＮ系は、２相展開回路において、ＤＡＴＡＥＶＥＮ信号が伝達されるノード（Ｆ）をインバータ８４、８５で遅延させ、入力データを６分周した信号ＤＣＬの立ち上がりで出力するラッチ（クロックドインバータ７８、インバータ７９、クロックドインバータ８０）と、ラッチの出力を反転した信号をＤ０として出力するインバータ８１を備えている。
【０３２３】
ノードＦの電位を、信号ＸＳＭＰの立ち下がりで取り込み、信号ＳＭＰの立ち上がりで出力する第３のマスタースレーブ型のラッチ（クロックドインバータ５６、インバータ５７、クロックドインバータ５８、クロックドインバータ５９、インバータ６０、クロックドインバータ６１）と、クロックドインバータ５９の出力（ノードＨ）を信号ＸＳＭＰの立ち下がりで取り込み、信号ＳＭＰの立ち上がりで出力する第４のマスタースレーブ型のラッチ（クロックドインバータ６２、インバータ６３、クロックドインバータ６４、クロックドインバータ６５（出力はノードＪ）、インバータ６６、クロックドインバータ６７）を備え、第３のマスタースレーブ型のラッチのインバータ６０の出力をインバータ６８で反転した信号を、信号ＤＣＬの立ち上がりで出力するラッチ（クロックドインバータ７４、インバータ７５、クロックドインバータ７６）と、このラッチの出力を反転した信号をＤ２として出力するインバータ７７を備えている。第４のマスタースレーブ型のラッチのインバータ６６の出力をインバータ６９で反転した信号を、信号ＤＣＬの立ち上がりで出力するラッチ（クロックドインバータ７０、インバータ７１、クロックドインバータ７２）と、このラッチの出力を反転した信号をＤ４として出力するインバータ７３を備えている。
【０３２４】
６相展開回路の動作の概略を説明すると、入力データＤＡＴＡからＤＡＴＡＯＤＤ（ノードＡ）、ＤＡＴＡＥＶＥＮ（Ｆ）が生成され、ＤＡＴＡＯＤＤのパスのノードＣ、Ｅで、ノードＦの信号がサンプリングパルス信号ＳＭＰの１サイクル、２サイクル分遅延され、入力データＤＡＴＡの６分周クロックであるＤＣＬの立ち上がり（入力データＤＡＴＡの７が入力されるタイミング）で、ノードＡ、Ｃ、ＥのデータがＤ１、Ｄ３、Ｄ５としてパラレル出力される。ＤＡＴＡＥＶＥＮのパスのノードＨ、Ｊで、ノードＦの信号がサンプリングパルス信号ＳＭＰの１サイクル、２サイクル分遅延され、入力データＤＡＴＡの６分周クロックであるＤＣＬの立ち上がり（入力データＤＡＴＡの７が入力されるタイミング）で、ノードＦ、Ｈ、ＪのデータがＤ０、Ｄ２、Ｄ４としてパラレル出力される。
【０３２５】
以上、本発明を上記各実施例に即して説明したが、本発明は上記実施例の構成にのみ限定されるものでなく、特許請求の範囲の請求項の発明の範囲内で当業者であればなし得るであろう各種変形、修正を含むことは勿論である。例えば、本発明は、プリンタヘッド、液晶ドライバＩＣ、メモリ等、入力されたデータをシリアル−パラレル変換する半導体装置に適用した例を含むことは勿論である。
【０３２６】
【発明の効果】
以上、説明したように、本発明によれば下記記載の効果を奏する。
【０３２７】
本発明の第１の効果は、ＤＡＣ回路を内蔵した駆動回路一体型表示装置と共にメモリ内蔵コントローラＩＣを備えたことにより、ＩＣコストの大幅な低減を可能としている、ということである。
【０３２８】
本発明の第２の効果は、メモリ内蔵コントローラＩＣからのバス幅を太くすることによって、読み出し周波数を低下し、インタフェース回路の消費電力が低下することである。また、配線同士の交差点の数を減らすことによって、インタフェース回路の消費電力が低下することである。
【０３２９】
本発明の第３の効果は、ＥＭＩの影響が無視できることである。その理由は、太いバスの利用によって、データ処理の周波数が低下しているためである。処理周波数が低下すると、ＥＭＩノイズは激減するためＥＭＩの影響は無視できる。さらに、データ配線長が短くなるためＥＭＩノイズは相乗的に小さくなる。
【０３３０】
本発明の第４の効果は、基板内を、同一のプロセスで作成できる、ということである。従来、各種回路素子を形成した場合、各回路群で使用する電圧に合わせて各種プロセスが使用されていた。本発明では、処理する周波数が低いために、最も高電圧を必要とする回路群に合わせた単一のプロセスですべての回路群を作成しても問題なく動作する。基板内を、同一のプロセスで作成できるということは、言い換えれば、基板上に形成されたトランジスタのゲート絶縁膜はすべて同一構造で、その膜厚はプロセスばらつきの範囲内で等しくすることができる。すなわち、トランジスタの閾値電圧が高電圧用に高く設定されていても、周波数が低いため低電圧駆動が可能である。
【０３３１】
本発明の第５の効果は、表示装置の信頼性を向上する、ということである。その理由は、本発明においては、回路の動作周波数を低く抑えることができるためである。動作周波数が低いと各素子にかかるストレスが小さくなるため、信頼性が向上する。単純な見積もりでは、周波数の低下割合と連続使用可能時間の上昇割合は比例関係にある。すなわち、周波数が低下すると信頼性が向上する。また、前述のＥＭＩの影響がない点も信頼性の向上に大きな役割を果たす。
【０３３２】
本発明の第６の効果は、電圧―電流変換回路を備え、電流駆動素子を駆動することができる、ということである。これらの効果により、高精細・多階調・低コスト・低消費電力ディスプレイ装置を実現できる。
【０３３３】
本発明の第７の効果は、シリアル−パラレル変換回路のレイアウト面積が小さくなることである。これは、１ビット入力のシリアル−パラレル変換回路複数個配置することで多ビット入力多ビット出力のシリアル−パラレル変換回路を実現するため、パッドから個々の１ビット入力のシリアル−パラレル変換回路に１対１に配線を設けるだけで済み、従来のように多ビット入力多ビット出力のシリアル−パラレル変換回路レイアウト領域全体に渡って多数本のデータバス配線を引き回す必要が無いからである。
【図面の簡単な説明】
【図１】本発明の第１の実施例の表示装置の構成を示す図である。
【図２】本発明の第１の実施例の表示装置のタイミング動作を説明するための図である。
【図３】メモリ内蔵ドライバＩＣ並びにメモリ内蔵コントローラＩＣに対して、内蔵するメモリ容量とＩＣコストの関係を示す図である。
【図４】読み出し周波数とインタフェース回路消費電力の関係を示す図である。
【図５】本発明の第２の実施例の表示装置の構成を示す図である。
【図６】本発明の第３の実施例の表示装置の構成を示す図である。
【図７】本発明の第４の実施例の表示装置の構成を示す図である。
【図８】本発明の第５の実施例の表示装置の構成を示す図である。
【図９】本発明の第５の実施例の表示装置のタイミング動作を説明するための図である。
【図１０】本発明の第６の実施例の表示装置の構成を示す図である。
【図１１】本発明の第７の実施例の表示装置の構成を示す図である。
【図１２】本発明の第７の実施例の表示装置のタイミング動作を説明するための図である。
【図１３】本発明の第８の実施例の表示装置の構成を示す図である。
【図１４】本発明の第９の実施例の表示装置の構成を示す図である。
【図１５】本発明の第１０の実施例の表示装置の構成を示す図である。
【図１６】本発明の第１０の実施例の表示装置のタイミング動作を説明するための図である。
【図１７】本発明の第１１の実施例の表示装置の構成を示す図である。
【図１８】本発明の第１２の実施例の表示装置の構成を示す図である。
【図１９】本発明の第１２の実施例の表示装置のタイミング動作を説明するための図である。
【図２０】本発明の第１３の実施例の表示装置の構成を示す図である。
【図２１】本発明の第１４の実施例の表示装置の構成を示す図である。
【図２２】本発明の第１５の実施例の表示装置の構成を示す図である。
【図２３】本発明の第１６の実施例の表示装置の構成を示す図である。
【図２４】本発明の第１６の実施例の表示装置のタイミング動作を説明するための図である。
【図２５】本発明の第１７の実施例の表示装置の構成を示す図である。
【図２６】本発明の第１８の実施例の表示装置の構成を示す図である。
【図２７】本発明の第１８の実施例の表示装置のタイミング動作を説明するための図である。
【図２８】本発明の第１９の実施例の表示装置の構成を示す図である。
【図２９】本発明の第２０の実施例の表示装置の構成を示す図である。
【図３０】本発明の第２１の実施例の表示装置の構成を示す図である。
【図３１】本発明の第２１の実施例の表示装置のタイミング動作を説明するための図である。
【図３２】本発明の第２２の実施例の表示装置の構成を示す図である。
【図３３】本発明の第２３の実施例の表示装置の構成を示す図である。
【図３４】本発明の第２４の実施例の表示装置の構成を示す図である。
【図３５】本発明の実施例で用いられる表示パネル基板の作成の主要工程を説明するための断面図である。
【図３６】本発明の実施例で用いられる表示パネル基板の作成の主要工程を説明するための断面図である。
【図３７】従来の駆動回路一体型の液晶表示装置を用いたディスプレイシステムの概要を示す図である。
【図３８】従来のＤＡＣ回路内蔵の駆動回路一体型液晶表示装置を用いたディスプレイシステムの概要を示す図である。
【図３９】比較例として従来のアーキテクチャを適用した表示装置の構成を示す図である。
【図４０】図３９のシフトレジスタの回路構成を示す図である。
【図４１】図３９の６ビットデータレジスタとこれに接続されるデジタルデータバスラインの回路構成を示す図である。
【図４２】図３９の６×６６ロードラッチの回路構成を示す図である。
【図４３】図３９のシフトレジスタ回路およびデジタルデータバスラインに入力される信号のタイミングチャートである。
【図４４】従来のレベル変換回路の回路構成を示す図である。
【図４５】本発明の実施例の表示装置の構成を示すブロック図である。
【図４６】図４５に示した本発明の実施例におけるレベル変換機能つき１−ｔｏ−２シリアルパラレル変換回路の回路構成を示す図である。
【図４７】図４６に示した１−ｔｏ−２シリアルパラレル変換回路のタイミング波形を示すタイミングチャート図である。
【図４８】図４６に示した１−ｔｏ−２シリアルパラレル変換回路の最高動作周波数の測定結果を示したグラフである。
【図４９】図４６内に含まれるレベル変換部と図４４に示した従来のレベル変換回路との消費電力を比較したグラフである。
【図５０】図３９に示した表示装置と図４５に示した表示装置の、表示基板上に集積されたデジタル信号処理部の消費電力を比較したものである。
【図５１】１ビット入力２ビット出力シリアル−パラレル変換回路の回路構成を示す図である。
【図５２】１ビット入力６ビット出力のシリアル−パラレル変換回路の回路構成を示す図である。
【図５３】１ビット入力６ビット出力のシリアル−パラレル変換回路の回路構成を示す図である。
【符号の説明】
１０　ガラス基板
１１　酸化シリコン膜
１２　アモルファスシリコン
１３　酸化シリコン膜
１４　フォトレジスト
１５　酸化シリコン膜
１６　マイクロクリスタルシリコン（μ−ｃ−Ｓｉ）
１７　タングステンシリサイド（ＷＳｉ）１７
１８　フォトレジスト
１９　酸化シリコン膜／窒化シリコン膜
２０　金属（アルミニウムとチタン）
２１　窒化シリコン膜
２２　画素電極（ＩＴＯ）
３０、３２、３３、３５、３６、３８、３９、４１、４８、５０、５２、５４、５６、５８　クロックドインバータ
３１、３４、３７、４０、４２、４３、４９、５１、５３、５５、５７　インバータ
６１、６２、６３、６５、６７、７０、７２、７４、７６、７８、８０　クロックドインバータ
５７、６０、６３、６６、６８、６９、７１、７３、７５、７７、７９、８１、８２、８３、８４、８５　インバータ
１０１　表示デバイス基板
１０２　コントローラＩＣ
１０３　システム側回路基板
１０４　レベルシフタ
１０５　ラッチ回路
１０６　ＤＡＣ回路
１０７　セレクタ回路
１０８　レベルシフタ／タイミングバッファ
１０９　走査回路
１１０　表示部
１１１　メモリ
１１２　出力バッファ
１１３　コントローラ
１１４　インタフェース回路
４０１　タイミングバッファ
５１１〜５１５　ラッチ
７０１　タイミングバッファ
８０１　電圧−電流変換回路／電流出力バッファ
１００１　デコーダ
１００２　電流出力バッファ
１８０１　シリアル／パラレル変換回路
３５０１　走査回路／データレジスタ
３５０２　ＤＡＣ
３５０３　レベルシフタ
３５０４　走査回路
３５０５　アナログスイッチ
３５０６　走査回路
３５０７　データレジスタ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a display device used for a projector, a notebook PC, a monitor, a mobile phone, a PDA, and the like, and particularly to a voltage-driven display device such as a liquid crystal display device and a current-driven display device.
The present invention also relates to a semiconductor device, and more particularly to a semiconductor device having driven elements formed in an array, for example, a voltage-driven display such as a liquid crystal display device used for a projector, a notebook PC, a monitor, a mobile phone, a PDA, and the like. The present invention relates to a device, a current driven display device, a memory device, an optical printer head, and the like.
[0002]
[Prior art]
With the development of the multimedia age, display devices have been reduced from small ones used in viewfinders of projector devices and video cameras and mobile phones to display panels of automobile televisions and navigation systems, PDA (Personal). Digital assistants and portable computers such as pocket PCs (Personal Computers) and the like, and large-sized ones used for notebook PCs, monitors, and the like, are rapidly spreading. Among these display devices, the liquid crystal display device is currently applied to the widest product group. In particular, an active matrix liquid crystal display device driven by a thin film transistor (Thin Film Transistor (hereinafter, abbreviated as “TFT”) or the like) has higher resolution and higher image quality than a simple matrix liquid crystal display device. It has become the mainstream of liquid crystal display devices. TFTs are classified into amorphous silicon TFTs and polysilicon TFTs depending on the difference in the semiconductor material used.
[0003]
Since an amorphous silicon TFT does not require a high-temperature process, a panel can be manufactured using a substrate such as glass.
[0004]
Conventionally, a polysilicon TFT requires an expensive quartz substrate due to a high-temperature process, and has been limited to a small and high-value-added panel. In recent years, due to advances in laser annealing and other technologies, a precursor film is formed by low-pressure (LP) CVD, plasma (P) CVD, sputtering, etc., which is annealed with a laser to be polycrystallized, and a glass substrate can be used. A technology capable of forming a polysilicon TFT at an extremely low temperature has been developed, and display panels for medium-sized and notebook PCs are also manufactured using the polysilicon TFT.
[0005]
The mobility of the polysilicon TFT is one or more digits higher than that of the amorphous silicon TFT, and the current driving capability is high.
[0006]
When a liquid crystal display device is formed using a polysilicon TFT, the peripheral circuit can be formed on the same substrate as the pixels because the current driving capability of the polysilicon TFT is high. Reduction and size reduction are possible, and mounting cost can be reduced.
[0007]
Such a liquid crystal display device in which peripheral circuits are integrated on the same substrate is called a "drive circuit integrated liquid crystal display device".
[0008]
The liquid crystal display device integrated with a driving circuit includes, as peripheral circuits, a data driver that drives a data line connected to the source terminal of the pixel TFT, and a gate driver that drives a gate line connected to the gate terminal of the pixel TFT. This form is the most widespread, and is widely used in liquid crystal projectors that require a small, high-definition liquid crystal display device, portable notebook personal computers that require a smaller frame, and the like.
[0009]
Among conventional liquid crystal display devices, in a drive device that does not integrate a drive circuit, a gate driver LSI (Large Scale Integrated Circuit) chip group and a gate driver LSI chip group, a controller, a DC-DC converter, and the like are formed by a TCP (Tape Carrier Package). And on a flexible board or a connection circuit board. In this structure, it is unavoidable to increase the definition and increase the number of gradations, to complicate the mounting, and to increase the frame. At the same time, the problem of EMI (Electro Magnetic Interference: radio interference) increases due to the increase in frequency. Therefore, much effort is paid to noise measures such as strengthening the ground wire of the printed circuit board used, changing the arrangement of component materials of the printed circuit board, changing the wiring layout, adding an EMI filter, and improving the interface.
[0010]
On the other hand, a drive circuit integrated type in which peripheral circuits are integrated on the same substrate is easy to mount, and the size of the picture frame hardly changes even if the definition and the number of gradations increase. Therefore, it is very effective for portable use.
[0011]
FIG. 37 is a diagram showing an outline of a display system of a conventional general driving circuit integrated type liquid crystal display device. Referring to FIG. 37, in the conventional driving circuit integrated liquid crystal display device, an active matrix display area 110 in which pixels in M rows and N columns are arranged in a matrix and a scanning circuit (scanning line (gate line) ) Drive circuit) 109, a column-direction scanning circuit (data line driving circuit) 3504, an analog switch 3505, a level shifter 3503, and the like are integrally formed on the display device substrate 101 by a polysilicon TFT. .
[0012]
The controller 113, the memory 111, the digital / analog conversion circuit (DAC circuit) 3502, the scanning circuit / data register 3501, the interface circuit 114, and the like are single crystal silicon circuits (LSI) and are formed outside the display device substrate 101. .
[0013]
The analog switches 3505 have the same number of outputs as the number N of data lines in the column direction of the active matrix display area 110.
[0014]
Further, among conventional liquid crystal display devices integrated with a drive circuit, there is a device of a type in which a more complicated circuit such as a DAC circuit is built. FIG. 38 is a diagram showing an outline of a display system of a conventional liquid crystal display device with a built-in DAC circuit. In a conventional liquid crystal display device with a built-in DAC circuit, an active matrix display region 110 in which pixels of M rows and N columns are arranged in a matrix and similar to the device of FIG. The following circuits are formed on the display device substrate 101 in addition to the scanning circuit 109 and the column-directional scanning circuit 3506. That is, the data register 3507, the latch circuit 105, the DAC circuit 106, the selector circuit 107, the level shifter / timing buffer 108, the level shifter, and the like are formed on the display device substrate 101.
[0015]
In this configuration, the controller IC with a built-in memory does not include a DAC circuit, and is composed of a digital circuit including the memory 111, the output buffer 112, and the controller 113. As a result, since the IC can be manufactured without using the process for the analog circuit, the price of the IC can be lower than that of the above-described driver IC with a built-in memory.
[0016]
The above-described liquid crystal display device is thin and lightweight, and consumes less power than a CRT (Cathode Ray Tube) tube. Utilizing such features, the liquid crystal display device is mounted on a portable information processing device.
[0017]
With the rapid spread of mobile terminals such as mobile phones, PDAs, and mobile PCs in recent years, needs for displays for mobile use have been further increased. In the display of such a mobile terminal, for example, there are the following requirements.
[0018]
(1) To improve portability, the area other than the display unit is reduced.
[0019]
(2) In a portable terminal, a battery drive system is generally adopted, and low power consumption is desired in order to extend the duration of battery drive by one charge.
[0020]
(3) Since the spread of portable terminals requires low price, it is desired that portable displays have low cost.
[0021]
It is expected that these requirements can be realized by a liquid crystal display device integrated with a driving circuit, an organic EL (electroluminescence) device, or the like.
[0022]
As a device for measuring low power consumption, miniaturization, and high definition of a liquid crystal display with a built-in peripheral circuit, for example, Japanese Patent Application Laid-Open No. 11-202290 discloses a signal side peripheral circuit for driving liquid crystal on a TFT substrate and a scanning device. An image memory for storing at least one line of display data written from the CPU through the connection portion, the connection portion having a relay bus for transferring display data to the signal wiring and the side peripheral circuit; An apparatus is disclosed in which an image memory chip having a circuit formed thereon is mounted on a liquid crystal display device, and display data from the image memory chip is transferred in parallel with a low-speed clock every line.
[0023]
[Problems to be solved by the invention]
The problems of the above-described conventional display device will be described.
[0024]
The first problem is that the price and power consumption of the driver IC increase with the increase in the definition and the number of gray scales of the display.
[0025]
The reason is that the display data of all the pixels must be serially transferred at high speed to the liquid crystal module every frame time. As the definition becomes higher and the number of pixels increases, the transfer rate at this time increases. As a result of the high-speed transfer, high speed is also required of the driver IC, a through current or the like is generated in a large number of CMOSs constituting the circuit element, and power consumption increases with an increase in operation speed. Further, the price of an IC that operates at a high speed increases. When the number of gradations increases, the circuit configuration becomes complicated and the transfer speed further increases, which leads to further increase in power consumption and cost. Further, as described above, in an IC incorporating a DAC circuit or the like, it is necessary to use different kinds of processes together, which further increases the cost.
[0026]
A second problem is that the number of pixels and the number of gradations are limited due to the necessity of reducing the power consumption and the price of the entire system.
[0027]
The reason is that the power consumption of the driver IC increases when the number of pixels or the number of gradations increases as described above.
[0028]
A third problem is that there is a problem in reliability due to high frequency operation.
[0029]
The reason is that when a low-temperature polysilicon TFT is operated at a high frequency, a change in TFT characteristics is likely to occur.
[0030]
A fourth problem is that since different voltages are used for each circuit block on the display panel substrate, it is necessary to use a process corresponding to a plurality of voltages together.
[0031]
Furthermore, when the frequency of the input signal increases, the problem of EMI is large. The reason is that the source driver IC is driven with the input frequency as it is. As a result, spurious (spurious) radio waves generated from the rectangular wave of the drive circuit increase, and EMI noise also increases. Therefore, as described above, a great deal of effort has been paid to various EMI measures.
[0032]
On the other hand, if the EMI noise level is sufficiently low, various reference tests can be easily passed, and not only reliability can be improved, but also costs related to EMI-related tests can be reduced.
[0033]
Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a display device which realizes high-definition, multi-gradation display at low cost, low power consumption. is there.
[0034]
Another object of the present invention is to provide a display device having improved reliability.
[0035]
Still another object of the present invention is to provide a display device for suppressing the influence of EMI.
[0036]
It is still another object of the present invention to provide a drive circuit integrated display device that can drive all circuits by a process for one type of voltage without using a process for a plurality of voltages. Still another object of the present invention is to provide a semiconductor device and a display device in which the layout area of a serial-parallel conversion circuit is reduced.
[0037]
[Means for Solving the Problems]
A display device according to the present invention that achieves the above object has, in one aspect (side surface), a display panel unit having a display unit in which pixel groups are arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines. A scanning line driving circuit for sequentially applying voltages to the plurality of scanning lines, and a data line driving circuit for receiving display data supplied from a host device and applying a signal corresponding to the display data to the plurality of data lines A display memory that stores display data, an output buffer that reads data from the display memory and outputs the read data to the display panel unit, and controls the display memory and the output buffer to communicate with the host device. A controller device having a controller that controls communication and control is provided outside the display panel unit, and the display panel unit includes the controller device. A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that constitutes a part of a data line driving circuit and converts display data of a digital signal transferred from the controller device into an analog signal; The width of the bus for data transfer to and from the display panel unit is such that more bit data is transferred in parallel per transfer than the bus between the controller and the host device. In the present invention, by increasing the bus width of the data transfer, the operating frequency of the data line driving circuit is reduced, whereby the transistor elements constituting the peripheral circuit including the data line driving circuit and the scanning line driving circuit are: The gate insulating film of the transistor element of the peripheral circuit is formed by the same process as a TFT (Thin Film Transistor) forming a pixel switch formed in the display panel portion. The thickness is set to be the same as the thickness of the gate insulating film.
In other words, the data line driving circuit, the scanning line driving circuit, and the gate insulating film of each transistor forming the display section have the same structure, and their film thicknesses are equal within the range of process variation.
[0038]
In another aspect of the present invention, the display panel unit includes a display memory for storing display data, and a digital / analog conversion circuit (referred to as a “DAC circuit”) for converting display data of a digital signal into an analog signal. ing. In the present invention, the DAC circuit and the display memory are formed by the same process as a TFT (Thin Film Transistor) forming process of the pixel portion.
In other words, the DAC circuit, the display memory, and the gate insulating film of each transistor constituting the pixel portion have the same structure, and their film thicknesses are equal within the range of process variation.
[0039]
In the present invention, the display panel unit includes a selector circuit which receives an output of the DAC circuit as an input and has an output connected to a data line group. In the present invention, the display panel section has a level shifter for level-shifting a signal amplitude defined by a power supply voltage of the controller IC to a high voltage on the display panel section side. In the present invention, the display panel unit includes a serial / parallel conversion circuit that converts serial data into parallel data, and the DAC circuit is supplied with data that has been converted into parallel data by the serial / parallel conversion circuit. You. As will be apparent to those skilled in the art from the following description of the embodiments, the above object is also attained by the present invention described in each claim.
Further, in another aspect, the serial-parallel conversion circuit function is achieved by using a plurality of 1-bit input serial-parallel conversion circuits and driving them simultaneously.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described. In a preferred embodiment of the display device according to the present invention, the display unit (110 in FIG. 1) having pixel portions arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines; A scanning line driving circuit (109 in FIG. 1) for sequentially applying a voltage to the scanning lines, and a data line for receiving display data supplied from a host device and applying a signal corresponding to the display data to the plurality of data lines. A display circuit having a drive circuit and a display memory (111 in FIG. 1) for storing display data corresponding to the pixel portion, in addition to a display device substrate (101 in FIG. 1), and reading data from the display memory. The output buffer (112 in FIG. 1) for outputting to the display device substrate (101 in FIG. 1), the display memory (111 in FIG. 1) and the output buffer (112 in FIG. 1) are controlled to A controller IC (113 in FIG. 1) having a controller (113 in FIG. 1) for controlling communication and control, a part of a data line driving circuit is formed on a display device substrate (101 in FIG. 1), A DAC (digital-to-analog conversion) circuit (106 in FIG. 1) for converting signal display data into an analog signal is provided, and a controller IC (102 in FIG. 1) and a data line on a display device substrate (101 in FIG. 1) are provided. The width of the bus for data transfer between the drive circuit and the bus between the controller (113 in FIG. 1) and the host device (114 in FIG. 1) allows more bit data to be transferred in one transfer. It is configured to be transferred in parallel.
[0041]
More specifically, in a preferred embodiment of the display device according to the present invention, the display device substrate (101 in FIG. 1) is provided at an intersection of a plurality of data lines (N lines) and a plurality of scanning lines (M lines). 1 is provided with a display unit (110 in FIG. 1) having a pixel group arranged in M rows and N columns in a matrix, and the display data of B-bit gradation is equivalent to (M × N) pixels (that is, (M × N × B) bits), a display memory (111 in FIG. 1), an output buffer (112 in FIG. 1) for reading data from the display memory (111 in FIG. 1) and outputting the data to the display panel substrate (101 in FIG. 1). A controller IC (102 in FIG. 1) having a controller (113 in FIG. 1) that controls a display memory (111 in FIG. 1) and an output buffer (112 in FIG. 1), and performs communication and control with a higher-level device. The display device substrate (Figure Is provided separately from the 101).
[0042]
In the controller IC (102 in FIG. 1), the output buffer (112 in FIG. 1) converts (N × B) bits corresponding to one row of (M × N × B) bits of the memory into the block division number S {(N × B) / S}.
[0043]
From the output buffer (112 in FIG. 1) of the controller IC (102 in FIG. 1), via a {(N × B) / S} bit-width data bus to the display device substrate (101 in FIG. 1), {(N × B) / S} In one horizontal period, the display data for one line is transferred in the above-mentioned block division number S times in one horizontal period.
[0044]
On the display device substrate (101 in FIG. 1), a level shifter (104 in FIG. 1) for level-shifting the amplitude of the signal received from the data bus to a signal having a higher amplitude and outputting the signal, and latching the output of the level shifter A latch circuit (105 in FIG. 1), a DAC circuit (106 in FIG. 1) that inputs an output of B bits of the latch circuit and outputs an analog signal, and an input of the output of the DAC circuit and N columns of the display unit A data line driving circuit including a selector having the same N outputs (107 in FIG. 1), a scanning line driving circuit (109 in FIG. 1) for sequentially applying voltages to the plurality of scanning lines (gate lines), It has. The level shifters (104 in FIG. 1) and the latch circuits (105 in FIG. 1) are all arranged {(N × B) / S}, and the DAC circuits (106 in FIG. 1) are arranged (N / S). , The selector circuit (107 in FIG. 1) receives the outputs of the (N / S) DAC circuits (106 in FIG. 1), and, based on the input selector control signal, generates one for each output of the DAC circuits. The data signals are sequentially supplied to the S data lines in the time period obtained by dividing the horizontal period by the block division number S, and the controller of the controller IC (113 in FIG. 1) operates on the display device substrate (FIG. 1). 101) supplies a clock signal to the level shifter timing buffer (108 in FIG. 1), and the latch clock signal and the selector control signal which are boosted and output by the level shifter timing buffer (108 in FIG. 1) are Serial latch circuit (105 in FIG. 1) and the selector circuit is supplied to (107 of FIG. 1).
[0045]
In one embodiment of the present invention, a transistor element constituting a peripheral circuit including a data line driving circuit and a scanning line driving circuit formed on a display device substrate is a TFT (Thin) forming a pixel switch formed in a display portion. It is formed by the same process as that of the Film Transistor, and is preferably made of a polycrystalline silicon TFT.
That is, the data line drive circuit, the scan line drive circuit, and the gate insulating film of each of the transistors forming the display section have the same structure, and their film thicknesses are set to be equal within the range of process variation.
[0046]
In the embodiment of the present invention, a configuration including a scanning line driving circuit (109 in FIG. 5) and a level shifter / timing buffer (108 in FIG. 5) for supplying a clock to the data line driving circuit is provided on both sides of the display unit. Is also good.
[0047]
In the embodiment of the present invention, the positions of the latch circuit and the level shifter formed on the display device substrate (101) and constituting the data line driving circuit may be switched (see FIG. 6).
[0048]
In the embodiment of the present invention, the amplitude of the signal of the controller IC (102 of FIG. 7) and the amplitude of the signal of the display device substrate (101 of FIG. 7) may be the same. In the display device substrate (101 in FIG. 7), the level shift circuit is omitted.
[0049]
In the embodiment of the present invention, in order to drive a current drive type pixel element, a current corresponding to the gray scale of display data is generated, and a voltage-current conversion circuit / current output buffer (current output buffer) for supplying a current to a data line is provided. 8 and 15, 801), and a configuration including a decoder and a current output buffer (1001, 1002 in FIGS. 10 and 17).
[0050]
In another embodiment of the present invention, (N × B) output buffers (112 in FIGS. 11 and 13) of the controller IC (102 in FIGS. 11 and 29) are arranged, and (N × B) B) One line of display data is transferred once in one horizontal period to the display device substrate (101 in FIGS. 11 and 13) via a data bus having a bit width in units of (N × B) bits. Then, a configuration may be adopted in which N DAC circuits (106 in FIGS. 11 and 13) are provided corresponding to the data lines. In such a configuration, the amplitude of the signal of the controller IC (102 of FIGS. 14 and 29) may be the same as the amplitude of the signal of the display device substrate (101 of FIGS. 14 and 29). In the display device substrate (101 in FIG. 14), the level shift circuit is omitted.
[0051]
In the embodiment of the present invention, a serial / parallel conversion circuit (FIG. 18, FIG. 20 to FIG. 23, FIG. 25, FIG. 26, FIG. 28 to FIG. 28) for converting serial data into parallel data is provided on the display device substrate (101). 30 and 1801) of FIGS. 32 to 34, and the DAC circuit may be configured to be supplied with data converted in parallel by the serial / parallel conversion circuit. By supplying data converted into parallel bits by the serial / parallel conversion circuit (a signal obtained by latching the converted data and / or a level-shifted signal) to an input of the DAC circuit, the operating frequency of the DAC circuit can be reduced.
This multi-bit input multi-bit output serial-parallel converter is constituted by a plurality of 1-bit input serial-parallel converters, and these plural 1-bit input serial-parallel converters are driven simultaneously.
[0052]
In another embodiment, the display device according to the present invention includes a DAC circuit (106 in FIG. 33) that converts display data of a digital signal into an analog signal in a display panel unit (101 in FIGS. 33 and 34). A display memory (111 in FIGS. 33 and 34) for storing display data is provided, and the DAC circuit and the display memory are formed by the same process as a TFT (Thin Film Transistor) forming process of a pixel portion.
In other words, the DAC circuit, the display memory, and the gate insulating film of each transistor constituting the pixel portion have the same structure, and their film thicknesses are equal within the range of process variation.
[0053]
More specifically, in another embodiment of the display device according to the present invention, the display device substrate (101 in FIG. 33) includes an intersection of a plurality of data lines (N lines) and a plurality of scanning lines (M lines). A display unit (110 in FIG. 33) having a pixel group arranged in M rows and N columns in a matrix, and display data of B-bit gradation for (M × N) pixels (that is, (M × N × B) ) Bits), a memory for storing (111 in FIG. 33), an output buffer for reading data from the display memory and outputting it to the display panel substrate side (112 in FIG. 33), a display memory (111 in FIG. 33) and an output buffer (111 in FIG. 33). A controller (113 in FIG. 33) that controls (112) in FIG. 33 and communicates with and controls the higher-level device is provided on the same substrate. The output buffer (112 in FIG. 33) stores (N × B) bits corresponding to one row in (M × N × B) bits of the memory (111 in FIG. 33) by the number of block division numbers S. And {(N × B) / (P × S)} divided by P phase.
[0054]
The display device substrate (101 in FIG. 33) includes a serial-parallel conversion circuit (1801 in FIG. 33) that serially receives the output of the output buffer (112 in FIG. 33), expands the output into a P-phase, and outputs the P-phase. A latch circuit (105 in FIG. 33) that latches the output of the conversion circuit (1801 in FIG. 33), a DAC circuit (106 in FIG. 33) that receives the B-bit output of the latch circuit and outputs an analog signal, A data line drive circuit including a selector (107 in FIG. 33) having an output of the DAC circuit as an input and having the same N outputs as the N columns of the display unit, and a scanning line for sequentially applying a voltage to the plurality of scanning lines And a drive circuit (109 in FIG. 33). {(N × B) / (P × S)} serial / parallel converters (1801 in FIG. 33) are arranged, and {(N × B) / S} latch circuits (105 in FIG. 33) are arranged. Then, (N / S) DAC circuits (106 in FIG. 33) are arranged, and the selector circuit (107 in FIG. 33) receives the outputs of the (N / S) DAC circuits (106 in FIG. 33). Based on the selector control signal, data signals are sequentially supplied to the S data line groups for each output of each DAC circuit for the time period divided by the block division number S. A latch clock signal is supplied from a controller (113 in FIG. 33) to a latch circuit (105 in FIG. 33), a selector control signal is supplied to a selector circuit (107 in FIG. 33), and a serial / parallel conversion circuit (113 in FIG. 33). 1801), a serial / parallel conversion control signal is supplied.
[0055]
In this embodiment, the TFTs forming the peripheral circuit including the data line driving circuit and the scanning line driving circuit are formed by the same process as the TFT of the pixel switch of the display portion.
In other words, the data line drive circuit, the scan line drive circuit, and the gate insulating film of each of the transistors forming the display section have the same structure, and the film thickness is set to be equal within the range of process variation. . It should be noted that, among the inventions of each claim in the claims, the correspondence between some inventions and the accompanying drawings is described. Claim 11 is FIG. 1, claim 12 is FIG. Claim 13 is FIG. 7, claim 14 is FIG. 8, claim 15 is FIG. 10, claim 16 is FIG. 11, claim 17 is FIG. 13, claim 18 is FIG. 14, and claim 19 is FIG. 20 is FIG. 17, claim 21 is FIG. 18, claim 22 is FIG. 21, claim 23 is FIG. 22, claim 24 is FIG. 23, claim 25 is FIG. 25, claim 26 is FIG. 26, and claim 27. 28, claim 28 is FIG. 29, claim 29 is FIG. 30, claim 30 is FIG. 32, claim 31 is FIG. 33, claim 32 is FIG. 34, and claims 33 to 35 are FIG. 36.
[0056]
【Example】
Embodiments of the present invention will be described below in detail with reference to the drawings in order to explain the above-described embodiments of the present invention in further detail.
[0057]
[Example 1]
FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention. With reference to FIG. 1, a first embodiment of the present invention will be described in detail. Referring to FIG. 1, the first embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. The system circuit side substrate 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer (controller) 108, a scanning circuit (scanning line driving circuit) 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, and a display unit 110. Connected to IC102. The level shifter circuit 104, the latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, the selector circuit 107 is connected to the column side of the display unit 110, and the output of the level shifter circuit 104 is latched by the latch circuit 105. The output of the latch circuit 105 is converted into an analog signal by the DAC circuit 106 and output to the data line of the display unit 110 via the selector circuit 107.
[0058]
In this embodiment, the display section 110 performs active matrix display of M rows and N columns with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. The selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110.
[0059]
The output buffer 112 divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 by the number of block divisions S, and ｛(N × B) / S ｝ It is composed of circuits of the number of bits.
[0060]
The level shifter 104 and the latch circuit 105 are composed of circuits having the same number of {(N × B) / S} bits as the output buffer 112.
[0061]
The DAC circuit 106 is composed of an (N / S) circuit, inputs the number of gradation bits B, and outputs an analog signal corresponding to a digital value of each gradation.
[0062]
FIG. 2 is a diagram for explaining the timing operation of the first embodiment of the present invention. Referring to FIG. 2, when an input data signal is input from the output buffer 112 of the controller IC 102 to the display device substrate 101 via the {(N × B) / S} bit data bus during one horizontal period, The data is latched at the falling edge of the latch clock signal supplied to the latch circuit 105. As a result, the output signal of the latch circuit 105 becomes an input signal to the next DAC circuit 106. The latch clock signal is supplied from the level shifter / timing buffer 108 to the latch circuit 105.
[0063]
Each data signal is subjected to DA conversion (digital / analog conversion) by the DAC circuit 106 to be an analog signal corresponding to the digital value of each gradation.
[0064]
As a selector control signal supplied to the selector circuit 107, a control pulse is sequentially scanned as shown in FIG. 2 on wirings for the number of block divisions S (S = 4 in FIG. 2). The selector control signal is supplied from the level shifter / timing buffer 108 to the selector circuit 107.
[0065]
When this selector control signal is input to the selector circuit 107, the signals are sequentially selected from the output signal of the DAC circuit 106 and separated into the number (S) of the block division number S, which is the block division number S. It is sent to each signal line (data line) of the signal line group.
[0066]
By supplying (N / S) such signal line groups and supplying signals in parallel to all of them, signal supply to N signal lines in one horizontal period is realized.
[0067]
A gate signal for driving each gate line of the M-th row of pixel switches of the display unit 110 is supplied from the scanning circuits 109 (M), and is kept at a high level for one horizontal period, and is kept at a low level for other periods. It is. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0068]
In this embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configuration of FIGS.
[0069]
A data signal for the display unit 110 in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation.
[0070]
In the output buffer 112, data is transferred in {(N × B) / S} bits because the output is divided into the block division number S for each of the M gate scanning lines and output. From the output buffer 112 of the controller IC 102 to the display device substrate 101 via the {(N × B) / S} bit data bus, the data is divided into 1 (= 4) block divisions in one horizontal period. Display data for the line is transferred. As a result, data can be transferred at a lower transfer rate than the conventional serial transfer method.
[0071]
The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage amplitude to a high voltage value (voltage amplitude).
[0072]
The level shift circuit 104 eliminates the need for data transfer at a high voltage, so that power consumption is significantly reduced.
[0073]
The latch circuit 105 latches the data signal at the falling edge of the latch clock signal supplied to the latch circuit 105, as shown in FIG. The latch circuit 105 is supplied as a latch clock signal to which a signal from the controller 113 which is boosted to a high voltage amplitude by the level shifter / timing buffer 108 is supplied. The level shift circuit 104 and the latch circuit 105 perform processing with {(N × B) / S} bits, which is the same as the number of bits transferred from the output buffer 112.
[0074]
The DAC circuit 106 is composed of an (N / S) circuit, and performs a digital-to-analog conversion from a data group of the number of grayscale bits B of the input {(N × B) / S} bits, and converts one analog signal Thus, all the circuits output (N / S) (bit) analog signal data. That is, the B outputs of the {(N × B) / S} latch circuits 105 are input to one corresponding DAC 106, and the DAC 106 outputs an analog voltage signal corresponding to the grayscale data.
[0075]
The (N / S) analog data signals (bits) of the DAC 106 are sequentially selected by the selector circuit 107 for each output based on the selector control signal in the time period divided into the block division number S. A data signal is supplied to the data line group (S = 4 in FIG. 2).
[0076]
As a result, a data signal is supplied to the N data lines.
[0077]
Every time each of the M gate lines is scanned, the corresponding data is sequentially read from the memory 111 and written to the display unit 110 for display.
[0078]
[Example 2]
A second embodiment of the present invention will be described. FIG. 5 is a diagram showing a configuration of the second exemplary embodiment of the present invention. Referring to FIG. 5, the second embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. The system circuit side substrate 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, and a display unit 110, and is connected to the controller IC 102. The level shifter circuit 104, the latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0079]
In the present embodiment, unlike the first embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 are arranged on opposite sides with the display unit 110 interposed therebetween. The driving capability of the gate driver of the scanning circuit 109 is reduced, and the delay between both ends of the gate line is eliminated.
[0080]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block divisions S, and ｛(N × B) / S回路 There is a circuit of the number of bits. The level shifter 104 and the latch circuit 105 include a circuit having the same number of {(N × B) / S} bits as the output buffer 112. The DAC circuit 106 includes an (N / S) circuit.
[0081]
[Example 3]
A third embodiment of the present invention will be described. FIG. 6 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 6, the third embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, and a display unit 110, and is connected to the controller IC 102. The latch circuit 105, the level shifter circuit 104, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column of the display unit 110.
[0082]
That is, in the present embodiment, the arrangement of the latch circuit 105 and the level shifter 104 is different from that of the first embodiment.
[0083]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B.
[0084]
The memory 111 has a capacity of (M × N × B) bits.
[0085]
Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block divisions S, and ｛(N × B) / S回路 There is a circuit of the number of bits.
[0086]
The level shifter 104 and the latch circuit 105 include a circuit having the same number of {(N × B) / S} bits as the output buffer 112. The DAC circuit 106 includes an (N / S) circuit.
[0087]
In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0088]
[Example 4]
Next, a fourth embodiment of the present invention will be described. FIG. 7 is a diagram showing the configuration of the fourth embodiment of the present invention. Referring to FIG. 7, the fourth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. The system circuit side substrate 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 includes a timing buffer 701, a scanning circuit 109, a latch circuit 105, a DAC circuit 106, a selector circuit 107, and a display unit 110, and is connected to the controller IC 102. The latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column of the display unit 110.
[0089]
That is, the present embodiment is different from the first and third embodiments in that the level shifter circuit 104 does not exist and the timing buffer 701 is provided instead of the level shifter / timing buffer 108.
[0090]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block divisions S, and ｛(N × B) / S回路 There is a circuit of the number of bits. The latch circuit 105 has a circuit having the same number of {(N × B) / S} bits as the output buffer 112. The DAC circuit 106 includes an (N / S) circuit. In this embodiment, as in the second embodiment, the timing buffer 701 and the scanning circuit 109 may of course be arranged on both the left and right sides of the display unit 110.
[0091]
[Example 5]
Next, a fifth embodiment of the present invention will be described. FIG. 8 is a diagram showing the configuration of the fifth embodiment of the present invention. Referring to FIG. 8, a fifth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a voltage-current conversion circuit / current output buffer 801 and a display unit 110. , And the controller IC 102. The level shifter circuit 104, the latch circuit 105, the DAC circuit 106, the voltage-current conversion circuit / current output buffer 801 and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0092]
That is, the present embodiment is different from the first to fourth embodiments in that a voltage-current conversion circuit / current output buffer 801 exists.
[0093]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block divisions S, and ｛(N × B) / S回路 There is a circuit of the number of bits. The level shifter 104 and the latch circuit 105 include a circuit having the same number of {(N × B) / S} bits as the output buffer 112.
[0094]
The DAC circuit 106 and the voltage-current conversion circuit / current output buffer 801 are composed of (N / S) circuits. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0095]
In the present embodiment, unlike the first to fourth embodiments, the provision of the voltage-current conversion circuit / current output buffer 801 makes it possible to supply a data signal to a current-driven display element instead of a voltage-driven display element. It is possible.
[0096]
FIG. 9 is a diagram for explaining the timing operation of the fifth embodiment of the present invention. Referring to FIG. 9, when an input data signal is input to the display device substrate 101 during one horizontal period, the data is latched at the falling edge of the latch clock signal supplied to the latch circuit 105. As a result, the output signal of the latch circuit 105 is as shown in FIG. This signal becomes an input signal to the next DAC circuit 106.
[0097]
Each data signal is DA-converted (digital-to-analog converted) by the DAC circuit 106, and becomes an analog signal corresponding to the digital value of each gradation. This DAC output signal is converted from a voltage signal to a current signal by a voltage-current conversion circuit / current output buffer 801.
[0098]
As selector control signals, control pulses are sequentially scanned as shown in FIG. 9 on the wirings for the block division number S (S = 4 in FIG. 9).
[0099]
When this selector control signal is input to the selector circuit 107, signals are sequentially selected from the output signal of the voltage-current conversion circuit / current output buffer 801 and separated into signals of the number of block divisions S. S is sent to each signal line of the signal line group.
[0100]
By supplying (N / S) such signal line groups and supplying signals in parallel to all of them, signal supply to N signal lines in one horizontal period is realized.
[0101]
The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0102]
In the present embodiment, with the configuration of FIGS. 8 and 9, it is possible to perform display on the display unit 110 using current signals of M rows and N columns. A data signal for the display unit in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation. In the output buffer 112, data is transferred in {(N × B) / S} bits because the output is divided into the block division number S for each of the M gate scanning lines and output. As a result, data can be transferred at a lower transfer rate than the conventional transfer method.
[0103]
The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. The level shift circuit 104 eliminates the need for data transfer at a high voltage, so that power consumption is significantly reduced. The latch circuit 105 latches the data signal as shown in FIG. The level shift circuit 104 and the latch circuit 105 perform processing with {(N × B) / S} bits, which is the same as the number of bits transferred from the output buffer 112. The DAC circuit 106 is composed of an (N / S) circuit, and performs a digital-to-analog conversion from a data group of gray scale bits B among {(N × B) / S} input bits to convert a 1-bit analog signal. As a result, all circuits output (N / S) -bit analog signal data.
[0104]
This (N / S) -bit analog data signal is converted from a voltage value to a current value by the next voltage-current conversion circuit / output buffer 801. This signal is sequentially selected by the next selector circuit 107 at the time divided into the block division number S for each bit, and the data signal is supplied to the S data line groups.
[0105]
As a result, a data signal (for one line) is supplied to the N data lines. Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0106]
[Example 6]
Next, a sixth embodiment of the present invention will be described. FIG. 10 is a diagram showing the configuration of the sixth embodiment of the present invention. Referring to FIG. 10, the sixth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a selector circuit 107, a decoder circuit 1001, a current output buffer 1002, and a display unit 110, and is connected to the controller IC 102. You. The level shifter circuit 104, the latch circuit 105, the decoder circuit 1001, the current output buffer 1002, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0107]
That is, this embodiment is different from the first to fifth embodiments in that the DAC circuit 106 does not exist and the decoder circuit 1001 and the current output buffer 1002 exist. The current output buffer 1002 is of a variable output current type and outputs a current according to the decoding result of the decoder circuit 1001.
[0108]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block divisions S, and ｛(N × B) / S回路 There is a circuit of the number of bits. The level shifter 104 and the latch circuit 105 include a circuit having the same number of {(N × B) / S} bits as the output buffer 112. The decoder circuit 1001 and the current output buffer 1002 are composed of (N / S) circuits. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0109]
[Example 7]
Next, a seventh embodiment of the present invention will be described. FIG. 11 is a diagram showing the configuration of the seventh embodiment of the present invention. Referring to FIG. 11, the seventh embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101.
[0110]
The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, and a display unit 110, and is connected to the controller IC 102. The level shifter circuit 104, the latch circuit 105, and the DAC circuit 106 are arranged in this order, and the DAC circuit 106 is connected to the column of the display unit 110. In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the DAC circuit 106 has the same N outputs as the number of column-side inputs of the display unit 110. The output buffer 112 has a circuit of (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111. The level shifter 104 and the latch circuit 105 include a circuit having the same (N × B) number of bits as the output buffer 112.
[0111]
That is, the present embodiment is different from the first to sixth embodiments in that the selector circuit 107 does not exist and the block is not divided. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0112]
FIG. 12 is a diagram for explaining the timing operation of the seventh embodiment of the present invention. Referring to FIG. 12, when an input data signal is input to the display device substrate 101 during one horizontal period, the data is latched at the falling edge of the latch clock signal supplied to the latch circuit 105.
[0113]
As a result, the output signal of the latch circuit 105 is as shown in FIG. This signal becomes an input signal to the next DAC circuit 106. Each data signal is DA-converted (digital-to-analog converted) by the DAC circuit 106, and becomes an analog signal corresponding to the digital value of each gradation. The DAC output signal is sent to each data signal line as it is.
[0114]
The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0115]
In the present embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configuration of FIG. 11 and FIG. A data signal for the display unit in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation. In the output buffer 112, data is transferred in (N × B) bits in order to output every M gate scanning lines. As a result, data can be transferred at a lower transfer rate than the conventional transfer method. The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. The level shift circuit 104 eliminates the need for data transfer at a high voltage, so that power consumption is significantly reduced.
[0116]
The latch circuit 105 latches the data signal as shown in FIG. The level shift circuit 104 and the latch circuit 105 perform processing with the same number of bits (N × B) as the number of bits transferred from the output buffer 112. The DAC circuit 106 is composed of N circuits. The DAC circuit 106 performs digital-to-analog conversion from a data group of the number of gray scale bits B among (N × B) input bits to obtain a 1-bit analog signal. Outputs bit analog signal data. The N-bit analog data signal is directly supplied to the N data lines to supply the data signal. Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0117]
Example 8
Next, an eighth embodiment of the present invention will be described. FIG. 13 is a diagram showing the configuration of the eighth embodiment of the present invention. Referring to FIG. 13, the eighth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, and a display unit 110, and is connected to the controller IC 102. The latch circuit 105, the level shifter circuit 104, and the DAC circuit 106 are arranged in this order, and the DAC circuit 106 is connected to the column of the display unit 110.
[0118]
That is, in the present embodiment, the arrangement of the latch circuit 105 and the level shifter 104 is different from that of the seventh embodiment.
[0119]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the DAC circuit 106 has the same N outputs as the number of column-side inputs of the display unit 110. The output buffer 112 has a circuit of (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111. The level shifter 104 and the latch circuit 105 include a circuit having the same (N × B) number of bits as the output buffer 112.
[0120]
That is, this embodiment is different from the first to sixth embodiments in the same way as the seventh embodiment in that the selector circuit 107 does not exist and the block is not divided. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0121]
[Example 9]
Next, a ninth embodiment of the present invention will be described. FIG. 14 is a diagram showing the configuration of the ninth embodiment of the present invention. Referring to FIG. 14, the ninth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a timing buffer 401, a scanning circuit 109, a latch circuit 105, a DAC circuit 106, and a display unit 110, and is connected to the controller IC 102.
[0122]
The latch circuit 105 and the DAC circuit 106 are arranged in this order, and N DAC circuits 106 are connected to the column side of the display unit 110. That is, the present embodiment is different from the seventh and eighth embodiments in that the level shifter circuit 104 does not exist and the timing buffer 401 is provided instead of the level shifter / timing buffer 108.
[0123]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the DAC circuit 106 has the same N outputs as the number of column-side inputs of the display unit 110.
[0124]
The output buffer 112 is provided with a circuit of (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111. The latch circuit 105 is provided with a circuit having the same (N × B) number of bits as the output buffer 112.
[0125]
That is, this embodiment is different from the first to sixth embodiments in the same way as the seventh embodiment in that the selector circuit 107 does not exist and the block is not divided. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0126]
[Example 10]
Next, a tenth embodiment of the present invention will be described. FIG. 15 is a diagram showing the configuration of the tenth embodiment of the present invention. Referring to FIG. 15, a tenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a voltage-current conversion circuit / current output buffer 801 and a display unit 110. Connected. The level shifter circuit 104, the latch circuit 105, the DAC circuit 106, the voltage-current conversion circuit / current output buffer 801 are arranged in this order, and the voltage-current conversion circuit / current output buffer 801 is connected to the column side of the display unit 110.
[0127]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. The voltage-current conversion circuit / current output buffer 801 has the same N outputs as the number of column-side inputs of the display unit 110. The output buffer 112 has a circuit of (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111. The level shifter 104 and the latch circuit 105 include a circuit having the same (N × B) number of bits as the output buffer 112. The DAC circuit 106 includes N circuits.
[0128]
That is, the present embodiment is different from the fifth embodiment in that the selector circuit 107 does not exist and the block is not divided. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0129]
FIG. 16 is a diagram for explaining the timing operation of the tenth embodiment of the present invention. Referring to FIG. 16, when an input data signal is input to the display device substrate 101 during one horizontal period, the data is latched at the falling edge of the latch clock signal supplied to the latch circuit 105. As a result, the output signal of the latch circuit 105 is as shown in FIG. This signal becomes an input signal to the next DAC circuit 106. Each data signal is subjected to DA conversion (digital / analog conversion) by the DAC circuit, and becomes an analog signal corresponding to the digital value of each gradation. Although this DAC output signal is a voltage signal, it is converted into a current output signal by the voltage-current conversion circuit / current output buffer 801. This current output signal is sent to each data signal line as it is. The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0130]
In the present embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configurations of FIGS. A data signal for the display unit in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation. In the output buffer 112, data is transferred in (N × B) bits in order to output every M gate scanning lines. As a result, data can be transferred at a lower transfer rate than the conventional transfer method. The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. This level shift circuit eliminates the need for data transfer at a high voltage, so that power consumption is greatly reduced.
[0131]
The latch circuit 105 latches the data signal as shown in FIG. The level shift circuit 104 and the latch circuit 105 perform processing with the same number of bits (N × B) as the number of bits transferred from the output buffer 112.
[0132]
The DAC circuit 106 is composed of N circuits. The DAC circuit 106 performs digital-to-analog conversion from a data group of the number of gray scale bits B among (N × B) input bits to obtain a 1-bit analog signal. It outputs N-bit analog signal voltage data. This N-bit analog data signal is converted from a voltage signal to a current signal by a voltage-current conversion circuit / current output buffer 801. The N-bit analog current signal is directly supplied to the N data lines, and the data signal is supplied. Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0133]
[Example 11]
Next, an eleventh embodiment of the present invention will be described. FIG. 17 is a diagram showing the configuration of the eleventh embodiment of the present invention. Referring to FIG. 17, the eleventh embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a decoder circuit 1001, a current output buffer 1002, and a display unit 110, and is connected to the controller IC 102. A level shifter circuit 104, a latch circuit 105, a decoder circuit 1001 that inputs the outputs of the B latch circuits 105, and a current output buffer 1002 that receives the output of the decoder circuit 1001 and outputs a current value according to the decoding result are arranged in this order. A current output buffer 1002 is connected to the column side of the display unit 110. In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. In addition, the current output buffer 1002 has the same N outputs as the number of column-side inputs of the display unit 110. The output buffer 112 has a circuit of (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111. The level shifter 104 and the latch circuit 105 include a circuit having the same (N × B) number of bits as the output buffer 112. The decoder circuit 1001 includes N circuits.
[0134]
That is, the present embodiment is different from the sixth embodiment in that the selector circuit 107 does not exist and the block is not divided. In this embodiment, as in the second embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as a matter of course.
[0135]
[Example 12]
Next, a twelfth embodiment of the present invention will be described. FIG. 18 is a diagram showing the configuration of the twelfth embodiment of the present invention. Referring to FIG. 18, the twelfth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a serial / parallel conversion circuit 1801, and a display unit 110. Connected. The level shifter circuit 104, the serial / parallel conversion circuit 1801, the latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0136]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of {(N × B) / (P × S)} bits. The level shifter 104 has a circuit having the same number of ((N × B) / (P × S)) bits as the output buffer 112. The latch circuit 105 has a circuit of {(N × B) / S} bits. The DAC circuit 106 includes an (N / S) circuit.
[0137]
This embodiment is different from the other embodiments in that a serial / parallel conversion circuit 1801 is provided and the number of bits of each circuit is different.
[0138]
FIG. 19 is a diagram for explaining the timing operation of the twelfth embodiment of the present invention. Referring to FIG. 19, when an input data signal is input to the display device substrate 101 during one horizontal period, a signal developed by the serial / parallel conversion circuit 1801 into a serial / parallel developed number P (here, P = 2) Become.
[0139]
The P-phase expansion is controlled by an S / P conversion circuit control signal in a serial / parallel conversion circuit (hereinafter abbreviated as “S / P conversion circuit”) 1801. The S / P conversion circuit control signal is supplied from the level shifter / timing buffer 108 to the S / P conversion circuit 1801.
[0140]
In the example of FIG. 19, at the falling edge of the odd (even) pulse of the S / P conversion circuit control signal, the odd data of the input data signal is latched, and the S / P conversion circuit output A is generated. On the other hand, at the falling edge of the even (odd) pulse of the S / P conversion circuit control signal, the even data of the input data signal is latched, and the S / P conversion circuit output B is generated. When the number of developments P is 3 or more, the data signal is developed for each multiple of P. Next, the signal is latched at the falling edge of the latch clock signal supplied to the latch circuit 105. As a result, the output signal of the latch circuit 105 is as shown in the figure. This signal becomes an input signal to the next DAC circuit 106. Each data signal is subjected to DA conversion (digital / analog conversion) by the DAC circuit, and becomes an analog signal corresponding to the digital value of each gradation.
[0141]
As a selector control signal, control pulses are sequentially scanned as shown in FIG. 19 on the wirings for the block division number S (S = 4 in FIG. 19). When this selector control signal is input to the selector circuit 107, the signals are sequentially selected from the DAC output signal, separated into signals of the number of block divisions S, and each signal line of the signal line group whose number is the block division number S Sent to
[0142]
By supplying (N / S) such signal line groups and supplying signals in parallel to all of them, signal supply to N signal lines in one horizontal period is realized. The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0143]
In the present embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configuration of FIGS. A data signal for the display unit in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation. The output buffer 112 divides each of the M gate scanning lines into block division numbers S, and outputs the divided data into serial / parallel phase expansion numbers P, so that ｛(N × B) / (P × S )｝ Data is transferred in bits.
[0144]
As a result, data can be transferred at a lower transfer rate than the conventional transfer method. The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. This level shift circuit eliminates the need for data transfer at a high voltage, so that power consumption is greatly reduced. The serial / parallel conversion circuit 1801 develops the output signal into the serial / parallel phase development number P (here, P = 2) as shown in FIG. The level shift circuit 104 and the serial / parallel conversion circuit 1801 perform processing with {(N × B) / (P × S)} bits which are the same as the number of bits transferred from the output buffer 112.
[0145]
The latch circuit 105 latches the data signal as shown in FIG. The latch circuit 105 has P times the number of bits by serial / parallel conversion, and performs processing with {(N × B) / S} bits. The DAC circuit 106 is composed of an (N / S) circuit, and performs a digital-to-analog conversion from a data group of gray scale bits B among {(N × B) / S} input bits to convert a 1-bit analog signal. As a result, all circuits output (N / S) -bit analog signal data. The (N / S) -bit analog data signal is sequentially selected by the next selector circuit 107 in the time period divided into the block division number S for each bit, and the data signal is supplied to the S data line groups. . As a result, a data signal is supplied to the N data lines. Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0146]
In this embodiment, the latch is performed at the falling edge of the S / P conversion circuit control signal. However, the latch may be performed at the rising edge. Alternatively, the output A may be latched at the falling (rising) edge, and the output B may be latched at the rising (falling) edge. In the case of this configuration, a waveform having a cycle twice as long as the S / P conversion circuit control signal in FIG. 19 can be used as the S / P conversion circuit control signal.
[0147]
Example 13
Next, a thirteenth embodiment of the present invention will be described. FIG. 20 is a diagram showing the configuration of the thirteenth embodiment of the present invention. Referring to FIG. 20, a thirteenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a serial / parallel conversion circuit 1801, and a display unit 110. Connected. The level shifter circuit 104, the serial / parallel conversion circuit 1801, the latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0148]
In the present embodiment, unlike the twelfth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 are arranged on the left and right sides of the display unit 110. In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of {(N × B) / (P × S)} bits. The level shifter 104 has a circuit having the same number of ((N × B) / (P × S)) bits as the output buffer 112. The latch circuit 105 has a circuit of {(N × B) / S} bits. The DAC circuit 106 includes an (N / S) circuit.
[0149]
[Example 14]
Next, a fourteenth embodiment of the present invention will be described. FIG. 21 is a diagram showing the configuration of the fourteenth embodiment of the present invention. Referring to FIG. 21, the fourteenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a serial / parallel conversion circuit 1801, and a display unit 110. Connected. The serial / parallel conversion circuit 1801, the latch circuit 105, the level shifter circuit 104, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0150]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of {(N × B) / (P × S)} bits.
[0151]
Since the level shifter 104 and the latch circuit 105 are arranged after the serial / parallel conversion, there are circuits for {(N × B) / S} bits which are P times larger than the number of output buffers.
[0152]
The DAC circuit 106 includes an (N / S) circuit.
[0153]
This embodiment is different from the twelfth and thirteenth embodiments in the arrangement order and the number of circuits of the serial / parallel conversion circuit 1801, the level shifter 104 and the latch circuit 105. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0154]
[Example 15]
Next, a fifteenth embodiment of the present invention will be described. FIG. 22 is a diagram showing the configuration of the fifteenth embodiment of the present invention. Referring to FIG. 22, the fifteenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 includes a timing buffer 401, a scanning circuit 109, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a serial / parallel conversion circuit 1801, and a display unit 110, and is connected to the controller IC 102. The serial / parallel conversion circuit 1801, the latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0155]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of {(N × B) / (P × S)} bits. Since the latch circuit 105 is arranged after the serial / parallel conversion, there is a circuit having {(N × B) / S} bits, which is P times larger than the output buffer. The DAC circuit 106 includes an (N / S) circuit.
[0156]
The present embodiment is different from the twelfth and fourteenth embodiments in that the level shifter circuit 104 does not exist and the timing buffer 401 is provided instead of the level shifter / timing buffer 108. In this embodiment, as in the second embodiment, the timing buffer 401 and the scanning circuit 109 may of course be arranged on both the left and right sides of the display unit 110.
[0157]
[Example 16]
Next, a sixteenth embodiment of the present invention will be described. FIG. 23 is a diagram showing the configuration of the sixteenth embodiment of the present invention. Referring to FIG. 23, the sixteenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 includes a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a selector circuit 107, a serial / parallel conversion circuit 1801, a voltage-current conversion circuit / current output buffer 801 and a display. It has a built-in unit 110 and is connected to the controller IC 102. The level shifter circuit 104, serial / parallel conversion circuit 1801, latch circuit 105, DAC circuit 106, voltage-current conversion circuit / current output buffer 801, and selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110. Have been.
[0158]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of {(N × B) / (P × S)} bits.
[0159]
The level shifter 104 has a circuit having the same number of ((N × B) / (P × S)) bits as the output buffer 112.
[0160]
The latch circuit 105 has a circuit of {(N × B) / S} bits. The DAC circuit 106 and the voltage-current conversion circuit / current output buffer 801 are composed of (N / S) circuits.
[0161]
This embodiment is different from the other embodiments in that a voltage-current conversion circuit / current output buffer 801 exists. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0162]
FIG. 24 is a diagram for explaining the timing operation of the sixteenth embodiment of the present invention. Referring to FIG. 24, when an input data signal is input to the display device substrate 101 during one horizontal period, a signal developed by the serial / parallel conversion circuit 1801 into a serial / parallel development number P (here, P = 2) Become. This development is controlled by an S / P conversion circuit control signal in a serial / parallel conversion circuit (hereinafter abbreviated as “S / P conversion circuit”) 1801.
[0163]
In the example of FIG. 24, the odd data of the input data signal is latched at the falling edge of the odd (even) pulse of the S / P conversion circuit control signal, and the output A of the S / P conversion circuit is generated. On the other hand, the even data of the input data signal is latched at the falling edge of the even (odd) pulse of the S / P conversion circuit control signal, and the output B of the S / P conversion circuit 1801 is generated.
[0164]
When the number of developments P is 3 or more, the data signal is developed for each multiple of P.
[0165]
Next, the signal is latched at the falling edge of the latch clock signal supplied to the latch circuit 105.
[0166]
As a result, the output signal of the latch circuit 105 is as shown in FIG. This signal becomes an input signal to the next DAC circuit 106.
[0167]
Each data signal is DA-converted (digital-to-analog converted) by the DAC circuit 106, and becomes an analog signal corresponding to the digital value of each gradation. This DAC output signal is converted from a voltage signal to a current signal by a voltage-current conversion circuit / current output buffer 801. As selector control signals, control pulses are sequentially scanned as shown in FIG. 24 on the wirings for the block division number S (S = 4 in FIG. 24).
[0168]
When this selector control signal is input to the selector circuit 107, the signals are sequentially selected from the DAC output signal, separated into signals of the number of block divisions S, and each signal line of the signal line group whose number is the block division number S Sent to By supplying (N / S) such signal line groups and supplying signals in parallel to all of them, signal supply to N signal lines in one horizontal period is realized. The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0169]
In the present embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configuration of FIGS. A data signal for the display unit 110 of M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation.
[0170]
Since the output buffer 112 divides the M gate scanning lines into block division numbers S for each and separates them into serial / parallel phase development numbers P and outputs the divided data, ｛(N × B) / (P × S)デ ー タ Data is transferred in bits. As a result, data can be transferred at a lower transfer rate than the conventional transfer method.
[0171]
The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. The level shift circuit 104 eliminates the need for data transfer at a high voltage, so that power consumption is significantly reduced.
[0172]
The serial / parallel conversion circuit 1801 expands the output signal into the serial / parallel phase expansion number P (here, P = 2) as shown in FIG. The level shift circuit 104 and the serial / parallel conversion circuit 1801 perform processing with {(N × B) / (P × S)} bits which are the same as the number of bits transferred from the output buffer 112.
[0173]
The latch circuit 105 latches the data signal as shown in FIG. This latch circuit 105 has P times the number of bits by serial / parallel conversion, and performs processing with {(N × B) / S} bits.
[0174]
The DAC circuit 106 is composed of an (N / S) circuit, and performs a digital-to-analog conversion from a data group of gray scale bits B among {(N × B) / S} input bits to convert a 1-bit analog signal. As a result, all circuits output (N / S) -bit analog signal data.
[0175]
This (N / S) -bit analog data signal is converted from a voltage signal to a current signal by a voltage-current conversion circuit / current output buffer 801. The (N / S) -bit analog current signal is sequentially selected by the next selector circuit 107 at a time divided into the block division number S for each bit, and supplies a data signal to the S data line groups. . As a result, a data signal is supplied to the N data lines.
[0176]
Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0177]
In this embodiment, the latch is performed at the falling edge of the S / P conversion circuit control signal. However, the latch may be performed at the rising edge. Alternatively, the output A may be latched at the falling (rising) edge, and the output B may be latched at the rising (falling) edge. In the case of this configuration, as the S / P conversion circuit control signal, a waveform having a cycle twice as long as the S / P conversion circuit control signal in FIG. 24 can be used.
[0178]
[Example 17]
Next, a seventeenth embodiment of the present invention will be described. FIG. 25 is a diagram showing the configuration of the seventeenth embodiment of the present invention. Referring to FIG. 25, the seventeenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a decoder circuit 1001, a selector circuit 107, a serial / parallel conversion circuit 1801, a current output buffer 1002, and a display unit 110. And is connected to the controller IC 102. The level shifter circuit 104, serial / parallel conversion circuit 1801, latch circuit 105, decoder circuit 1001, current output buffer 1002, and selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0179]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of {(N × B) / (P × S)} bits. The level shifter 104 has a circuit having the same number of ((N × B) / (P × S)) bits as the output buffer 112. The latch circuit 105 has a circuit of {(N × B) / S} bits. The decoder circuit 1001 and the current output buffer 1002 are composed of (N / S) circuits.
[0180]
This embodiment is different from the above-described embodiment in that a decoder circuit 1001 and a current output buffer 1002 are present. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0181]
[Example 18]
Next, an eighteenth embodiment of the present invention will be described. FIG. 26 is a diagram showing the configuration of the eighteenth embodiment of the present invention. Referring to FIG. 26, the eighteenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a DAC circuit 106, a serial / parallel conversion circuit 1801, and a display unit 110, and is connected to the controller IC 102. The level shifter circuit 104, the serial / parallel conversion circuit 1801, the latch circuit 105, and the DAC circuit 106 are arranged in this order, and the DAC circuit 106 is connected to the column of the display unit 110.
[0182]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits.
[0183]
Further, the DAC circuit 106 has the same N outputs as the number of column-side inputs of the display unit 110. In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of serial / parallel phase expansions P (N × B) / There is a circuit of P｝ number of bits. The level shifter 104 has a circuit having the same number of {(N × B) / P} bits as the output buffer 112. The latch circuit 105 has a circuit of (N × B) bits. The DAC circuit 106 includes N circuits.
[0184]
This embodiment is different from the other embodiments in that the selector circuit 107 does not exist and the number of bits of each circuit is different. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0185]
FIG. 27 is a diagram for explaining the timing operation of the eighteenth embodiment of the present invention. Referring to FIG. 27, when an input data signal is input to the display device substrate 101 during one horizontal period, a signal developed by the serial / parallel conversion circuit 1801 into a serial / parallel developed number P (here, P = 2) Become. This development is controlled by an S / P conversion circuit control signal in a serial / parallel conversion circuit (hereinafter abbreviated as “S / P conversion circuit”) 1801.
[0186]
In the example of FIG. 27, the odd data of the input data signal is latched at the falling edge of the odd (even) pulse of the S / P conversion circuit control signal, and the output A of the S / P conversion circuit is generated. On the other hand, the even data of the input data signal is latched at the falling edge of the even (odd) pulse of the S / P conversion circuit control signal, and the output B of the S / P conversion circuit is generated. When the number of developments P is 3 or more, the data signal is developed for each multiple of P. Next, the signal is latched at the falling edge of the latch clock signal supplied to the latch circuit 105. As a result, the output signal of the latch circuit 105 is as shown in the figure. This signal becomes an input signal to the next DAC circuit 106. Each data signal is subjected to DA conversion (digital / analog conversion) by the DAC circuit, and becomes an analog signal corresponding to the digital value of each gradation. The DAC output signal is sent to each data signal line as it is. The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0187]
In the present embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configurations of FIGS. 26 and 27. A data signal for the display unit in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation. In the output buffer 112, data is transferred by {(N × B) / P} bits in order to separate and output the number P of serial / parallel phases for each of the M gate scanning lines. As a result, data can be transferred at a lower transfer rate than the conventional transfer method. The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. This level shift circuit eliminates the need for data transfer at a high voltage, so that power consumption is greatly reduced.
[0188]
The serial / parallel conversion circuit 1801 develops the output signal into the serial / parallel phase development number P (here, P = 2) as shown in FIG. The level shift circuit 104 and the serial / parallel conversion circuit 1801 perform processing with {(N × B) / P} bits, which is the same as the number of bits transferred from the output buffer 112. The latch circuit 105 latches the data signal as shown in FIG. The latch circuit 105 has P times the number of bits by serial / parallel conversion, and performs processing with (N × B) bits. The DAC circuit 106 is composed of N circuits. The DAC circuit 106 performs digital-to-analog conversion from a data group of the number of gray scale bits B among (N × B) input bits to obtain a 1-bit analog signal. Outputs bit analog signal data. The N-bit analog data signal is directly supplied to N data lines. Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0189]
In this embodiment, the latch is performed at the falling edge of the S / P conversion circuit control signal. However, the latch may be performed at the rising edge. Alternatively, the output A may be latched at the falling (rising) edge, and the output B may be latched at the rising (falling) edge. In the case of this configuration, a waveform having a cycle twice as long as the S / P conversion circuit control signal in FIG. 27 can be used as the S / P conversion circuit control signal.
[0190]
[Example 19]
Next, a nineteenth embodiment of the present invention will be described. FIG. 28 is a diagram showing the configuration of the nineteenth embodiment of the present invention. Referring to FIG. 28, the nineteenth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101.
[0191]
Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 incorporates a level shifter / timing buffer 108, a scanning circuit 109, a serial / parallel conversion circuit 1801, a level shifter 104, a latch circuit 105, a DAC circuit 106, and a display unit 110, and is connected to the controller IC 102. The serial / parallel conversion circuit 1801, the level shifter circuit 104, the latch circuit 105, and the DAC circuit 106 are arranged in this order, and the DAC circuit 106 is connected to the column of the display unit 110. In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the DAC circuit 106 has the same N outputs as the number of column-side inputs of the display unit 110.
[0192]
The output buffer 112 has a circuit of {(N × B) / P} bits corresponding to one row of (M × N × B) bits of the memory 111. The latch circuit 105 has a circuit of (N × B) bits. The DAC circuit 106 includes N circuits.
[0193]
In this embodiment, the arrangement of the level shifters 104 and the number of bits are different from those of the eighteenth embodiment. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0194]
[Example 20]
Next, a twentieth embodiment of the present invention will be described. FIG. 29 is a diagram showing the configuration of the twentieth embodiment of the present invention. Referring to FIG. 29, the twentieth embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 includes a timing buffer 401, a scanning circuit 109, a serial / parallel conversion circuit 1801, a latch circuit 105, a DAC circuit 106, and a display unit 110, and is connected to the controller IC 102. The serial / parallel conversion circuit 1801, the latch circuit 105, and the DAC circuit 106 are arranged in this order, and the DAC circuit 106 is connected to the column side of the display unit 110.
[0195]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the DAC circuit 106 has the same N outputs as the number of column-side inputs of the display unit 110.
[0196]
The output buffer 112 has a circuit of {(N × B) / P} bits corresponding to one row of (M × N × B) bits of the memory 111. The serial / parallel conversion circuit 1801 receives the serial output from the output buffer 112 P times and develops it into a P phase (P-bit parallel output), and outputs (N × B) bits from the serial / parallel conversion circuit 1801 in parallel. Is done. The latch circuit 105 has a circuit of (N × B) bits. The DAC circuit 106 includes N circuits.
[0197]
This embodiment is different from the eighteenth and nineteenth embodiments in that the level shifter circuit 104 does not exist and the timing buffer 401 is provided instead of the level shifter / timing buffer 108. In this embodiment, as in the thirteenth embodiment, the timing buffer 401 and the scanning circuit 109 may of course be arranged on both the left and right sides of the display unit 110.
[0198]
[Example 21]
Next, a twenty-first embodiment of the present invention will be described. FIG. 30 is a diagram showing the configuration of the twenty-first embodiment of the present invention. Referring to FIG. 30, the twenty-first embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 includes a level shifter / timing buffer 108, a scanning circuit 109, a serial / parallel conversion circuit 1801, a level shifter 104, a latch circuit 105, a DAC circuit 106, a voltage-current conversion circuit / current output buffer 801 and a display unit 110. And is connected to the controller IC 102. The level shifter circuit 104, the serial / parallel conversion circuit 1801, the latch circuit 105, the DAC circuit 106, the voltage-current conversion circuit / current output buffer 801 are arranged in this order, and the voltage-current conversion circuit / current output buffer 801 is arranged in the column of the display unit 110. Connected to the side.
[0199]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. The voltage-current conversion circuit / current output buffer 801 has the same N outputs as the number of column-side inputs of the display unit 110.
[0200]
The output buffer 112 has a circuit of {(N × B) / P} bits obtained by dividing (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 by P. There is. The level shifter 104 has a circuit having the same number of {(N × B) / P} bits as the output buffer 112. The latch circuit 105 receiving the parallel output (P) of the serial / parallel conversion circuit 1801 has (N × B) circuits. The DAC circuit 106 and the voltage-current conversion circuit / current output buffer 801 are composed of N circuits.
[0201]
This embodiment is different from the other embodiments in that a voltage-current conversion circuit / current output buffer 801 exists. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0202]
FIG. 31 is a diagram for explaining the timing operation of the twenty-first embodiment of the present invention. Referring to FIG. 31, when an input data signal is input to the display device substrate 101 during one horizontal period, a signal developed by the serial / parallel conversion circuit 1801 into a serial / parallel developed number P (here, P = 2) Become.
[0203]
This development is controlled by an S / P conversion circuit control signal in a serial / parallel conversion circuit (hereinafter abbreviated as “S / P conversion circuit”) 1801. In the example of FIG. 31, the odd data of the input data signal is latched at the falling edge of the odd (even) pulse of the S / P conversion circuit control signal, and the output A of the S / P conversion circuit is generated. On the other hand, the even data of the input data signal is latched at the falling edge of the even (odd) pulse of the S / P conversion circuit control signal, and the output B of the S / P conversion circuit is generated. When the number of developments P is 3 or more, the data signal is developed for each multiple of P.
[0204]
Next, the signal is latched at the falling edge of the latch clock signal supplied to the latch circuit 105. As a result, the output signal of the latch circuit 105 is as shown in the figure. This signal becomes an input signal to the next DAC circuit 106. Each data signal is subjected to DA conversion (digital / analog conversion) by the DAC circuit, and becomes an analog signal corresponding to the digital value of each gradation. Although this DAC output signal is a voltage signal, it is converted into a current output signal by the voltage-current conversion circuit / current output buffer 801. This current output signal is sent to each data signal line as it is. The gate signal is maintained at a high level for one horizontal period, and is at a low level during other periods. Such gate signals are sequentially scanned, and a gate signal is supplied to each of the M gate lines.
[0205]
In the present embodiment, it is possible to perform display on the display unit 110 of M rows and N columns by the configuration of FIGS. A data signal for the display unit in M rows and N columns is prepared as a digital signal, and (M × N × B) bits of data are stored in the memory 111 according to the bit number B of the digital gradation. In the output buffer 112, data is transferred by {(N × B) / P} bits in order to separate and output the number P of serial / parallel phases for each of the M gate scanning lines. As a result, data can be transferred at a lower transfer rate than the conventional transfer method. The transferred data signal is boosted by the level shift circuit 104 from input data having a low voltage value to a high voltage value. Since the level shift circuit 104 does not require data transfer at a high voltage, power consumption is significantly reduced. The serial / parallel conversion circuit 1801 develops the output signal into the serial / parallel phase development number P (here, P = 2) as shown in FIG. The level shift circuit 104 and the serial / parallel conversion circuit 1801 perform processing with {(N × B) / P} bits, which is the same as the number of bits transferred from the output buffer 112.
[0206]
The latch circuit 105 latches the data signal as shown in FIG. The latch circuit 105 has P times the number of bits by serial / parallel conversion, and performs processing with (N × B) bits. The DAC circuit 106 is composed of N circuits. The DAC circuit 106 performs digital-to-analog conversion from a data group of the number of gray scale bits B among (N × B) input bits to obtain a 1-bit analog signal. Outputs bit analog signal data. This N-bit analog data signal is converted from a voltage signal into a current signal by a voltage-current conversion circuit / current output buffer 801 consisting of N bits. The N-bit analog current data signal is directly supplied to the N data lines. Each time the M gate lines are scanned, data is sequentially read from the memory 111 and written to the display unit 110.
[0207]
In this embodiment, the latch is performed at the falling edge of the S / P conversion circuit control signal. However, the latch may be performed at the rising edge. Alternatively, the output A may be latched at the falling (rising) edge, and the output B may be latched at the rising (falling) edge. In the case of this configuration, as the S / P conversion circuit control signal, a waveform having a cycle twice as long as the S / P conversion circuit control signal in FIG. 31 can be used.
[0208]
[Example 22]
Next, a twenty-second embodiment of the present invention will be described. FIG. 32 is a diagram showing the configuration of the twenty-second embodiment of the present invention. Referring to FIG. 32, a twenty-second embodiment of the present invention includes a system-side circuit board 103, a controller IC 102, and a display device board 101. Here, the system circuit-side board 103 includes an interface circuit 114 and is connected to the controller IC 102. The controller IC 102 includes a controller 113, a memory 111, and an output buffer 112, and is connected to the system circuit board 103 and the display device board 101. The display device substrate 101 includes a level shifter / timing buffer 108, a scanning circuit 109, a level shifter 104, a latch circuit 105, a serial / parallel conversion circuit 1801, a decoder circuit 1001, a current output buffer 1002, and a display unit 110. Connected to. The level shifter circuit 104, the serial / parallel conversion circuit 1801, the latch circuit 105, the decoder circuit 1001, and the current output buffer 1002 are arranged in this order, and the current output buffer 1002 is connected to the column side of the display unit 110.
[0209]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. The current output buffer 1002 has N outputs equal to the number of column-side inputs of the display unit 110.
[0210]
In the output buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of serial / parallel phase expansions P (N × B) / There is a circuit of P｝ number of bits.
[0211]
The level shifter 104 has a circuit having the same number of {(N × B) / P} bits as the output buffer 112. The latch circuit 105 has a circuit of (N × B) bits.
[0212]
The decoder circuit 1001 and the current output buffer 1002 are composed of N circuits.
[0213]
This embodiment is different from the other embodiments in that a current output buffer 1002 is present. In this embodiment, as in the thirteenth embodiment, the level shifter / timing buffer 108 and the scanning circuit 109 may be arranged on both left and right sides of the display unit 110, as in the thirteenth embodiment.
[0214]
[Example 23]
Next, a twenty-third embodiment of the present invention will be described. FIG. 33 is a diagram showing the configuration of the twenty-third embodiment of the present invention. Referring to FIG. 33, the twenty-third embodiment of the present invention includes a system-side circuit board 103 and a display device board 101. Here, the system-side circuit board 103 includes an interface circuit 114 and is connected to the display device board 101. The display device substrate 101 includes a controller 113, a memory 111, a buffer 112, a scanning circuit 109, a latch circuit 105, a serial / parallel conversion circuit 1801, a DAC circuit 106, a selector circuit 107, and a display unit 110. Connected to substrate 103. The serial / parallel conversion circuit 1801, the latch circuit 105, the DAC circuit 106, and the selector circuit 107 are arranged in this order, and the selector circuit 107 is connected to the column side of the display unit 110.
[0215]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits. Further, the selector circuit 107 has the same N outputs as the number of column-side inputs of the display unit 110. In the buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of block division numbers S and the serial / parallel phase development number P. There is a circuit of (N × B) / (P × S)｝ number of bits. Since the latch circuit 105 is arranged after the serial / parallel conversion, there is a circuit having {(N × B) / S} bits, which is P times larger than the output buffer.
[0216]
The DAC circuit 106 includes an (N / S) circuit. This embodiment is different from the other embodiments in that the controller IC 102 does not exist and the memory 111 and the buffer 112 are arranged on the display device substrate 101. In this embodiment, as in the second embodiment, the controller 113 and the scanning circuit 109 may of course be arranged on both left and right sides of the display unit 110.
[0219]
[Example 24]
Next, a twenty-fourth embodiment of the present invention will be described. FIG. 34 is a diagram showing the configuration of the twenty-fourth embodiment of the present invention. Referring to FIG. 34, the twenty-fourth embodiment of the present invention includes a system-side circuit board 103 and a display device board 101. Here, the system-side circuit board 103 includes an interface circuit 114 and is connected to the display device board 101. The display device board 101 includes a controller 113, a memory 111, a buffer 112, a scanning circuit 109, a latch circuit 105, a serial / parallel conversion circuit 1801, a DAC circuit 106, and a display unit 110, and is connected to the system-side circuit board 103. Is done. The serial / parallel conversion circuit 1801, the latch circuit 105, and the DAC circuit 106 are arranged in this order, and the DAC circuit 106 is connected to the column side of the display unit 110.
[0218]
In this embodiment, active matrix display of M rows and N columns is performed on the display unit 110 with the number of gray scale bits B. The memory 111 has a capacity of (M × N × B) bits.
[0219]
The DAC circuit 106 has N circuits, and has N outputs equal to the number of column-side inputs of the display unit 110. In the buffer 112, (N × B) bits corresponding to one row of (M × N × B) bits of the memory 111 are divided by the number of serial / parallel phase expansions P (｛(N × B) / P).回路 A circuit of the number of bits is provided. Since the latch circuit 105 is arranged after the serial / parallel conversion, there is a circuit having (N × B) bits, which is P times larger than the output buffer. This embodiment is different from the other embodiments in that the controller IC 102 does not exist and the memory 111 and the buffer 112 are arranged on the display device substrate 101. In this embodiment, as in the second embodiment, the controller 113 and the scanning circuit 109 may of course be arranged on both left and right sides of the display unit 110.
[0220]
Next, a method of manufacturing the display panel substrate used in each of the above embodiments will be described.
[0221]
[Example 25]
In this example, a TFT array of polysilicon (polycrystalline silicon, poly-Si) was manufactured. 35 to 36 are process cross-sectional views showing a manufacturing structure of an array of polysilicon TFTs (planar structure) for forming a channel in a surface layer of polycrystalline silicon.
[0222]
Specifically, after forming the silicon oxide film 11 on the glass substrate 10, the amorphous silicon 12 was grown. Next, annealing was performed using an excimer laser to convert amorphous silicon into polysilicon (FIG. 35A).
[0223]
Further, after a silicon oxide film 13 having a thickness of 10 nm is grown and patterned (FIG. 35B), a photoresist 14 is applied and patterned (masking a p-channel region), and phosphorus (P) ions are doped. As a result, n-channel source and drain regions were formed (FIG. 35C).
[0224]
Further, after growing a 90-nm-thick silicon oxide film 15 serving as a gate insulating film, microcrystalline silicon (μ-c-Si) 16 and tungsten silicide (WSi) 17 for forming a gate electrode are grown. Then, it was patterned into a gate shape (FIG. 35D).
[0225]
Photoresist 18 was applied and patterned (masking the n-channel region), and boron (B) was doped to form n-channel source and drain regions (FIG. 36E).
[0226]
After continuously growing the silicon oxide film and the silicon nitride film 19, holes for contact were made (FIG. 36F), aluminum and titanium 20 were formed by sputtering, and patterning was performed (FIG. 36G). ). By this patterning, the source / drain electrodes of the CMOS of the peripheral circuit, the data line wiring connected to the drain of the pixel switch TFT, and the contact to the pixel electrode are formed.
[0227]
Subsequently, a silicon nitride film 21 as an insulating film was formed, a hole for contact was made, an ITO (indium tin oxide) 22 as a transparent electrode for a pixel electrode was formed, and patterning was performed (FIG. 36 (h)).
[0228]
In this manner, a TFT pixel switch having a planar structure was formed, and a TFT array was formed.
[0229]
The peripheral circuit section has substantially the same process as the n-channel TFT together with the n-channel TFT similar to the pixel switch, but a p-channel TFT is formed by doping with boron. FIG. 36H shows an n-channel TFT of the peripheral circuit, a p-channel TFT of the peripheral circuit, a pixel switch (n-channel TFT), a storage capacitor, and a pixel electrode from the left side of the figure.
[0230]
The circuit configuration was the same as that of the first embodiment shown in FIG. The TFTs constituting the circuit on the display device substrate were made of TFTs having the same process. A process which requires the highest voltage and which can operate the pixel switch and selector circuit 107 was adopted.
[0231]
Further, a patterned pillar of 4 μm was formed on the TFT substrate (not shown) to be used as a spacer for maintaining a cell gap and to have an impact resistance.
[0232]
Further, a sealing material for ultraviolet curing was applied to the outside of the pixel region of the counter substrate (not shown).
[0233]
After bonding the TFT substrate and the counter substrate, liquid crystal was injected. The liquid crystal material was a nematic liquid crystal, and a chiral material was added to match the rubbing direction to obtain a twisted nematic (TN) type.
[0234]
In the present embodiment, a transmissive liquid crystal display device that simultaneously satisfies high definition, multiple gradations, low cost, and low power consumption as compared with the conventional configuration can be realized.
[0235]
In this embodiment, an excimer laser is used for forming the polysilicon film. However, another laser, for example, a CW laser that oscillates continuously may be used.
[0236]
In the first embodiment and the like, the data is transferred from the controller IC 102 to the data line driving circuit of the display device substrate 101 in units of one line or in units of bit data obtained by dividing one line by the block division number S (= 4) or the like. The operating frequency of the data line driving circuit is reduced. Generally, as the thickness of the gate insulating film of a transistor is larger, the threshold value is higher and the operation speed is lower. In the above embodiment in which the operating frequency of the peripheral circuit is reduced, the operation can be performed even if a TFT having a low operating speed is used. That is, when the operating frequency increases, optimization of the threshold value of the transistor and the like are required, but by lowering the operating frequency, in this embodiment, the threshold value of the transistor does not need to be optimized. In this embodiment, a CMOS circuit of a polycrystalline silicon TFT (the thickness of a gate insulating film is 90 nm) formed by the same process that requires the high voltage and capable of operating the pixel switch and the selector circuit 107 is used. Peripheral circuits.
[0237]
[Example 26]
As a twenty-sixth embodiment of the present invention, a TFT array of polysilicon (polycrystalline silicon, poly-Si) was manufactured to constitute a reflective display device. 35 and 36, after a silicon oxide film 11 is formed on a glass substrate 10, an amorphous silicon 12 is grown and then annealed using an excimer laser to convert the amorphous silicon into polysilicon (FIG. 35 ( a)), and a silicon oxide film having a thickness of 10 nm was further grown (FIG. 35B).
[0238]
After patterning, the source and drain regions of the n-channel TFT were formed by patterning the photoresist and doping with phosphorus ions (P) (FIG. 35 (c)).
[0239]
Further, after growing a 90 nm silicon oxide film 15, microcrystalline silicon (μ-c-Si) 16 and tungsten silicide (WSi) 17 were grown and patterned into a gate shape (FIG. 35 (d)).
[0240]
After continuously growing a silicon oxide film and a silicon nitride film, holes for contact were made (FIG. 36 (f)), and aluminum and titanium were formed by sputtering and patterned (FIG. 36 (g)).
[0241]
Subsequently, an organic film was applied and patterned using a mask for realizing a substantially random uneven structure. Again, a hole for contact was made, aluminum and titanium were formed by sputtering, and patterned to obtain a reflective pixel electrode (reflective plate).
[0242]
A 3.5 μm silica spacer was sprayed on the TFT substrate. Further, a sealing material for ultraviolet curing was applied to the outside of the pixel region of the opposing substrate. After bonding the TFT substrate and the counter substrate, liquid crystal was injected. The liquid crystal material was a nematic liquid crystal, and a chiral material was added to match the rubbing directions to obtain a twisted nematic (TN) type having a twist angle of 67 degrees.
[0243]
In addition, a color filter having a density and a color tone suitable for the reflection type configuration was adopted as the color filter on the counter substrate. Further, by using a compensating plate and an optimized polarizing plate, a reflection type liquid crystal display device having a high contrast ratio and a high reflectance was realized.
[0244]
The circuit configuration used in this embodiment is the same as the twelfth embodiment shown in FIG. With this configuration, the driving method is such that the common power potential (Vcom) of the opposing substrate is inverted for each scanning line. Thereby, the voltage applied to the liquid crystal was set to an amplitude of 5 V at the maximum (the transistor for driving the data line is driven at 5 V).
[0245]
Since the present embodiment is a reflection type liquid crystal, a backlight is not required, and a liquid crystal display device with lower power consumption than the twenty-fifth embodiment can be realized.
[0246]
[Example 27]
An organic EL is used as a display element. After forming a TFT array in the same manner as in the twenty-sixth embodiment, an element isolation film was formed and patterned. Next, a hole injection layer and a light emitting layer were sequentially formed by inkjet patterning. In this step, the hole injection layer and the light emitting layer were patterned using an inkjet patterning apparatus having a control mechanism capable of discharging ink to an arbitrary position. After forming the cathode, it was sealed.
[0247]
The circuit configuration used in this embodiment is the same as that of the sixteenth embodiment shown in FIG. In this example, the organic EL was driven to obtain a good display.
[0248]
In the above embodiment, the configuration in which the display elements are sequentially scanned has been described. On the other hand, by providing two memories in the pixel portion, two fields of data may be stored in the two memories, and a panel sequential scan in which the entire panel is scanned at a time may be used.
[0249]
The operation and effect of the above-described embodiment will be described.
[0250]
(1) The provision of a drive IC with a built-in DAC circuit and a controller IC with a built-in memory allows a significant reduction in IC cost.
[0251]
In a drive circuit integrated display device without a built-in DAC circuit, a driver IC with a built-in memory is required instead of a controller IC. FIG. 3 shows the relationship between the built-in memory capacity and the IC cost for the built-in memory driver IC and the built-in memory controller IC. IC cost is increasing with an increase in memory capacity. Comparing the driver IC with a built-in memory and the controller IC with a built-in memory shows that the cost of the controller IC with a built-in memory is about half the cost. As described above, according to the present invention, the cost can be easily reduced.
[0252]
(2) Reduce the power consumption of the interface circuit.
[0253]
FIG. 4 shows the relationship between the read frequency (MHz) and the power consumption of the interface circuit. As can be seen from FIG. 4, when the read frequency decreases by one digit, the power consumption also decreases by almost one digit.
[0254]
In the present invention, the read frequency is reduced by increasing the width of the bus from the memory built-in controller IC. Due to this decrease in frequency, power consumption can be significantly reduced.
[0255]
[Example 28]
A twenty-eighth embodiment of the present invention will be described. Hereinafter, the reason why the present invention can reduce the power consumption will be described in detail while comparing the circuit configuration of a conventional display device as a comparative example, focusing on power consumption. First, as a comparative example, power consumption in a typical example of the configuration of a conventionally known polysilicon TFT-LCD will be considered.
[0256]
FIG. 39 is a diagram illustrating an example of the architecture of a display device when a conventional configuration principle is applied, as a comparative example. An example of a circuit configuration of one element of a shift register (66-bit Shift-Register), a data register (DATA REGISTER), a load latch (LOAD-LATCH), and a level shift (Level-Shifter) used in FIG. 40, 41, 42, and 44, respectively. FIG. 43 is a timing chart showing the timing operation of the system of FIG. The specific numerical values shown in FIG. 39 are set so as to match the specifications of the display device (see FIG. 45) of the twenty-eighth embodiment of the present invention described below for the sake of explanation and comparison.
[0257]
Referring to FIG. 39, digital video data DB0 to DB5 (for example, 0 to 3.0 V) are level-shifted to, for example, 0 to 10 V by a level shift circuit (Level Shifter), and output from a buffer (Buffer). The clock CLK supplied to the 66-bit shift register (66-bit Shift-Register) is also level-shifted by the level shift circuit (Level Shifter). From the buffer (Buffer), 4-bit signals of CLK, XCLK, D1, and D2 are supplied to a shift register (6-bit Shift-Register). The 66 data registers (DATA REGISTER) are latch timing signals Rn (n = 1 to 66) from a 66-bit shift register (66-bit Shift-Register), and are 6-bit data buses DB0 to DB5. And a latch circuit for storing and holding the data by the complementary signal XRn is provided in parallel.
[0258]
In the shift register (66-bit Shift-Register) of FIG. 40, a first clocked inverter, an inverter whose input is connected to the output of the first clocked inverter, and an input whose output is connected to the output of the inverter are output. The second clocked inverter connected to the output of the first clocked inverter forms a unit latch circuit, and the shift register in FIG. 40 has a cascade configuration of 66 stages, which is the number of data registers (6b-DATA REGISTER). It has a connected latch. In the two-stage latches, the clock signals input to the corresponding clocked inverters are complementary (CLK and XCLK), and each of the two-stage latches constitutes a master-slave latch. From the 66 outputs of the shift register, latch timing signals R1 to R66 of the data latch are output. The latch timing signals R1 to R66 are controlled by control signals DST, D1, and D2 supplied to the shift register (as shown in FIG. 43, DST is at a high level, D1 is at a high level, and R1 is at a high level. Becomes). The load latch (LOAD-LATCH) includes, as shown in FIG. 42, a first clocked inverter that is turned on / off by a clock DCL, an inverter whose input is connected to the output of the first clocked inverter, The input is connected to the output of the inverter, the output is connected to the output of the first clocked inverter, and the second clocked inverter that is turned on / off by the complementary clock XDCL of the clock DCL is configured by a unit latch circuit.
[0259]
As shown in FIG. 44, the level shift circuit (Level Shifter) cross-connects the gate and the drain of a pair of P-type MOS transistors whose sources are connected to the 10 V side, and connects the drains of the pair of P-type MOS transistors. The data (0-3V) and its complementary signal are differentially input to the gates of the pair of N-type MOS transistors, and the amplitude is 0-10V. Is taken out.
[0260]
In the configuration shown in FIG. 39, 6 × 66-bit load latches (6 × 66-bit digital-to-analog converters) are used to simultaneously input digital video data at desired timing and hold them for a certain period of time. LOAD-LATCH). In order to write digital video data into this load latch, 66 circuits of 6-bit data registers (6b-DATA-REGISTER) addressed by shift registers (66b-Shift-Register) are connected in a bus system. These logic circuits, that is, digital signal processing circuits, are driven by a power supply voltage of 10 V or more. Therefore, the digital signals of the six digital data bus lines to which the 6-bit data register (6b-DATA-REGISTER) is connected are also driven at an amplitude of 10 V or more using the level conversion circuit (Level-Shifter).
As described above, in the conventional configuration shown in FIG. 39, in order to simultaneously drive 66 6-bit DACs, digital data input with a 6-bit width is converted into digital data with a 396-bit width. That is, this display device has six data bus lines, 66 six-bit data registers connected to the bus lines, and an opening for taking in each data register and holding data. A shift register for supplying a control signal and a load latch for holding 396-bit width data for a certain period constitute a 6-bit input / 396-bit output serial-parallel conversion circuit.
[0261]
The digital data bus line and the clock line for driving the shift register are driven at the highest speed on the display device substrate. FIG. 43 shows a timing chart of a control line for driving the control device.
[0262]
When a display device is designed with this conventional architecture, the digital signal processing circuit composed of the above circuit consumes about half of the total power consumed on the glass substrate as will be described later (most of the rest is consumed). , Consumed by the DAC). Therefore, a device for reducing the power of the digital signal processing circuit is useful.
[0263]
Considering the power of the digital signal processing circuit, the following (a) to (c) are factors of consumption.
(A) The digital data bus line has a large parasitic capacitance. The first reason is that many data registers are connected to this. The second reason is that many interline couplings occur because the branch line connecting the bus line to the data register crosses the bus line on the layout.
FIG. 41 shows a circuit of one element of the 6-bit data register (6b-DATA-REGISTER) of FIG. 39 and bus lines D0 to D5.
(B) The digital data bus line is driven at the highest frequency on a glass substrate. Similarly, clock lines (CLK and XCLK in FIG. 39) for driving the shift register (66b-Shift-Register) are also driven at the highest frequency.
(C) The level conversion circuit (Level-Shifter) (for example, see FIG. 44) consumes a lot of power.
[0264]
Therefore, the present inventors have found that power consumption can be reduced by reducing these factors. That is, in view of the above-described factors of power consumption, a new display device architecture was devised.
[0265]
FIG. 45 shows a configuration of a display device according to a twenty-eighth embodiment of the present invention. FIG. 45 shows a parallel architecture display device according to the present invention. In addition, based on the design specifications shown in Table 1, a DAC with 176 pixels × RGB × 234 pixels and a 6-bit gradation (260,000 colors) is integrated on a glass substrate, and a 3V digital interface (3.0 V interface) LCD is used as a frame. Drive at a frequency of 30 Hz.
[0266]
Table 1 Specifications of the display device of the present invention

[0267]
In the display device according to the embodiment of the present invention shown in FIG. 45, the display device substrate (the glass substrate (Glass Substrate in FIG. 45)) includes a plurality of data lines (N lines) and a plurality of scanning lines (M lines). A display area (Display Area) having pixel groups arranged in M rows and N columns in a matrix at intersections is provided, and display data of B-bit (6 bits in FIG. 45) gray scale is expressed by (M × N) pixels. A display memory (Frame Memory) for storing minutes (that is, (M × N × B) bits); an output buffer for reading data (Digital Image Data) from the display memory and outputting the data to the display panel substrate (Glass Substrate); A controller that controls a display memory and the output buffer, and controls communication and control with a higher-level device. A controller device, and the output buffer in the controller device divides (N × B) bits corresponding to one row of the (M × N × B) bits of the memory into blocks. {(N × B) / (P × S)} divided by the number S and the P phase are arranged.
[0268]
In the example shown in FIG. 45, N = 176 × 3 (for RGB) = 528, M = 234, S = 8, and P = 2. The number of data lines (signal lines) in the display area (Display Area) is 528 in total from S001 to S528, and the number of data lines of the data bus (the number of output buffers of the controller device) is ｛(N × B). / (P × S)｝ = 528 × 6 / (8 × 2) = 66 × 3 = 198, and the digital video data (between the controller IC (Controller Frame Memory) and the glass substrate (Glass Substrate) 198 bits of D001 to D198 are provided with a data bus for Digital Image Data transfer, and driven at a transfer rate of 125 KHz.
[0269]
A data line driving circuit (Data Driver) for driving a data line in a display area on a glass substrate (Glass Substrate) is displayed via a {(N × B) / (P × S)} bit width data bus. Data (digital video data) is transferred. In one horizontal period, {(N × B) / (P × S)} bits of digital video data are divided into (P × S) times, and display data for one line is transferred. In the example shown in FIG. 45, 198-bit width data (D001 to D198) is divided into 2 × 8 times, and display data for one line is transferred.
[0270]
A data line driving circuit (Data Driver) on a glass substrate (Glass Substrate) is a P level shift circuit (LS) commonly connected to one data line of the data bus, and includes a controller. A level shift circuit for level-shifting the amplitude of the P-phase signal output from the output buffer on the device side and sequentially received via the data line to a signal having a higher amplitude, and driving the outputs of the P number of the level shift circuits A P-phase expansion circuit (SPC) including a latch circuit (LATs) that latches each according to a clock, develops P-phase serial bit data into P parallel bits, and latches and outputs as P-bit parallel data; For a data bus of {(N × B) / (P × S)} data lines, the P-phase expansion circuit (SPC The {(N × B) / (P × S)} comprises pieces. {(N × B) / (P × S)} P-phase expansion circuits (SPCs) output {(N × B) / S} bits of data in parallel, of which B bits are (N / S) digital-to-analog conversion circuits (referred to as “DAC circuits”) for inputting an output and outputting an analog signal; receiving the outputs of the (N / S) DAC circuits; And a selector for outputting to the N data lines.
[0271]
In the configuration shown in FIG. 45, there are {(N × B) / (P × S)} two-phase expansion circuits (SPC) each including two level shift circuits (LS) and a plurality of latch circuits (LATs). That is, {(528 × 6) / (2 × 8)} = 66 × 3 = 198 pieces are juxtaposed. Naturally, this number is equal to the number of data signal lines D001 to D198. Data of {(528 × 6) / 8} = 66 × 6 = 396 bits (G001 to G396) are output from the 198 two-phase expansion circuits (SPCs). Further, 66 (N / S) = 528/8 = 66 6-bit DAC circuits (6b-DAC) are provided, and outputs (66 analog voltage outputs) of 66 DAC circuits (6b-DAC) are provided. A selector that receives an input and outputs the data to N (528) data lines (S001 to S528) of the display unit (Display Area) is configured as a 1: 8 demultiplexer. A 1: 8 demultiplexer divides one signal into eight outputs. (N / S) = 66 demultiplexers (1-to-8 DEMUX) are provided. The selector circuit (1-to-8 DEMUX × 66) receives the outputs of the 66 DAC circuits (6b-DAC) and outputs the 66 DAC circuits (66 analog voltage outputs) based on the selector control signal. Are sequentially supplied to the 66 data line groups in a time period divided into eight block division numbers. Further, a scanning line driver (Scan Line Driver) for sequentially applying a voltage to a plurality of scanning lines of the display area (Display Area) is provided.
[0272]
The controller device supplies a control signal such as a clock (CLK) (frequency 62.5 kHz), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync) to a level shift circuit (Level Shifter (2)) on the glass substrate. I do. These clocks and control signals along with the data bus follow the 3.0 V interface. In the level shift circuit (Level Shifter (2)), the level of the clock and control signal is converted into a 10 V system and output to a timing circuit (Timing Circuit). The timing circuit (Timing Circuit) supplies a clock (CLK) having a 10 V amplitude and XCLK which is a complementary clock of the clock (CLK) to the SPC or the like. The power supply circuit (Power) supplies a power supply voltage of 10 V, -5 V, or the like to the glass substrate.
[0273]
As described above, the data driver (DATA Driver) integrated on the glass substrate includes a sampling level conversion and two-phase expansion circuit (SPC) for a 3V interface, a 6-bit DAC, and a 1-to-8 demux (1 to 8 DEMUX). It consists of.
[0274]
FIG. 46 is a diagram showing an example of a circuit of one element (SPC connected to one data signal D (n)) of the two-phase expansion circuit (SPC) of FIG. This two-phase expansion circuit (SPC) (a circuit for converting 1-bit serial data to 2-bit parallel data) includes two sampling level shift circuits commonly connected to the output D (n) (0-3V) of the data buffer. (LS) and a plurality of latch circuits (LAT) connected to respective outputs of the two sampling level conversion circuits (LS). Each latch circuit latches input data with a sampling clock CLK and its complementary clock XCLK. I do.
[0275]
An upper first sampling level shift circuit (LS) in the SPC of FIG. 46 is connected in series between a higher power supply (10 V in this example) and a lower power supply (GND), and includes first to third power supplies. A first to a third MOS transistor (P1, N3, N2) forming a switch element, a capacitor (C2) connected to a connection point of the first and second MOS transistors (P1, N3), and D ( n) and a third MOS transistor (N1) connected between an input terminal connected to the third MOS transistor (N2) and a gate terminal of the third MOS transistor (N2) and forming a fourth switch element. N2), and a capacitor (C1) connected to the gate of the first and second MOS transistors (P1, N3). The first sampling clock (CLK) (0-10 V) is common to the gates of the first and second MOS transistors (P1, N3). input It is, to the gate of the fourth MOS transistor (N1), a second sampling clock complementary with the first sampling clock (CLK) (XCLK) is input.
[0276]
The operation of the sampling level shift circuit (LS) will be described. When the first sampling clock (CLK) is at the low level (setup period), the MOS transistor (P1) forming the first switch element is turned on, and the second switching element is turned on. The MOS transistor (N3) serving as the switch element is turned off, and the capacitor (C2) is charged to the power supply voltage of the higher power supply. When the second sampling clock (XCLK) is at the high level, the fourth MOS transistor (N1) forming the fourth switch element is turned on, and the capacitor (C1) is charged with the input signal voltage.
[0277]
When the first sampling clock (CLK) is at the high level (output period), the MOS transistor (P1) forming the first switch element is turned off, the MOS transistor (N3) forming the second switch element is turned on, The terminal voltage of the capacitor (C2) at this time is directly or indirectly extracted as an output signal. The sampling level shift circuit (LS) is mounted on a glass substrate, the first MOS transistor P1 is composed of a P-type TFT, and the second to fourth MOS transistors N3, N2, N1 are N-type TFTs. (Thin Film Transistor).
[0278]
The configuration of the second sampling level shift circuit (LS) below the SPC in FIG. 46 is the same, and the connection of the sampling clock is different from that of the first sampling level shift circuit (LS). The second sampling clock (XCLK) is commonly input to the gates of the first and second MOS transistors (P1, N3), and the first sampling clock (CLK) is input to the gate of the fourth MOS transistor (N1). ) Is entered. The second sampling level shift circuit (LS) operates when the second sampling clock (XCLK) is at a low level (setup period) and when the second sampling clock (XCLK) is at a high level (output period). An operation complementary to that of the first sampling level shift circuit (LS) is performed.
[0279]
According to the sampling level shift circuit (LS) of the present invention shown in FIG. 46, the following operation and effect can be obtained.
(A) Low power consumption because no steady current flows.
(B) Since there is a single-phase input (= inverted data is unnecessary), the number of terminals is small (a general level conversion circuit requires two inputs of data and inverted data).
(C) The potential on the high voltage side is not generated at the input terminal, and the possibility of destroying the circuit on the low voltage side is low. When the latch-type sense amplifier shown in FIG. 44 is used for a level shifter, a potential on a high voltage side may be generated at an input terminal.
[0280]
In the case of a polysilicon TFT LCD, for example, it is configured to have about 200 data input terminals. When the present invention is used for an application that requires sampling and level shifting of a large number of data, Especially effective.
[0281]
As shown in FIG. 46, the two-phase expansion circuit (SPC) includes first and second sampling level shift circuits (LS), and the first and second sampling level shift circuits provide an input signal D (n). ) Are commonly input to the second sampling level shift circuit, and the signals of the first and second sampling clock signals (CLK, XCLK) of the first sampling level shift circuit are inverted (that is, the inverted signals). XCLK, CLK) are input to corresponding switch elements as first and second sampling clocks, respectively, and the output of the first sampling level shift circuit is taken in based on the previous first sampling clock signal (CLK). Latch (LAT), latches the output of the first latch (LAT) based on the second sampling clock signal (XCLK) A second latch (LAT) to be output, a third latch (LAT) that outputs an output of the latch of the second latch (LAT) based on a first sampling clock signal (CLK), and a second sampling level. A fourth latch (LAT) that takes in the output of the shift circuit based on the second sampling clock signal (XCLK), and a fifth latch that outputs the output of the fourth latch based on the first sampling clock signal (CLK) (LAT). The first and second latches constitute a first master-slave type latch, and the fourth and fifth latches constitute a second master-slave type latch. Activation of each latch (LAT) is controlled by an input clock signal, and a first clocked inverter whose input and output are connected to an input terminal and an output terminal of the latch, and an output of the first clocked inverter. And a second clocked inverter whose input is connected to the output of the inverter and whose output is connected to the input of the inverter. The first and second clocked inverters each have a clock. Activation / deactivation is controlled by a clock XCLK complementary to CLK.
[0282]
FIG. 47 shows this operation waveform of the circuit of FIG. The odd-numbered signal (G (2n-1)) is output from the three-stage cascade-connected latch outputs, and the even-numbered signal (G (2n)) is output from the two-stage cascade-connected latch outputs. Is output in synchronization with the sampling clock signal (CLK).
[0283]
In the display device shown in FIG. 45, digital video data (Digital Image Data) is input from an external controller IC with a 3V amplitude and a 198-bit width, and the signal level is converted to a 10V amplitude by a digital signal processing circuit (SPC array). The data is supplied to the DAC at a desired timing. The output of one DAC uses a demultiplexer (DEMUX) to drive eight data lines connected to a pixel array (Display Area) in a time-division manner.
[0284]
The feature of this configuration is that data is supplied at a low speed via an interface having a large bus width (198 bit width), and this data is a two-phase expansion circuit having a level conversion function driven in parallel on a glass substrate. (SPC). As described above, digital signal processing is performed by driving a large number of phase expansion circuits in parallel, so this configuration is called a “parallel digital data driver architecture”.
[0285]
Table 2 compares this parallel digital data driver architecture with conventional architectures and discusses why this parallel architecture is low power consumption.
[0286]
Table 2 Comparison of architectures

() Indicates the ratio
[0287]
In the parallel driver architecture of the present invention, the bus width of the interface of digital video data is widened, and the 198 two-phase expansion circuits (SPCs) are driven in parallel, so that the clock frequency can be maintained while maintaining the throughput. , 2.1 MHz to 62.5 kHz.
[0288]
Attention is paid to a digital signal processing circuit arranged before the DAC (input side of the DAC). In the parallel driver architecture of the present invention, 5148 transistors are connected to a clock line driven at 62.5 kHz. On the other hand, in the conventional architecture, 396 transistors are connected to a clock line of a shift register driven at 2.1 MHz.
[0289]
When the product of the number of transistors connected to the clock line and the clock frequency is calculated for each architecture, the parallel architecture is smaller. That is, the power consumption associated with charging / discharging the clock line is smaller in the parallel architecture.
[0290]
Further, in the parallel architecture, since there is no interline coupling between the digital data bus line and its branch line, the power for charging and discharging is zero.
[0291]
The interline coupling, that is, the capacitance generated at a place where a certain wiring for transmitting digital data crosses a certain wiring for transmitting other digital data will be described.
[0292]
In the case of the example shown in FIG. 39, the bus width of the input data is 6 bits, and it is composed of a shift register (66-bit Shift-Register), a data latch (DATA-REGISTER) and a load latch (LOAD-LATCH). The bus width of the data after the phase expansion, which is expanded by the phase expansion circuit, is 6 × 66 bits.
[0293]
At this time, the number of intersections between the bus line and the branch line is 975. In general, when the bus width of input data is n bits and the bus width output by the phase expansion circuit is k × n bits, the number C of interline couplings is
C = n (n-1) (k-1) / 2
Indicated by That is,
The number of interline couplings (denoted by Ci in FIG. 39) is 975. In general, in such a configuration, the input data has a bus width of n bits and is output by the phase expansion circuit. When the bus width is k × n bits, the number C of interline couplings is at least
C = n (n-1) (k-1) / 2
There are the numbers indicated by.
[0294]
In the above example, n = 6 and k = 66. In the case of a conventional phase development circuit composed of a bus line and a data latch connected thereto, the number of interline couplings cannot be reduced.
[0295]
On the other hand, in the present invention, since the number of the interline couplings is zero, power for charging / discharging the bus lines is eliminated, and low power consumption can be achieved.
[0296]
In general, the parallel architecture involves an increase in the circuit scale (when the clock frequency is reduced to 1 / n, the circuit scale is required to be n times in order to obtain the same throughput). The number of transistors is about 8600 in the architecture of FIG. 39 (FIG. 39), and 9900 in the parallel driver architecture (FIG. 45), and does not increase so much.
[0297]
FIG. 50 shows a comparison of the power consumption of the digital signal processing circuit between the parallel digital data driver architecture of the present invention and the conventional architecture.
[0298]
In the logic section excluding the level conversion circuit, the power was reduced from 5.8 mW to 0.82 mW, including charging and discharging of the parasitic capacitance.
[0299]
As a result, the power consumption of the digital signal processing circuit could be reduced from 12.5 mW to 1.08 mW per panel by employing the parallel digital data driver architecture of the present invention.
[0300]
The power of one element of the new level conversion circuit (LS) shown in FIG. 46 (the level shift circuit (New Level Shifter) in the broken line in FIG. 49) is as shown in FIG. The new level conversion circuit has a data rate of about several μW at a data rate of 200 KHz. As shown in comparison with FIG. 46, in the conventional level conversion circuit shown in FIG. 44, the data rate is about 25 μW at 100 KHz, about 35 μW at 150 KHz, and about 47 μW at 200 KHz.
[0301]
In the case of the architecture of the present invention, the maximum operation clock on the display substrate (Glass Substrate) is 62.5 kHz, which is greatly reduced as compared with the conventional 2 MHz. Thereby, the operation margin of the circuit is widened.
[0302]
FIG. 48 shows the results of measuring the maximum operating frequency (maximum clock frequency) of a two-phase expansion circuit (SPC) having a level conversion function. From FIG. 48, it can be seen that when the input signal voltage (Input Data Voltage) is 3 V, the circuit operates at 3 MHz or more. Further, it is understood that the power supply voltage VDD can be further reduced from 10 V, and thus the power consumption can be reduced by lowering the power supply voltage.
[0303]
More specifically, with reference to the configuration of the TFT-LCD of the embodiment shown in FIG. 45, 198 bits (198 bits) supplied in parallel from a 3.0 V interface of a controller (Controller Frame Memory) outside the substrate Digital image data (3 kHz amplitude) of 125 kHz is input to terminals D001 to D198 of a data driver (Data Driver) on a glass substrate (Glass Substrate). D001 is an input terminal of a 1-bit input 2-bit output serial-parallel conversion circuit (SPC). As described with reference to FIG. 46, the serial-parallel conversion circuit (SPC) includes two level shifters (L / S) and a latch (LAT). The same applies to terminals D002 to D198, each of which is an input terminal of a 1-bit 2-bit output serial-parallel conversion circuit. The 198 serial-parallel conversion circuits having 1-bit input and 2-bit output constitute a serial-parallel conversion circuit having 198-bit input and 398-bit output, and 398-bit output nodes are shown by G001 to G396 in the figure. The nodes indicated by G001 to G396 are connected to 66 input nodes of a 6-bit gray scale DA converter. The outputs of these 66 DA converters are input to a demultiplexer array (1 to 8 DEMUX × 66), and outputs S001 to S528 of the demultiplexer array are connected to analog data lines in a display area, and a display area (Display Area) is displayed. ) Is driven. The display unit (Display Area) in FIG. 45 is made of, for example, a 2.4-inch, 41K (176 × 234) pixel TFT-LCD.
[0304]
In FIG. 45, an output node group (for example, G001, G002) that outputs a signal obtained by performing serial-parallel conversion on data (for example, D001) input to an input node of a serial-to-parallel conversion circuit (SPC); An output node group (G003, G004) that outputs a signal obtained by performing serial-parallel conversion on data input to an input node (for example, D002) adjacent to the input node (D001) is adjacent to the input node (D003). Further, as shown in FIG. 45, the circuit unit having the serial-parallel conversion circuit (SPC) is laid out in a substantially rectangular shape, and an input node group is provided on one of the long sides of the rectangle, and the other side of the long side is provided. An output node group is provided on one side.
[0305]
The display device illustrated in FIG. 45 converts digital data input with a width of 198 bits into digital data with a width of 396 bits and inputs the digital data to a DAC array which is a data line driving circuit. This serial-parallel conversion circuit having 198-bit input and 396-bit output is constituted by using 198 circuits of a serial-parallel conversion circuit (SPC) having 1-bit input and 2-bit output. Further, these 198 1-bit input 2-bit output serial-parallel conversion circuits (SPCs) are simultaneously driven by commonly connected CLK and XCLK wirings. Since digital signal processing is performed by driving a large number of serial-parallel conversion circuits in parallel in this manner, this configuration is referred to as a “parallel digital data driver architecture”.
[0306]
In the case of the architecture of the present invention, the maximum operating frequency on the display substrate (Glass Substrate) is 62.5 kHz, which is significantly reduced as compared with the conventional 2 MHz. Thereby, the operation margin of the circuit is widened. Further, the EMI noise is reduced because the operating frequency is lowered. In addition, in FIG. 39 which is a conventional example, the data bus lines are wired from one end of the display device to the other, whereas in FIG. 45 which is the present invention, each data bus line is connected from the input terminal (pad). Only to the SPC. That is, the EMI noise is synergistically reduced because the data wiring length is extremely short.
[0307]
The conventional circuit (FIG. 39) includes six digital data bus lines, one shift register, a 66 × 6 data register, one load latch, and eight conventional level shifters.
[0308]
FIG. 47 is a diagram showing the measurement results of the voltage waveform of the two-phase expansion circuit (SPC). The input of (D (n)) having a 3V amplitude is sampled in synchronization with the rising and falling timings of the clock signal CLK. , 10 (V) digital data G (2n-1) and G (2n) are generated in synchronization with the next rising timing of the clock signal CLK. The frequency of the clock signal is 62.5 kHz, which is the actual driving frequency of the LCD.
[0309]
Also, referring to FIG. 49 described above, the present invention uses a pair of cross-connected p-channel TFT latches (see FIG. 49) whose sources are connected to a pair of commonly connected n-channel TFTs (see FIG. 49). (Referred to as Cascode-Voltage Switch Logic).
FIG. 49 shows the power of the new level shift (L / S) circuit and the power of the conventional level shifter in comparison. At 125 KHz, the circuit of the present invention is 1.4 μW, and the conventional circuit is 30 μW. In the conventional circuit, most of the power consumption occurs as a through current during the transition period. The p-channel TFT and the n-channel TFT flow from the power supply of +10 V to the 0 V ground via the p-channel TFT and the n-channel TFT at the time of transition from LOW to HIGH and from HIGH to LOW.
On the other hand, in the new level shifter (L / S) according to the present invention, almost no current flows from the power supply to the ground.
[0310]
It is also possible to widen the bus width of the interface of digital video data and realize 198-bit input by referring to FIG. 39 which is a conventional configuration. However, when the 6-bit input in the conventional configuration is changed to the 198-bit input, 198 data bus lines are wired from side to side of the display device. For example, a wiring having a width of 5 μm is wired at a pitch of 10 μm. In this case, a layout area of about 2 mm is required only for the width of the wiring region.
[0311]
On the other hand, according to the present invention, as shown in FIG. 45, a large number of data wirings are provided in the horizontal direction in FIG. 45 by wiring one-to-one from the pads to the input part of the 1-bit input 2-bit output serial-parallel conversion circuit. Need not be laid out, and the layout area can be reduced. In the case of the example shown in FIG. 45, the height of the serial-parallel conversion circuit (SPC) having a 1-bit input and 2-bit output including a level shift function in the vertical direction in the drawing is only about 0.4 mm.
[0312]
In FIG. 48, the circuit is supplied with a power supply voltage (VDD) of 10 V, and operates at a clock frequency range exceeding 3 MHz with an input amplitude of 3.0 V. It also operates with an input data voltage of 1.5V or less. This keeps the power required for an external silicon IC such as a controller low.
[0313]
FIG. 50 shows a comparison between the power of the conventional design and the power of the architecture of the present invention. From FIG. 50, the level shifter of the conventional architecture is 6.7 mW, whereas the level shifter of the present invention is used. In this case, the power is reduced by 96% to 0.26 mW. These powers were calculated in consideration of the total, the number of level shifters, and the data rate required for each architecture based on the results of FIG.
The power in the logic including the power required to change (invert) the parasitic capacitance in the interline coupling is 0.82 mW in the present invention, whereas it is 5.8 mW in the conventional architecture. . The total power has been reduced from 12.5 mW to 1.08 mW by the circuit of the invention of FIG.
[0314]
A low-power digital data driver (parallel digital data driver) and a 2.4-inch, 3V interface level shifter (L / S) on a polysilicon TFT LCD were integrated and fabricated, and the power consumption of the LCD was measured. At a frame frequency of 30 Hz, the overall power consumption was 12 mW. In a conventional circuit, it was 23 mW.
About 1.1 m is also consumed by the digital data transfer circuit, and most of the rest is consumed by the DAC.
[0315]
An example of the specifications of the reflective display device will be described.
Display type: 2.4-inch, low-temperature polysilicon TFT reflective LCD
Pixel pitch: 176 × RGB × 234
Number of colors: 6 bits (262k)
Data driver frequency: 62.5kHz
Power consumption: 12mW (23mW: conventional technology)
Input data voltage: HIGH level 3V, LOW level: 0V
Power supply voltage: 10V, 0V, -5V
[0316]
As described above, in the polysilicon TFT LCD, a parallel digital data architecture for reducing power consumption has been developed, featuring a 3V interface level shifter and 198 serial / parallel conversion circuits driven by a 62.5 kHz low-speed clock signal. The power consumption of a 2.4-inch, 41K (176 × 234) pixel TFT LCD with 6b DAC integrated was 12 mW at a 30-Hz frame frequency. This feature makes the architecture of the present invention suitable for mobile application display systems. The following documents are referred to (Non-Patent Documents 1 to 5).
[0317]
[Non-patent document 1]
T. Nakamura et al. , "Low Temperature Poly-Si TFT-LCD with Integrated Analog Circuit," Asia Display '01 Digest, pp 1603-1606 (2001)
[Non-patent document 2]
Y. Mikami et al. , "A 5-in. SVGA TFT-LCD with Integrated Multiple DAC Using Low-Temperature poly-Si TFTs," Asia Display '01 Digest, pp1607-1610 (2001).
[Non-Patent Document 3]
H. Kimura et al. , "A 2.15 inch QCIF Reflective Color TFT-LCD with Digital Memory on Glass (DMOG)," SID '01 Digest, pp 268-271 (2001)
[Non-patent document 4]
Y. Nakajima et al. , "A 3.8 inch QVGA Reflective Color LCD with Integrated 3b DAC Driver," ISSC2000 Digest, pp 188-189 (2000).
[Non-Patent Document 5]
M. Azami et al. , “A 2.6-in DTV TFT-LCD with Area-Reduced integrated 8-bit Digital Data Drivers Using 400-Mobile CGS Technology,” SID'99 Digest, (SID'99 Digest, 99)
[0318]
In the embodiments of FIGS. 45 to 47, a 1-bit input 2-bit output serial-parallel conversion circuit (SPC) including a level conversion function is described. However, the level conversion function may be provided as needed. When the level conversion function is unnecessary, for example, a 1-bit 2-bit output serial-parallel conversion circuit shown in FIG. 51 may be used.
The basic configuration shown in FIG. 51 is obtained by deleting the level conversion function (LS) in the serial-parallel conversion circuit (SPC) in FIG. 46, and converts data D (n) having a logical amplitude of 0 to 3 V into a sample clock CLK. , And latch circuits 513 and 515 which are connected in cascade to the output stage of the latch circuit 511 and latch the output of the preceding latch circuit with the clocks XLCK and CLK. And a latch circuit 514 connected in cascade to the output stage of the latch circuit 512 and latching the output of the latch circuit 512 with a clock CLK.
[0319]
In the above embodiment, an example is shown in which a large number of 1-bit input 2-bit output serial-parallel conversion circuits (SPC) are used. For example, when a 1-bit input 6-bit output serial-parallel conversion circuit is used, 52 and 53 may be applied. FIG. 52 shows a two-phase expansion circuit without a level shift function, which includes two CMOS inverters (power supply voltage = 4.0 V) to which data D (n) having a logic amplitude of 0 to 2.5 V are commonly input. A master-slave latch and a latch (clocked inverter and flip-flop) including two stages of latches each including a clocked inverter and a flip-flop (an inverter and a clocked inverter) provided with a signal obtained by inverting the output of one CMOS inverter by the inverter. (Sampled clocks SMP and XSMP are complementary clock signals), outputs DATAODD, and outputs a signal obtained by inverting the output of the other CMOS inverter by an inverter from a clocked inverter and a flip-flop (an inverter and a clocked inverter). Master-slave latch And outputs the DATAEVEN to pull.
[0320]
Referring to FIG. 53, in the two-phase expansion circuit of FIG. 52, the node (A) to which DATAODD is transmitted is delayed by inverters 82 and 83, and the frequency of input data (DATA) is divided by 6 at the rise of signal DCL. A latch (clocked inverter 52, inverter 53, clocked inverter 54) for outputting, and an inverter 55 for outputting the inverted signal of the latch as D1 are provided.
[0321]
A first master-slave type latch (clocked inverter 30, inverter 31, clocked inverter 32, clocked inverter 33, inverter 34) which takes in the potential of node A at the fall of signal XSMP and outputs it at the rise of signal SMP , Clocked inverter 35) and a second master-slave type latch (clocked inverter 36, inverter 37) which takes in the output (node C) of clocked inverter 33 at the fall of signal XSMP and outputs it at the rise of signal SMP. , A clocked inverter 38, a clocked inverter 39 (output is a node E), an inverter 40, and a clocked inverter 41, and a signal obtained by inverting the output of the inverter 34 of the first master-slave type latch by the inverter 42. Signal DCL Latch for output at the rising edge (the clocked inverter 48, an inverter 49, clocked inverters 50) and includes an inverter 51 for outputting a signal obtained by inverting the output of this latch as D2. A latch (clocked inverter 44, inverter 45, clocked inverter 46) that outputs a signal obtained by inverting the output of the inverter 40 of the second master-slave type latch by the inverter 43 at the rise of the signal DCL, and the output of this latch. And an inverter 47 that outputs a signal obtained by inverting the signal D3.
[0322]
In the two-phase expansion circuit, the DATAEVEN system delays a node (F) to which the DATAEVEN signal is transmitted by inverters 84 and 85, and outputs a latch (clocked inverter 78, An inverter 79, a clocked inverter 80) and an inverter 81 that outputs a signal obtained by inverting the output of the latch as D0.
[0323]
A third master-slave type latch (clocked inverter 56, inverter 57, clocked inverter 58, clocked inverter 59, clocked inverter 60) that takes in the potential of node F at the fall of signal XSMP and outputs it at the rise of signal SMP. , Clocked inverter 61) and a fourth master-slave type latch (clocked inverter 62, inverter 63) which takes in the output (node H) of clocked inverter 59 at the falling edge of signal XSMP and outputs it at the rising edge of signal SMP. , A clocked inverter 64, a clocked inverter 65 (output is node J), an inverter 66, and a clocked inverter 67. A signal obtained by inverting the output of the inverter 60 of the third master-slave type latch by the inverter 68 is Signal DCL Latch for output at the rising edge (clocked inverter 74, an inverter 75, clocked inverters 76) and includes an inverter 77 for outputting a signal obtained by inverting the output of this latch as D2. A latch (clocked inverter 70, inverter 71, clocked inverter 72) for outputting a signal obtained by inverting the output of the inverter 66 of the fourth master-slave type latch by the inverter 69 at the rise of the signal DCL; And an inverter 73 that outputs a signal obtained by inverting the signal as D4.
[0324]
To explain the outline of the operation of the six-phase expansion circuit, DATAODD (node A) and DATAEVEN (F) are generated from the input data DATA, and the signal of the node F is changed to the sampling pulse signal SMP at the nodes C and E of the path of DATAODD. The data of nodes A, C, and E are D1, D3, and D5 at the rising edge of DCL, which is delayed by one cycle and two cycles and is a clock obtained by dividing the input data DATA by six (the timing at which 7 of the input data DATA is input). Are output in parallel. At nodes H and J of the DATAEVEN path, the signal at node F is delayed by one cycle and two cycles of the sampling pulse signal SMP, and the rising edge of DCL, which is a 6-frequency-divided clock of input data DATA (input data 7 is input). ), The data at the nodes F, H, and J are output in parallel as D0, D2, and D4.
[0325]
As described above, the present invention has been described with reference to the above embodiments. However, the present invention is not limited to the configuration of the above embodiments, and a person skilled in the art within the scope of the claims set forth in the claims. Needless to say, various changes and modifications that could be made are included. For example, it goes without saying that the present invention includes an example in which the present invention is applied to a semiconductor device that performs serial-parallel conversion of input data, such as a printer head, a liquid crystal driver IC, and a memory.
[0326]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
[0327]
A first effect of the present invention is that the provision of a controller IC with a built-in memory together with a drive circuit-integrated display device with a built-in DAC circuit enables a significant reduction in IC cost.
[0328]
A second effect of the present invention is that the read frequency is reduced and the power consumption of the interface circuit is reduced by increasing the bus width from the memory built-in controller IC. In addition, reducing the number of intersections between wirings reduces the power consumption of the interface circuit.
[0329]
A third effect of the present invention is that the effect of EMI can be ignored. The reason is that the frequency of data processing has been reduced due to the use of a thick bus. When the processing frequency is reduced, EMI noise is drastically reduced, so that the influence of EMI can be ignored. Further, EMI noise is synergistically reduced because the data wiring length is shortened.
[0330]
A fourth effect of the present invention is that the inside of the substrate can be formed by the same process. Conventionally, when various circuit elements are formed, various processes have been used in accordance with the voltage used in each circuit group. In the present invention, since the frequency to be processed is low, even if all the circuit groups are created by a single process corresponding to the circuit group requiring the highest voltage, the operation can be performed without any problem. That the inside of the substrate can be formed by the same process means that, in other words, the gate insulating films of the transistors formed on the substrate all have the same structure, and their thicknesses can be made equal within the range of the process variation. That is, even if the threshold voltage of the transistor is set high for a high voltage, low voltage driving is possible because the frequency is low.
[0331]
A fifth effect of the present invention is that the reliability of the display device is improved. The reason is that in the present invention, the operating frequency of the circuit can be suppressed low. When the operating frequency is low, the stress applied to each element is reduced, so that the reliability is improved. In a simple estimation, the rate of decrease in frequency and the rate of increase in continuous available time are in a proportional relationship. That is, as the frequency decreases, the reliability improves. In addition, the fact that there is no influence of the above-mentioned EMI also plays a large role in improving reliability.
[0332]
A sixth effect of the present invention is that a voltage-current conversion circuit is provided, and a current driving element can be driven. With these effects, a high-definition, multi-tone, low-cost, low-power display device can be realized.
[0333]
A seventh effect of the present invention is that the layout area of the serial-parallel conversion circuit is reduced. This is because a multi-bit input multi-bit output serial-parallel conversion circuit is realized by arranging a plurality of 1-bit input serial-parallel conversion circuits. This is because it is only necessary to provide a wire for each pair, and it is not necessary to route a large number of data bus wires over the entire layout area of the serial-parallel conversion circuit with multi-bit input and multi-bit output as in the related art.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a display device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a timing operation of the display device according to the first embodiment of the present invention.
FIG. 3 is a diagram showing a relationship between a built-in memory capacity and an IC cost for a built-in memory driver IC and a built-in memory controller IC.
FIG. 4 is a diagram illustrating a relationship between a read frequency and interface circuit power consumption.
FIG. 5 is a diagram illustrating a configuration of a display device according to a second embodiment of the present invention.
FIG. 6 is a diagram illustrating a configuration of a display device according to a third embodiment of the present invention.
FIG. 7 is a diagram illustrating a configuration of a display device according to a fourth embodiment of the present invention.
FIG. 8 is a diagram illustrating a configuration of a display device according to a fifth embodiment of the present invention.
FIG. 9 is a diagram for explaining a timing operation of a display device according to a fifth embodiment of the present invention.
FIG. 10 is a diagram illustrating a configuration of a display device according to a sixth embodiment of the present invention.
FIG. 11 is a diagram illustrating a configuration of a display device according to a seventh embodiment of the present invention.
FIG. 12 is a diagram for explaining the timing operation of the display device according to the seventh embodiment of the present invention.
FIG. 13 is a diagram illustrating a configuration of a display device according to an eighth embodiment of the present invention.
FIG. 14 is a diagram illustrating a configuration of a display device according to a ninth embodiment of the present invention.
FIG. 15 is a diagram illustrating a configuration of a display device according to a tenth embodiment of the present invention.
FIG. 16 is a diagram for explaining a timing operation of the display device according to the tenth embodiment of the present invention.
FIG. 17 is a diagram illustrating a configuration of a display device according to an eleventh embodiment of the present invention.
FIG. 18 is a diagram illustrating a configuration of a display device according to a twelfth embodiment of the present invention.
FIG. 19 is a diagram illustrating a timing operation of the display device according to the twelfth embodiment of the present invention.
FIG. 20 is a diagram illustrating a configuration of a display device according to a thirteenth embodiment of the present invention.
FIG. 21 is a diagram illustrating a configuration of a display device according to a fourteenth embodiment of the present invention.
FIG. 22 is a diagram illustrating a configuration of a display device according to a fifteenth embodiment of the present invention.
FIG. 23 is a diagram illustrating a configuration of a display device according to a sixteenth embodiment of the present invention.
FIG. 24 is a diagram illustrating a timing operation of the display device according to the sixteenth embodiment of the present invention.
FIG. 25 is a diagram illustrating a configuration of a display device according to a seventeenth embodiment of the present invention.
FIG. 26 is a diagram illustrating a configuration of a display device according to an eighteenth embodiment of the present invention.
FIG. 27 is a diagram illustrating a timing operation of the display device according to the eighteenth embodiment of the present invention.
FIG. 28 is a diagram illustrating a configuration of a display device according to a nineteenth embodiment of the present invention.
FIG. 29 is a diagram illustrating a configuration of a display device according to a twentieth embodiment of the present invention.
FIG. 30 is a diagram illustrating a configuration of a display device according to a twenty-first embodiment of the present invention.
FIG. 31 is a diagram illustrating a timing operation of the display device according to the twenty-first embodiment of the present invention.
FIG. 32 is a diagram illustrating a configuration of a display device according to a twenty-second embodiment of the present invention.
FIG. 33 is a diagram illustrating a configuration of a display device according to a twenty-third embodiment of the present invention.
FIG. 34 is a diagram illustrating a configuration of a display device according to a twenty-fourth embodiment of the present invention.
FIG. 35 is a cross-sectional view for explaining main steps of manufacturing a display panel substrate used in the example of the present invention.
FIG. 36 is a cross-sectional view for explaining main steps of manufacturing a display panel substrate used in the example of the present invention.
FIG. 37 is a diagram showing an outline of a display system using a conventional liquid crystal display device integrated with a driving circuit.
FIG. 38 is a diagram showing an outline of a display system using a conventional drive circuit-integrated liquid crystal display device with a built-in DAC circuit.
FIG. 39 is a diagram showing a configuration of a display device to which a conventional architecture is applied as a comparative example.
40 is a diagram showing a circuit configuration of the shift register of FIG. 39.
FIG. 41 is a diagram showing a circuit configuration of a 6-bit data register of FIG. 39 and a digital data bus line connected thereto.
FIG. 42 is a diagram showing a circuit configuration of a 6 × 66 load latch of FIG. 39;
FIG. 43 is a timing chart of signals input to the shift register circuit and the digital data bus line in FIG. 39;
FIG. 44 is a diagram showing a circuit configuration of a conventional level conversion circuit.
FIG. 45 is a block diagram illustrating a configuration of a display device according to an embodiment of the present invention.
46 is a diagram showing a circuit configuration of a 1-to-2 serial / parallel conversion circuit with a level conversion function in the embodiment of the present invention shown in FIG. 45.
FIG. 47 is a timing chart showing a timing waveform of the 1-to-2 serial / parallel conversion circuit shown in FIG. 46;
FIG. 48 is a graph showing the measurement results of the maximum operating frequency of the 1-to-2 serial / parallel conversion circuit shown in FIG. 46;
FIG. 49 is a graph comparing the power consumption of the level conversion unit included in FIG. 46 and the conventional level conversion circuit shown in FIG. 44;
50 is a diagram comparing the power consumption of a digital signal processing unit integrated on a display substrate between the display device shown in FIG. 39 and the display device shown in FIG. 45.
FIG. 51 is a diagram showing a circuit configuration of a 1-bit input 2-bit output serial-parallel conversion circuit.
FIG. 52 is a diagram showing a circuit configuration of a serial-parallel conversion circuit with 1-bit input and 6-bit output.
FIG. 53 is a diagram showing a circuit configuration of a serial-parallel conversion circuit with 1-bit input and 6-bit output.
[Explanation of symbols]
10 Glass substrate
11 Silicon oxide film
12 Amorphous silicon
13 Silicon oxide film
14 Photoresist
15 Silicon oxide film
16 Microcrystal silicon (μ-c-Si)
17 Tungsten silicide (WSi) 17
18 Photoresist
19 silicon oxide film / silicon nitride film
20 Metals (aluminum and titanium)
21 Silicon nitride film
22 Pixel electrode (ITO)
30, 32, 33, 35, 36, 38, 39, 41, 48, 50, 52, 54, 56, 58 Clocked inverters
31, 34, 37, 40, 42, 43, 49, 51, 53, 55, 57 Inverter
61, 62, 63, 65, 67, 70, 72, 74, 76, 78, 80 Clocked inverter
57, 60, 63, 66, 68, 69, 71, 73, 75, 77, 79, 81, 82, 83, 84, 85 Inverter
101 Display device substrate
102 Controller IC
103 System side circuit board
104 level shifter
105 Latch circuit
106 DAC circuit
107 Selector circuit
108 level shifter / timing buffer
109 scanning circuit
110 Display
111 memory
112 output buffer
113 Controller
114 Interface Circuit
401 Timing buffer
511-515 Latch
701 Timing buffer
801 Voltage-current conversion circuit / current output buffer
1001 decoder
1002 Current output buffer
1801 serial / parallel conversion circuit
3501 Scanning circuit / data register
3502 DAC
3503 Level shifter
3504 Scanning circuit
3505 Analog switch
3506 Scanning circuit
3507 Data register

Claims (96)

A display panel unit having a display unit in which pixel groups are arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines;
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
A data line driving circuit that receives display data supplied from a host device and applies a signal corresponding to the display data to the plurality of data lines;
In the display device having
A display memory that stores display data, an output buffer that reads data from the display memory and outputs the read data to the display panel unit, a controller that controls the display memory and the output buffer, and controls communication and control with the higher-level device, Comprising a controller IC having
The display panel unit includes a digital / analog conversion circuit (referred to as a “DAC circuit”) which forms a part of the data line driving circuit and converts display data of a digital signal transferred from the controller device into an analog signal. ,
The width of the bus for data transfer between the controller IC and the display panel unit is such that more bit data is transferred in parallel per transfer than the bus between the controller and the host device. A display device having a configuration. A display panel unit having a display unit in which pixel groups are arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines;
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
A data line driving circuit that receives display data supplied from a host device and applies a signal corresponding to the display data to the plurality of data lines;
In the display device having
A display memory for storing display data in the display panel unit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) for converting display data of a digital signal read and transferred from the display memory into an analog signal;
With
The display device, wherein the DAC circuit and the display memory are formed by the same process as a process of forming a TFT (Thin Film Transistor) of a pixel switch of the display unit. 3. The display device according to claim 1, wherein the display panel unit includes a selector circuit having an output of the DAC circuit as an input and an output connected to a data line group. 4. 2. The display device according to claim 1, wherein the display panel unit includes a level shifter that level-shifts a signal amplitude defined by a power supply voltage of the controller IC to a high voltage on the display panel unit side. The display panel unit includes a serial-parallel conversion circuit that converts serial data to parallel data,
3. The display device according to claim 1, wherein the DAC circuit is supplied with data converted in parallel by the serial / parallel conversion circuit. The scanning line driving circuit is provided on both sides of the display unit, and a timing buffer for supplying a clock to the data line driving circuit is provided on both sides of the display unit. Display device. 3. The display panel unit according to claim 1, further comprising: a circuit that converts a voltage to a current, as a circuit constituting a part of the data line driving circuit, and drives the data line with a current. 4. Display device. The display device according to claim 1, wherein the display unit is made of a liquid crystal. The display device according to claim 1, wherein the display unit is made of an organic EL (electroluminescence). Transistors formed on the display panel and constituting peripheral circuits including the data line driving circuit and the scanning line driving circuit are formed in the same process as transistors forming pixel switches of the display unit formed on the display panel. The thickness of the gate insulating film of the transistor of the peripheral circuit including the data line driving circuit and the scanning line driving circuit is the same according to the thickness of the gate insulating film of the transistor driven at high voltage. The display device according to any one of claims 1 to 7, wherein the display device is set. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls communication and control with a higher-level device.
In the controller device, the output buffer is obtained by dividing (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × B) / S｝ pieces are arranged,
One horizontal ({N × B) / S} bit unit from the output buffer of the controller device to the display device substrate side via a {(N × B) / S} bit width data bus. During the period, the display data for one line is transferred by dividing into the block division number S times,
The display device substrate,
A level shifter that level-shifts the amplitude of the signal received from the data bus to a higher-amplitude signal and outputs the shifted signal;
A latch circuit for latching the output of the level shifter;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The level shifters and the latch circuits are each arranged {(N × B) / S},
(N / S) DAC circuits are arranged,
The selector circuit receives outputs of the (N / S) DAC circuits, and, based on a selector control signal, a time obtained by dividing one horizontal period by the block division number S for each output of the DAC circuits. Data signals are sequentially supplied to the S data line groups,
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
A latch clock signal boosted and output by the level shifter timing buffer and the selector control signal are respectively supplied to the latch circuit and the selector circuit;
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls communication and control with a higher-level device.
In the controller device, the output buffer is obtained by dividing (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × B) / S｝ pieces are arranged,
From the output buffer of the controller device, via the {(N × B) / S} bit width data bus, the display device substrate is supplied with {(N × B) / S} bits for one horizontal period. Then, the display data for one line is transferred after being divided into the block division number S times,
The display device substrate,
A latch circuit for latching a signal received from the data bus;
A level shifter that level-shifts the output amplitude of the latch circuit to a signal with a higher amplitude and outputs the signal;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the level shifter and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The level shifters and the latch circuits are each arranged {(N × B) / S},
(N / S) DAC circuits are arranged,
The selector circuit receives outputs of the (N / S) DAC circuits, and, based on a selector control signal, a time obtained by dividing one horizontal period by the block division number S for each output of the DAC circuits. Data signals are sequentially supplied to the S data line groups,
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
A latch clock signal boosted and output by the level shifter timing buffer and the selector control signal are respectively supplied to the latch circuit and the selector circuit;
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer is obtained by dividing (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × B) / S｝ pieces are arranged,
One horizontal ({N × B) / S} bit unit from the output buffer of the controller device to the display device substrate side via a {(N × B) / S} bit width data bus. During the period, the display data for one line is transferred by dividing into the block division number S times,
The display device substrate,
A latch circuit for latching a signal received from the data bus;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of the latch circuits as the number of the output buffers are {(N × B) / S}.
(N / S) DAC circuits are arranged,
The selector circuit receives outputs of the (N / S) DAC circuits, and, based on a selector control signal, a time obtained by dividing one horizontal period by the block division number S for each output of the DAC circuits. Data signals are sequentially supplied to the S data line groups,
The controller of the controller device supplies a clock signal to a timing buffer of the display device substrate, and a latch clock signal and the selector control signal from the timing buffer are supplied to the latch circuit and the selector circuit, respectively.
A display device characterized by the above-mentioned. A voltage-current conversion circuit that converts an output voltage of the DAC circuit into a current between the DAC circuit and the selector circuit; and a current that outputs the current converted by the voltage-current conversion circuit to the selector circuit. The display device according to claim 11, further comprising an output buffer, wherein a current is supplied to N data lines from N outputs of the selector circuit. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × N × B) B) / S｝ pieces are arranged,
From the output buffer of the controller device, via the {(N × B) / S} bit width data bus, the display device substrate is supplied with {(N × B) / S} bits for one horizontal period. Then, the display data for one line is transferred after being divided into the block division number S times,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A latch circuit for latching the output of the level shifter;
A decoder circuit for inputting a B-bit output of the latch circuit;
A current output buffer that receives an output of the decoder circuit as an input and outputs a current according to a decoding result;
A selector having an input of an output current of the current output buffer and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) / S number of the output buffers as the number of the level shifters and the latch circuits are arranged,
(N / S) decoder circuits are arranged,
The selector circuit receives the current outputs of the (N / S) current output buffer circuits, and, based on the selector control signal, sequentially outputs S data for each output in a time period divided into the block division number. Supply current to the wire group,
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
The latch clock signal and the selector control signal boosted by the level shifter timing buffer are supplied to the latch circuit and the selector circuit, respectively.
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
One transfer and one line of display data are transferred in parallel from the output buffer of the controller device to the display device substrate side via a (N × B) bit width data bus,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A latch circuit for latching the output of the level shifter;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number (N × B) of the output buffers as the level shifters and the latch circuits are arranged,
N DAC circuits are arranged,
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
A latch clock signal boosted by the level shifter timing buffer is supplied to the latch circuit.
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
One line of display data is transferred from the output buffer of the controller device to the display device substrate side in parallel by one transfer via the (N × B) bit width data bus,
The display device substrate,
A latch circuit for latching a low-amplitude signal received from the data bus;
A level shifter that level-shifts the amplitude of the output of the latch circuit to a signal having a higher amplitude,
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the level shifter and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) number of the level shifters and the latch circuits as the output buffer are arranged,
N DAC circuits are arranged,
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
A latch clock signal boosted by the level shifter timing buffer is supplied to the latch circuit.
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
From the output buffer of the controller device, one line of display data is transferred in one horizontal period to the display device substrate side via a (N × B) bit width data bus,
The display device substrate,
A latch circuit for latching a signal transferred to the data bus;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) latch circuits as the output buffers are arranged,
N DAC circuits are arranged,
The controller of the controller device supplies a clock signal to a timing buffer of the display device substrate,
A latch clock signal from the timing buffer is supplied to the latch circuit.
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
One line of display data is transferred from the output buffer of the controller device to the display device substrate side in parallel by one transfer via the (N × B) bit width data bus,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A latch circuit for latching the output of the level shifter;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A voltage-current conversion circuit / current output buffer circuit for inputting the output of the DAC circuit, performing voltage / current conversion, and outputting current to a corresponding data line;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number (N × B) of the output buffers as the level shifters and the latch circuits are arranged,
The DAC circuit and the voltage-current conversion circuit / current output buffer circuit are arranged in N pieces,
The controller of the controller device supplies a clock signal to a level shift timing buffer of the display device substrate,
A latch clock signal from the level shift timing buffer is supplied to the latch circuit.
A display device characterized by the above-mentioned. A decoder circuit for receiving and decoding the B-bit output of the latch circuit in place of the DAC circuit and the voltage-current conversion circuit / current output buffer circuit; 20. The display device according to claim 19, further comprising a current output buffer circuit that outputs a current to the line. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ are arranged,
Display data is transferred from the output buffer of the controller device to the display device substrate side via a {(N × B) / (P × S)} bit width data bus, and during one horizontal period, (N × B) / (P × S)｝ bit data is divided into (P × S) times, and display data for one line is transferred,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A serial / parallel conversion circuit for serially inputting the output of the level shifter, expanding the output into P-phase parallel bits, and outputting the result;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of {(N × B) / (P × S)} level shifters as the output buffers are arranged,
{(N × B) / S} latch circuits are arranged;
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs S outputs for each output of each DAC circuit based on a selector control signal in a time period divided into the block division number S. Supply data signals to the data lines
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
The latch clock signal boosted by the level shifter timing buffer, the selector control signal, and the serial / parallel conversion control signal are supplied to the latch circuit, the selector circuit, and the serial / parallel conversion circuit, respectively.
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ are arranged,
Display data is transferred from the output buffer of the controller device to the display device substrate side via a {(N × B) / (P × S)} bit width data bus, and during one horizontal period, (N × B) / (P × S)｝ bit data is divided into (P × S) times, and display data for one line is transferred.
A serial / parallel conversion circuit that serially inputs {(N × B) / (P × S)} bits of data transferred to the data bus and develops the data into P-phase parallel bits on the display device substrate When,
A latch circuit for latching an output of the serial / parallel conversion circuit;
A level shifter for level-shifting the output of the latch circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the level shifter and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (L × N) / (P × S) latch circuits as the output buffers are arranged,
{(N × B) / S} level shifters are arranged,
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs S outputs for each one output of the DAC circuit based on a selector control signal in a time period divided into the block division number S. Supply the data signal to the data line group of
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
The latch clock signal boosted by the level shifter timing buffer, the selector control signal, and the serial / parallel conversion control signal are supplied to the latch circuit, the selector circuit, and the serial / parallel conversion circuit, respectively.
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ are arranged,
Display data is transferred from the output buffer of the controller device to the display device substrate side via a data bus of {(N × B) / (P × S)} bit width, and during one horizontal period, {(N × B) / (P × S)} bit data is divided into (P × S) times and display data for one line is transferred,
The display device substrate,
A serial / parallel conversion circuit for serially inputting each bit data from the data bus and expanding the data into P-phase parallel bits;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of the latch circuits as the number of the output buffers are {(N × B) / S}.
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs the outputs of each of the DAC circuits based on a selector control signal in the time period divided into the block division number S by S. Supply data signals to the data lines
The controller of the controller device supplies a clock signal to a timing buffer of the display device substrate,
A latch clock signal, the selector control signal, and a serial / parallel conversion control signal from the timing buffer are supplied to the latch circuit, the selector circuit, and the serial / parallel conversion circuit, respectively.
A display device characterized by the above-mentioned. 24. The device according to claim 23, further comprising a voltage-current conversion circuit / current output buffer circuit that converts the output of the DAC circuit into a current and outputs a current between the DAC circuit and the selector. Display device. In place of the DAC circuit, a decoder circuit that inputs and decodes the outputs of the B latch circuits, and a current output buffer that outputs a current corresponding to a decode result output of the decoder circuit, comprises: 22. The display device according to claim 21, wherein (N / S) circuits are arranged between the selector and the selector. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
{(N × B) / P} output buffers are arranged in the controller device,
From the output buffer of the controller device, via a data bus of {(N × B) / P} bit width, the display device substrate side is divided into P times per horizontal period, and is divided into one line. Display data is transferred,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A serial-to-parallel conversion circuit for serially inputting the output of the level shifter and developing it into P-phase parallel bits;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of ((N × B) / P) level shifters as the output buffers are arranged,
(N × B) latch circuits are arranged,
N DAC circuits are arranged,
The controller of the controller device supplies a clock signal to a level shifter timing buffer of the display device substrate,
A latch clock signal and a serial / parallel conversion control signal boosted by the level shifter / timing buffer are supplied to the latch circuit and the serial / parallel conversion circuit, respectively.
A display device characterized by the above-mentioned. In the display device substrate,
Exchanging positions of the level shifter and the serial / parallel conversion circuit,
The serial / parallel conversion circuit serially inputs each bit signal of the data bus and develops the data signal into a P-phase parallel bit;
The level shifter level-shifts the amplitude of the output signal of the serial / parallel conversion circuit to a signal having a higher amplitude,
The DAC circuit inputs an output of the level shifter;
The display device according to claim 26, wherein: A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, {(N × B) / P} output buffers are arranged corresponding to the number obtained by dividing one row of (M × N × B) bits of the memory by P phase,
From the output buffer of the controller device, via a data bus of {(N × B) / P} bit width, the display device substrate side is divided into P times per horizontal period to display one line. The data is transferred,
The display device substrate,
A serial-to-parallel conversion circuit that serially inputs each bit data from the data bus, expands the data into P parallel bits, and outputs the data;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
(N × B) latch circuits are arranged,
N DAC circuits are arranged,
The controller of the controller device supplies a clock signal to a timing buffer of the display device substrate, and a latch clock signal and a serial / parallel conversion control signal from the timing buffer are supplied to the latch circuit and the serial / parallel conversion circuit, respectively. Supplied,
A display device characterized by the above-mentioned. 29. The display device according to claim 28, further comprising N voltage-current conversion circuits / current output buffers for inputting an output voltage of the DAC circuit, performing voltage-current conversion, and outputting a current. Instead of the DAC circuit, N decoder circuits each receiving and decoding the outputs of the B latch circuits, and N current output buffer circuits for outputting a current corresponding to the decoding result of the decoder circuit The display device according to claim 28, further comprising: A display unit having a pixel group in which a display device substrate is arranged in a matrix at M rows and N columns at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation;
An output buffer that reads data from the display memory and outputs the data to the display panel substrate side;
A controller that controls the display memory and the output buffer and controls communication and control with a higher-level device;
On the same substrate,
The output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase, and ｛(N × B) ) / (P × S)｝
On the display device substrate, further,
A serial / parallel conversion circuit that serially receives the output of the output buffer, expands the output into P-phase parallel bits, and outputs the result.
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
{(N × B) / (P × S)} serial / parallel conversion circuits are arranged,
{(N × B) / S} latch circuits are arranged;
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs S outputs for each output of each DAC circuit based on a selector control signal in a time period divided into the block division number S. Supply data signals to the data lines
A latch clock signal is supplied to the latch circuit from the controller, the selector control signal is supplied to the selector circuit, and a serial / parallel conversion control signal is supplied to the serial / parallel conversion circuit.
A display device characterized by the above-mentioned. A display unit having a pixel group in which a display device substrate is arranged in a matrix at M rows and N columns at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation;
An output buffer that reads data from the display memory and outputs the data to the display panel substrate side;
A controller that controls the display memory and the output buffer and controls communication and control with a higher-level device;
On the same substrate,
In the output buffer, (N × B) / P number of (N × B) bits corresponding to one row of (M × N × B) bits of the memory are divided by P phase. And
On the display device substrate, further,
A serial / parallel conversion circuit that serially receives the output of the output buffer, expands the output into P-phase parallel bits, and outputs the result.
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
{(N × B) / P} serial / parallel conversion circuits are arranged,
(N × B) latch circuits are arranged,
N DAC circuits are arranged,
A display device, wherein a latch clock signal is supplied from the controller to the latch circuit, and a serial / parallel conversion control signal is supplied to the serial / parallel conversion circuit. 33. The transistor according to claim 11, wherein a transistor forming a circuit formed on the display device substrate is manufactured by the same manufacturing process as a pixel switch of the display unit. Display device. A transistor forming a peripheral circuit including the data line driving circuit and the scanning line driving circuit formed on the display device substrate; a transistor forming a pixel switch of the display unit formed on the display device substrate; Formed in the same process,
The thickness of a gate insulating film of a transistor forming a peripheral circuit including the data line driving circuit and the scanning line driving circuit is the same as the thickness of a gate insulating film of a transistor forming the pixel switch. The display device according to any one of claims 11 to 32, characterized in that: At least a digital-to-analog conversion circuit for converting one line read from a display memory circuit for storing display data or one line into a plurality of parts and converting a digital signal transferred in parallel to an analog signal is provided. A display device including a data line driving circuit for applying an analog data signal to a plurality of data lines of the display unit,
The digital-to-analog conversion circuit, or the digital-to-analog conversion circuit and the display memory circuit are formed on the same substrate as the display unit,
Transistors constituting a circuit formed on the same substrate as the display portion are formed by the same process as a transistor forming a pixel switch of the display portion, and the gate insulating film has a thickness of the pixel switch. Wherein the thickness of the gate insulating film of the transistor is the same as that of the transistor. 36. The display device according to claim 10, wherein the transistor is formed of a polycrystalline silicon TFT (Thin Film Transistor). A display device having a data line driving circuit for receiving display data supplied from a higher-level device and applying a signal corresponding to the display data to a data line, wherein at least a circuit for transmitting a display signal in a circuit for phase-expanding the display data However, the display device does not intersect with a wiring which transmits another display signal. A display device having a circuit that receives display data supplied from a higher-level device and expands the display data,
The number C of intersections at which a certain signal line crosses another signal line for transmitting a signal before phase development is C = n (n-1) (k-1) / 2
(However, n indicates the degree of parallelism of the supplied display data, and k × n indicates the degree of parallelism of the display data after phase development.)
A display device that is less than the display device. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
From the output buffer of the controller device, (N × B) bits corresponding to one row of (M × N × B) bits of the display memory were divided by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ Digital display data is transferred to the display device substrate via a data bus having a bit width,
The display device substrate,
A data line driving circuit for driving a data line of the display unit,
P level shift circuits commonly connected to one data line of the data bus, wherein the amplitude of a P-phase signal output from the output buffer and sequentially received via the data line is provided. And a level shift circuit for level-shifting the P-phase serial bit data to a signal having a higher amplitude. A P-phase expansion circuit having a latch circuit that expands and latches output
From the {(N × B) / (P × S)} P-phase expansion circuits provided corresponding to the {(N × B) / (P × S)} bit width data bus, (N × B) / S｝ bit data is output in parallel,
(N / S) pieces are provided for {(N × B) / (P × S)} pieces of the P-phase expansion circuits. A digital-to-analog conversion circuit (referred to as "DAC circuit")
An output of the (N / S) DAC circuits is received as an input, and has N outputs connected to N data lines of the display unit, and outputs of the (N / S) DAC circuits. A selector for sequentially supplying the data to the data line group of the display unit at the time divided by the block division number S;
A display device comprising a data line driving circuit including: The digital video data of {(N × B) / (P × S)} bits is divided into (P × S) times for one line by the controller device via the data bus in one horizontal period. 40. The display device according to claim 39, wherein the display data is transferred to a data line driving circuit of the display device substrate. The P-phase expansion circuit includes, as the level shift circuit, first to third switch elements connected in series between a higher power supply and a lower power supply;
A first capacitor is connected to a connection point between the first switch element and the second switch element,
A fourth switch element connected between an input terminal to which an input signal is input and a control terminal of the third switch element;
A second capacitor is connected to a connection point between the control terminal of the third switch element and the fourth switch element,
In the first switch element and the second switch element, a first sampling control signal is commonly input to respective control terminals, and when one is on, the other is off,
A second sampling control signal is input to a control terminal of the fourth switch element,
40. The display circuit according to claim 39, further comprising a level shift circuit that directly or indirectly extracts a terminal voltage of the first capacitor as an output signal. The P-phase expansion circuit includes, as the level shift circuit, first to third switch elements connected in series between a higher power supply and a lower power supply;
A first capacitor is connected to a connection point between the first switch element and the second switch element,
A fourth switch element connected between an input terminal to which an input signal is input and a control terminal of the third switch element;
A second capacitor is connected to a connection point between the control terminal of the third switch element and the fourth switch element;
A first sampling control signal is commonly input to a control terminal of the first switch element and a control terminal of the second switch element,
When the first sampling control signal has a second logical value, the first switch element is turned on, the second switch element is turned off, and the first capacitor is connected to the power supply voltage of the higher power supply. Charged,
A second sampling control signal is input to a control terminal of the fourth switch element, and when the second sampling control signal has a first logical value, the fourth switch element is turned on, and the second sampling control signal is turned on. Is charged with the input signal voltage,
When the first sampling control signal has a first logical value, the first switch element is turned off, the second switch element is turned on, and the terminal voltage of the first capacitor at this time is directly 40. The display circuit according to claim 39, further comprising a level shift circuit extracted as an output signal. The P-phase expansion circuit comprises a two-phase expansion circuit;
The two-phase expansion circuit includes first and second level shift circuits whose input terminals are commonly connected to a data line,
The first level shift circuit includes first to third switch elements connected in series between a higher power supply and a lower power supply,
A first capacitor is connected to a connection point between the first switch element and the second switch element,
A fourth switch element connected between an input terminal to which an input signal is input and a control terminal of the third switch element;
A second capacitor is connected to a connection point between the control terminal of the third switch element and the fourth switch element;
A first sampling control signal is commonly input to a control terminal of the first switch element and a control terminal of the second switch element,
When the first sampling control signal has a second logical value, the first switch element is turned on, the second switch element is turned off, and the first capacitor is connected to the power supply voltage of the higher power supply. Charged,
A second sampling control signal complementary to the first sampling control signal is input to a control terminal of the fourth switch element, and when the second sampling control signal has a first logical value, the fourth sampling control signal Is turned on, the second capacitor is charged with the input signal voltage,
When the first sampling control signal has a first logical value, the first switch element is turned off, the second switch element is turned on, and the terminal voltage of the first capacitor at this time is directly Or indirectly, as an output signal,
The second level shift circuit has the same circuit configuration as the first level shift circuit,
An input signal is commonly input to the first and second level shift circuits,
The second sampling control signal is commonly input to the control terminal of the first switch element and the control terminal of the second switch element of the second level shift circuit. The first sampling control signal is input to a control terminal of the fourth switch element,
A first master-slave type latch that captures an output of the first level shift circuit based on the first sampling control signal and outputs the output based on the second sampling control signal;
A latch that outputs an output of the first master-slave type latch based on the first sampling control signal;
A second master-slave type latch that captures an output of the second level shift circuit based on the second sampling control signal and outputs the output based on the first sampling control signal;
40. The display circuit according to claim 39, comprising: A display panel unit having a display unit in which pixel groups are arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines;
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
A data line driving circuit that receives display data supplied from a host device and applies a signal corresponding to the display data to the plurality of data lines;
In the display device having
A display memory that stores display data, an output buffer that reads data from the display memory and outputs the read data to the display panel unit, a controller that controls the display memory and the output buffer, and controls communication and control with the higher-level device, Comprising a controller IC having
The display panel unit, comprising a part of the data line drive circuit, a voltage-current conversion circuit for converting display data of a digital signal transferred from the controller device to an analog current signal,
The width of the bus for data transfer between the controller IC and the display panel unit is such that more bit data is transferred in parallel per transfer than the bus between the controller and the host device. A display device having a configuration. A display panel unit having a display unit in which pixel groups are arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines;
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
A data line driving circuit that receives display data supplied from a host device and applies a signal corresponding to the display data to the plurality of data lines;
In the display device having
The display panel unit, at least, a display memory for storing display data,
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) for converting display data of a digital signal read and transferred from the display memory into an analog signal;
A display device comprising: A display panel unit having a display unit in which pixel groups are arranged in a matrix at intersections of a plurality of data lines and a plurality of scanning lines;
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
A data line driving circuit that receives display data supplied from a host device and applies a signal corresponding to the display data to the plurality of data lines;
In the display device having
The display panel unit, at least, a display memory for storing display data,
A voltage / current conversion circuit for converting display data of a digital signal read and transferred from the display memory into an analog current signal,
A display device comprising: 46. The display device according to claim 45, wherein the display panel unit includes a selector circuit having an output of the DAC circuit as an input and an output connected to a data line group. The display device according to claim 44, wherein the display panel unit includes a level shifter for level-shifting a signal amplitude defined by a power supply voltage of the controller IC to a higher voltage on the display panel unit side. The display panel unit includes a serial-parallel conversion circuit that converts serial data to parallel data,
46. The display device according to claim 45, wherein the DAC circuit is supplied with data converted in parallel by the serial / parallel conversion circuit. 47. The display device according to claim 44, further comprising the scanning line driving circuit on both sides of the display unit, and timing buffers for supplying a clock to the data line driving circuit on both sides of the display unit. The display device according to claim 1. 47. The display panel unit according to claim 44, further comprising a circuit for converting a voltage to a current as a circuit constituting a part of the data line driving circuit, and driving the data line with a current. The display device according to claim 1. 47. The display device according to claim 44, wherein the display unit is made of a liquid crystal. The display device according to any one of claims 44 to 46, wherein the display unit is made of organic EL (electroluminescence). The gate insulating films of the respective transistors forming the display portion, the data line driving circuit portion, and the scanning line driving circuit portion formed on the display panel portion have the same structure, and the thickness thereof is different from the process variation. The display device according to any one of claims 1 to 4, and 44 to 46, wherein the display device is equal within a range. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls communication and control with a higher-level device.
In the controller device, the output buffer is obtained by dividing (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × B) / S｝ pieces are arranged,
One horizontal ({N × B) / S} bit unit from the output buffer of the controller device to the display device substrate side via a {(N × B) / S} bit width data bus. During the period, the display data for one line is transferred by dividing into the block division number S times,
The display device substrate,
A level shifter that level-shifts the amplitude of the signal received from the data bus to a higher-amplitude signal and outputs the shifted signal;
A latch circuit for latching the output of the level shifter;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The level shifters and the latch circuits are each arranged {(N × B) / S},
(N / S) DAC circuits are arranged,
The selector circuit receives outputs of the (N / S) DAC circuits, and, based on a selector control signal, a time obtained by dividing one horizontal period by the block division number S for each output of the DAC circuits. Sequentially supplying data signals to the S data line groups;
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls communication and control with a higher-level device.
In the controller device, the output buffer is obtained by dividing (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × B) / S｝ pieces are arranged,
From the output buffer of the controller device, via the {(N × B) / S} bit width data bus, the display device substrate is supplied with {(N × B) / S} bits for one horizontal period. Then, the display data for one line is transferred after being divided into the block division number S times,
The display device substrate,
A latch circuit for latching a signal received from the data bus;
A level shifter that level-shifts the output amplitude of the latch circuit to a signal with a higher amplitude and outputs the signal;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the level shifter and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The level shifters and the latch circuits are each arranged {(N × B) / S},
(N / S) DAC circuits are arranged,
The selector circuit receives outputs of the (N / S) DAC circuits, and, based on a selector control signal, a time obtained by dividing one horizontal period by the block division number S for each output of the DAC circuits. Sequentially supplying data signals to the S data line groups;
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer is obtained by dividing (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × B) / S｝ pieces are arranged,
One horizontal ({N × B) / S} bit unit from the output buffer of the controller device to the display device substrate side via a {(N × B) / S} bit width data bus. During the period, the display data for one line is transferred by dividing into the block division number S times,
The display device substrate,
A latch circuit for latching a signal received from the data bus;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of the latch circuits as the number of the output buffers are {(N × B) / S}.
(N / S) DAC circuits are arranged,
The selector circuit receives outputs of the (N / S) DAC circuits, and, based on a selector control signal, a time obtained by dividing one horizontal period by the block division number S for each output of the DAC circuits. Sequentially supplying data signals to the S data line groups;
A display device characterized by the above-mentioned. A voltage-current conversion circuit that converts an output voltage of the DAC circuit into a current between the DAC circuit and the selector circuit; and a current that outputs the current converted by the voltage-current conversion circuit to the selector circuit. 58. The display device according to claim 55, further comprising an output buffer, wherein a current is supplied to N data lines from N outputs of the selector circuit. A voltage / current conversion circuit for converting display data of a digital voltage signal into an analog current signal in place of the DAC circuit, wherein current is supplied to N data lines from N outputs of the selector circuit; The display device according to any one of claims 11 to 13, and 55 to 57. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row out of (M × N × B) bits of the memory by the number of block divisions S (N × N × B) B) / S｝ pieces are arranged,
From the output buffer of the controller device, via the {(N × B) / S} bit width data bus, the display device substrate is supplied with {(N × B) / S} bits for one horizontal period. Then, the display data for one line is transferred after being divided into the block division number S times,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A latch circuit for latching the output of the level shifter;
A decoder circuit for inputting a B-bit output of the latch circuit;
A current output buffer that receives an output of the decoder circuit as an input and outputs a current according to a decoding result;
A selector having an input of an output current of the current output buffer and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) / S number of the output buffers as the number of the level shifters and the latch circuits are arranged,
(N / S) decoder circuits are arranged,
The selector circuit receives the current outputs of the (N / S) current output buffer circuits, and, based on the selector control signal, sequentially outputs S data for each output in a time period divided into the block division number. Supply current to the wire group,
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
One line of display data is transferred from the output buffer of the controller device to the display device substrate side in parallel by one transfer via the (N × B) bit width data bus,
The display device substrate,
A latch circuit for latching a low-amplitude signal received from the data bus;
A level shifter that level-shifts the amplitude of the output of the latch circuit to a signal having a higher amplitude,
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the level shifter and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) number of the level shifters and the latch circuits as the output buffer are arranged,
N DAC circuits are arranged,
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
From the output buffer of the controller device, one line of display data is transferred in one horizontal period to the display device substrate side via a (N × B) bit width data bus,
The display device substrate,
A latch circuit for latching a signal transferred to the data bus;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) latch circuits as the output buffers are arranged,
N DAC circuits are arranged,
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
From the output buffer of the controller device, one line of display data is transferred in one horizontal period to the display device substrate side via a (N × B) bit width data bus,
The display device substrate,
A latch circuit for latching a signal transferred to the data bus;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (N × B) latch circuits as the output buffers are arranged,
N DAC circuits are arranged,
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, (N × B) output buffers corresponding to one row of (M × N × B) bits of the memory are arranged,
One line of display data is transferred from the output buffer of the controller device to the display device substrate side in parallel by one transfer via the (N × B) bit width data bus,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A latch circuit for latching the output of the level shifter;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A voltage-current conversion circuit / current output buffer circuit for inputting the output of the DAC circuit, performing voltage / current conversion, and outputting current to a corresponding data line;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number (N × B) of the output buffers as the level shifters and the latch circuits are arranged,
The DAC circuit and the voltage-current conversion circuit / current output buffer circuit are arranged in N pieces.
A display device characterized by the above-mentioned. A voltage / current conversion circuit for inputting a B-bit output of the latch circuit and converting the output into an analog current signal instead of the DAC circuit and the voltage-current conversion circuit / current output buffer circuit. The display device according to claim 64, wherein: A decoder circuit for receiving and decoding the B-bit output of the latch circuit in place of the DAC circuit and the voltage-current conversion circuit / current output buffer circuit; The display device according to claim 64, further comprising a current output buffer circuit that outputs a current to the line. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ are arranged,
Display data is transferred from the output buffer of the controller device to the display device substrate side via a {(N × B) / (P × S)} bit width data bus, and during one horizontal period, (N × B) / (P × S)｝ bit data is divided into (P × S) times, and display data for one line is transferred,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A serial / parallel conversion circuit for serially inputting the output of the level shifter, expanding the output into P-phase parallel bits, and outputting the result;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of {(N × B) / (P × S)} level shifters as the output buffers are arranged,
{(N × B) / S} latch circuits are arranged;
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs S outputs for each output of the DAC circuits based on a selector control signal in a time period divided into the block division number S. Supply data signals to the data line group of
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ are arranged,
Display data is transferred from the output buffer of the controller device to the display device substrate side via a {(N × B) / (P × S)} bit width data bus, and during one horizontal period, (N × B) / (P × S)｝ bit data is divided into (P × S) times, and display data for one line is transferred.
A serial / parallel conversion circuit that serially inputs {(N × B) / (P × S)} bits of data transferred to the data bus and develops the data into P-phase parallel bits on the display device substrate When,
A latch circuit for latching an output of the serial / parallel conversion circuit;
A level shifter for level-shifting the output of the latch circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the level shifter and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of (L × N) / (P × S) latch circuits as the output buffers are arranged,
{(N × B) / S} level shifters are arranged,
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs S outputs for each one output of the DAC circuit based on a selector control signal in a time period divided into the block division number S. Supply data signals to the data line group of
A display device characterized by the above-mentioned. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, the output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ are arranged,
Display data is transferred from the output buffer of the controller device to the display device substrate side via a data bus of {(N × B) / (P × S)} bit width, and during one horizontal period, {(N × B) / (P × S)} bit data is divided into (P × S) times and display data for one line is transferred,
The display device substrate,
A serial / parallel conversion circuit for serially inputting each bit data from the data bus and expanding the data into P-phase parallel bits;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
{(N × B) / S} latch circuits are arranged;
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially receives the outputs of the DAC circuits for one output of each of the DAC circuits based on a selector control signal for the time divided into the block division number S, and sequentially outputs S. Supply data signals to the group of data lines,
A display device characterized by the above-mentioned. 70. A voltage-current conversion circuit / current output buffer circuit that converts the output of the DAC circuit into a voltage and a current and outputs a current between the DAC circuit and the selector. The display device according to any one of the above. The display according to any one of claims 67 to 69, further comprising a voltage / current conversion circuit that inputs an output of the latch circuit and converts the output from the latch circuit into an analog current signal, instead of the DAC circuit. apparatus. In place of the DAC circuit, a decoder circuit that inputs and decodes the outputs of the B latch circuits, and a current output buffer that outputs a current corresponding to a decode result output of the decoder circuit, comprises: The display device according to any one of claims 67 to 69, wherein (N / S) circuits are respectively arranged between the selector and the selector. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
{(N × B) / P} output buffers are arranged in the controller device,
From the output buffer of the controller device, via a data bus of {(N × B) / P} bit width, the display device substrate side is divided into P times per horizontal period, and is divided into one line. Display data is transferred,
The display device substrate,
A level shifter for level-shifting the amplitude of the signal received from the data bus to a signal of a higher amplitude,
A serial-to-parallel conversion circuit for serially inputting the output of the level shifter and developing it into P-phase parallel bits;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
The same number of ((N × B) / P) level shifters as the output buffers are arranged,
(N × B) latch circuits are arranged,
N DAC circuits are arranged,
A display device characterized by the above-mentioned. In the display device substrate,
Exchanging positions of the level shifter and the serial / parallel conversion circuit,
The serial / parallel conversion circuit serially inputs each bit signal of the data bus and develops the data signal into a P-phase parallel bit;
The level shifter level-shifts the amplitude of the output signal of the serial / parallel conversion circuit to a signal having a higher amplitude,
The DAC circuit inputs an output of the level shifter;
The display device according to claim 73, wherein: A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
In the controller device, {(N × B) / P} output buffers are arranged corresponding to the number obtained by dividing one row of (M × N × B) bits of the memory by P phase,
From the output buffer of the controller device, via a data bus of {(N × B) / P} bit width, the display device substrate side is divided into P times per horizontal period to display one line. The data is transferred,
The display device substrate,
A serial-to-parallel conversion circuit that serially inputs each bit data from the data bus, expands the data into P parallel bits, and outputs the data;
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
(N × B) latch circuits are arranged,
N DAC circuits are arranged,
A display device characterized by the above-mentioned. 76. The display device according to claim 75, further comprising N voltage-current conversion circuits / current output buffers for inputting an output voltage of the DAC circuit, performing voltage-current conversion, and outputting a current. 76. The display device according to claim 75, further comprising a voltage / current conversion circuit that inputs an output of the latch circuit and converts the output to an analog current signal, instead of the DAC circuit. Instead of the DAC circuit, N decoder circuits each receiving and decoding the outputs of the B latch circuits, and N current output buffer circuits for outputting a current corresponding to the decoding result of the decoder circuit The display device according to claim 75, further comprising: A display unit having a pixel group in which a display device substrate is arranged in a matrix at M rows and N columns at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation;
An output buffer that reads data from the display memory and outputs the data to the display panel substrate side;
A controller that controls the display memory and the output buffer and controls communication and control with a higher-level device;
On the same substrate,
The output buffer divides (N × B) bits corresponding to one row of (M × N × B) bits of the memory by the number of block division numbers S and the P phase, and ｛(N × B) ) / (P × S)｝
On the display device substrate, further,
A serial / parallel conversion circuit that serially receives the output of the output buffer, expands the output into P-phase parallel bits, and outputs the result.
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A selector having an input of the output of the DAC circuit and having the same N outputs as the N columns of the display unit;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
{(N × B) / (P × S)} serial / parallel conversion circuits are arranged,
{(N × B) / S} latch circuits are arranged;
(N / S) DAC circuits are arranged,
The selector circuit receives the outputs of the (N / S) DAC circuits, and sequentially outputs S outputs for each output of the DAC circuits based on a selector control signal in a time period divided into the block division number S. Supply data signals to the data line group of
A display device characterized by the above-mentioned. A display unit having a pixel group in which a display device substrate is arranged in a matrix at M rows and N columns at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation;
An output buffer that reads data from the display memory and outputs the data to the display panel substrate side;
A controller that controls the display memory and the output buffer and controls communication and control with a higher-level device;
On the same substrate,
In the output buffer, (N × B) / P number of (N × B) bits corresponding to one row of (M × N × B) bits of the memory are divided by P phase. And
On the display device substrate, further,
A serial / parallel conversion circuit that serially receives the output of the output buffer, expands the output into P-phase parallel bits, and outputs the result.
A latch circuit for latching an output of the serial / parallel conversion circuit;
A digital-to-analog conversion circuit (referred to as a “DAC circuit”) that receives a B-bit output of the latch circuit and outputs an analog signal;
A data line drive circuit including:
A scanning line driving circuit that sequentially applies a voltage to the plurality of scanning lines;
With
{(N × B) / P} serial / parallel conversion circuits are arranged,
(N × B) latch circuits are arranged,
N DAC circuits are arranged,
A display device characterized by the above-mentioned. 81. The transistor according to any one of claims 55 to 80, wherein a transistor forming a circuit formed on the display device substrate is manufactured by the same manufacturing process as a pixel switch of the display unit. Display device. A transistor forming a peripheral circuit including the data line driving circuit and the scanning line driving circuit formed on the display device substrate; a transistor forming a pixel switch of the display unit formed on the display device substrate; Formed in the same process,
The thickness of a gate insulating film of a transistor constituting a peripheral circuit including the data line driving circuit and the scanning line driving circuit is the same as the thickness of a gate insulating film of a transistor forming the pixel switch. The display device according to any one of claims 55 to 80, characterized in that: The gate insulating films of the respective transistors forming the display portion, the data line drive circuit portion, and the scan line drive circuit portion formed on the display device substrate have the same structure, and the thickness thereof is a process variation. The display device according to any one of claims 11 to 32 and 55 to 80, wherein the display device is equal within the range. At least a digital-to-analog conversion circuit for converting one line read from a display memory circuit for storing display data or one line into a plurality of parts and converting a digital signal transferred in parallel to an analog signal is provided. A display device including a data line driving circuit for applying an analog data signal to a plurality of data lines of the display unit,
The digital-to-analog conversion circuit, or the digital-to-analog conversion circuit and the display memory circuit are formed on the same substrate as the display unit,
A transistor forming a circuit formed on the same substrate as the display unit and a gate insulating film of a transistor forming a pixel switch of the display unit have the same structure and the same film thickness within a range of process variation. A display device characterized by the above-mentioned. 85. The display device according to claim 54, wherein the transistor is formed of a polycrystalline silicon TFT (Thin Film Transistor). A semiconductor device having a data line driving circuit for receiving data supplied from a higher-level device and applying a signal corresponding to the data to a data line, and at least in a circuit for expanding data, a wiring for transmitting a data signal includes: A semiconductor device which does not intersect with a wiring which transmits another data signal. A semiconductor device having a circuit for receiving data supplied from a higher-level device and expanding the data in phases,
The number C of intersections at which a certain signal line crosses another signal line for transmitting a signal before phase development is C = n (n-1) (k-1) / 2
(However, n indicates the degree of parallelism of the supplied data, and k × n indicates the degree of parallelism of the data after phase development.)
Semiconductor device. A display device substrate including a display unit having a pixel group arranged in M rows and N columns in a matrix at intersections of a plurality of data lines (N lines) and a plurality of scanning lines (M lines);
A display memory for storing (M × N) pixels (ie, (M × N × B) bits) of display data of B-bit gradation, and an output buffer for reading data from the display memory and outputting the data to the display panel substrate side And a controller that controls the display memory and the output buffer, and controls and communicates with and controls a higher-level device.
From the output buffer of the controller device, (N × B) bits corresponding to one row of (M × N × B) bits of the display memory were divided by the number of block division numbers S and the P phase. (N × B) / (P × S)｝ Digital display data is transferred to the display device substrate via a data bus having a bit width,
The display device substrate,
A data line driving circuit for driving a data line of the display unit,
P level shift circuits commonly connected to one data line of the data bus, the P level shift circuits each being configured to control the amplitude of a signal output from the output buffer and sequentially received through the data line. A level shift circuit for level-shifting to a signal having a high amplitude; and a latch circuit for latching outputs of the P number of the level shift circuits in accordance with a drive clock, developing the data into level-shifted P-bit parallel data, and outputting the data. Equipped with a P-phase expansion circuit,
From the {(N × B) / (P × S)} P-phase expansion circuits provided corresponding to the {(N × B) / (P × S)} bit width data bus, (N × B) / S｝ bit data is output in parallel,
(N / S) pieces are provided for {(N × B) / (P × S)} pieces of the P-phase expansion circuits. A digital-to-analog conversion circuit (referred to as "DAC circuit")
An output of the (N / S) DAC circuits is received as an input, and has N outputs connected to N data lines of the display unit, and outputs of the (N / S) DAC circuits. A selector for sequentially supplying the data to the data line group of the display unit at the time divided by the block division number S;
A display device comprising a data line driving circuit including: The digital video data of {(N × B) / (P × S)} bits is divided into (P × S) times for one line by the controller device via the data bus in one horizontal period. The display device according to claim 88, wherein the display data is transferred to a data line driving circuit of the display device substrate. The P-phase expansion circuit includes, as the level shift circuit, first to third switch elements connected in series between a higher power supply and a lower power supply;
A first capacitor is connected to a connection point between the first switch element and the second switch element,
A fourth switch element connected between an input terminal to which an input signal is input and a control terminal of the third switch element;
A second capacitor is connected to a connection point between the control terminal of the third switch element and the fourth switch element,
In the first switch element and the second switch element, a first sampling control signal is commonly input to respective control terminals, and when one is on, the other is off,
A second sampling control signal is input to a control terminal of the fourth switch element,
90. The display circuit according to claim 88, further comprising a level shift circuit that directly or indirectly extracts a terminal voltage of the first capacitor as an output signal. The P-phase expansion circuit includes, as the level shift circuit, first to third switch elements connected in series between a higher power supply and a lower power supply;
A first capacitor is connected to a connection point between the first switch element and the second switch element,
A fourth switch element connected between an input terminal to which an input signal is input and a control terminal of the third switch element;
A second capacitor is connected to a connection point between the control terminal of the third switch element and the fourth switch element;
A first sampling control signal is commonly input to a control terminal of the first switch element and a control terminal of the second switch element,
When the first sampling control signal has a second logical value, the first switch element is turned on, the second switch element is turned off, and the first capacitor is connected to the power supply voltage of the higher power supply. Charged,
A second sampling control signal is input to a control terminal of the fourth switch element, and when the second sampling control signal has a first logical value, the fourth switch element is turned on, and the second sampling control signal is turned on. Is charged with the input signal voltage,
When the first sampling control signal has a first logical value, the first switch element is turned off, the second switch element is turned on, and the terminal voltage of the first capacitor at this time is directly 90. The display circuit according to claim 88, further comprising a level shift circuit which is extracted as an output signal. The P-phase expansion circuit comprises a two-phase expansion circuit;
The two-phase expansion circuit includes first and second level shift circuits whose input terminals are commonly connected to a data line,
The first level shift circuit includes first to third switch elements connected in series between a higher power supply and a lower power supply,
A first capacitor is connected to a connection point between the first switch element and the second switch element,
A fourth switch element connected between an input terminal to which an input signal is input and a control terminal of the third switch element;
A second capacitor is connected to a connection point between the control terminal of the third switch element and the fourth switch element;
A first sampling control signal is commonly input to a control terminal of the first switch element and a control terminal of the second switch element,
When the first sampling control signal has a second logical value, the first switch element is turned on, the second switch element is turned off, and the first capacitor is connected to the power supply voltage of the higher power supply. Charged,
A second sampling control signal complementary to the first sampling control signal is input to a control terminal of the fourth switch element, and when the second sampling control signal has a first logical value, the fourth sampling control signal Is turned on, the second capacitor is charged with the input signal voltage,
When the first sampling control signal has a first logical value, the first switch element is turned off, the second switch element is turned on, and the terminal voltage of the first capacitor at this time is directly Or indirectly, as an output signal,
The second level shift circuit has the same circuit configuration as the first level shift circuit,
An input signal is commonly input to the first and second level shift circuits,
The second sampling control signal is commonly input to the control terminal of the first switch element and the control terminal of the second switch element of the second level shift circuit. The first sampling control signal is input to a control terminal of the fourth switch element,
A first master-slave type latch that captures an output of the first level shift circuit based on the first sampling control signal and outputs the output based on the second sampling control signal;
A latch that outputs an output of the first master-slave type latch based on the first sampling control signal;
A second master-slave type latch that captures an output of the second level shift circuit based on the second sampling control signal and outputs the output based on the first sampling control signal;
90. The display circuit according to claim 88, comprising: A driven element array section in which the driven elements are formed in an array,
A serial-parallel conversion circuit function having a 2-bit or more input number for parallel processing of data for driving the driven element;
A semiconductor device having
2. The semiconductor device according to claim 1, wherein the serial-parallel conversion circuit function having the number of inputs of 2 bits or more includes a plurality of 1-bit input serial-parallel conversion circuits. The semiconductor device according to claim 93, wherein at least two of the plurality of 1-bit input serial-parallel conversion circuits are simultaneously driven by a commonly connected control line. A driven element array section in which the driven elements are formed in an array,
A drive circuit for writing an electric signal to the driven element,
A serial-parallel conversion circuit function having a number of inputs of 2 bits or more to parallelize data;
A semiconductor device comprising:
An output node group that outputs a signal obtained by performing serial-parallel conversion on data input to an input node of the serial-parallel conversion circuit;
A semiconductor device, wherein an output node group that outputs a signal obtained by performing serial-parallel conversion on data input to an input node adjacent to the input node is adjacent to the input node. A driven element array section in which the driven elements are formed in an array,
A drive circuit for writing an electric signal to the driven element,
A serial-parallel conversion circuit function having a number of inputs of 2 bits or more to parallelize data;
A semiconductor device comprising:
The circuit having the serial-parallel conversion circuit function is laid out in a rectangular shape,
An input node group is provided on one of the long sides of the rectangle,
A semiconductor device, wherein an output node group is provided on another long side.

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