WO2013038978A1 - Signal transmission device and signal transmission method - Google Patents

Signal transmission device and signal transmission method Download PDF

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Publication number
WO2013038978A1
WO2013038978A1 PCT/JP2012/072697 JP2012072697W WO2013038978A1 WO 2013038978 A1 WO2013038978 A1 WO 2013038978A1 JP 2012072697 W JP2012072697 W JP 2012072697W WO 2013038978 A1 WO2013038978 A1 WO 2013038978A1
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WIPO (PCT)
Prior art keywords
transmission
signal
reception
level
data
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PCT/JP2012/072697
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French (fr)
Japanese (ja)
Inventor
進吾 野村
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シャープ株式会社
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Publication of WO2013038978A1 publication Critical patent/WO2013038978A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J7/00—Multiplex systems in which the amplitudes or durations of the signals in individual channels are characteristic of those channels

Definitions

  • the present invention relates to a signal transmission device and a signal transmission method, and more particularly, to a signal transmission device and a signal transmission method suitable for transmitting a plurality of types of data.
  • LVDS Low Voltage Differential Signaling
  • a level shift circuit is provided in the input portion of the source driver, and the amplitude of data serially transmitted from the output buffer of the controller IC to the source driver is set to the level.
  • a display device that boosts voltage by a shift circuit is disclosed. According to such a configuration, since the amplitude of data to be transmitted from the controller IC to the source driver can be reduced, data transmission with low power consumption can be realized as in the case of the LVDS.
  • an object of the present invention is to provide a signal transmission device and a signal transmission method that can transmit a plurality of data while suppressing an increase in cost.
  • a first aspect of the present invention is a signal transmission device that serially transmits a plurality of types of data between a transmission unit and a reception unit through a single transmission line
  • the transmitter is To receive a first clock signal that periodically changes, a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more), and N transmission-side data signals to be transmitted from the outside.
  • the sending input terminal of The N transmission-side data signals are sequentially sampled in synchronization with the second clock signal every one cycle of the first clock signal, and the voltage levels of the sampled N transmission-side data signals are made different from each other.
  • a transmission side signal processing unit for generating a transmission signal by A transmission side output terminal for outputting the transmission signal to the transmission line
  • the receiver is A receiving-side input terminal for receiving the first clock signal, the second clock signal, and the transmission signal from the transmission path;
  • the transmission signal is sampled in synchronization with the second clock signal for each cycle of the first clock signal, and the voltage levels of the sampled transmission signal are set to the N transmission sides before the voltage level changes.
  • a receiving-side signal processing unit that generates N receiving-side data signals by changing to a voltage level corresponding to the data signal;
  • a reception side output terminal for outputting the N reception side data signals to the outside.
  • the transmission-side signal processing unit includes a transmission-side phase control unit that varies the phases of the N transmission-side data signals by a period corresponding to one cycle of the second clock signal in synchronization with the second clock signal. It is characterized by that.
  • the transmission-side signal processing unit samples the N transmission-side data signals in synchronization with the second clock signal every cycle of the first clock signal, and the voltage level of each transmission data signal is transmitted.
  • the voltage level of the transmission data signal By converting the voltage level of the transmission data signal into one or the other of any two voltage levels of the N + 1 predetermined voltage levels, respectively, It further includes a transmission signal converter that generates the transmission signal having N + 1 types of voltage levels.
  • the transmission signal converting unit further converts a transmission-side second level of a preceding transmission-side data signal out of two transmission-side data signals in which periods to be sampled in each cycle of the first clock signal are continuous.
  • the subsequent voltage level and the voltage level after the conversion of the transmission side first level of the subsequent transmission side data signal are made the same.
  • the transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device.
  • the reception-side signal processing unit samples the transmission signal in synchronization with the second clock signal for each cycle of the first clock signal, and the transmission signal of the sampled voltage level of the transmission signal.
  • the voltage converted from the first level on the transmission side in the conversion unit is converted to the first level on the reception side corresponding to the first level on the transmission side, and the voltage level converted from the second level on the transmission side is converted to the transmission side.
  • a transmission signal inverse conversion unit that generates the N reception side data signals by converting the reception side second level corresponding to the second level is included.
  • a seventh aspect of the present invention is the sixth aspect of the present invention.
  • the reception-side signal processing unit further includes a reception-side phase control unit that synchronizes the N reception-side data signals with each other in synchronization with the second clock signal.
  • the transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device.
  • the transmission unit further includes a level shift signal generation unit that generates N level shift signals having different voltage levels.
  • the transmission-side signal processing unit is characterized in that the voltage levels of the sampled N transmission-side data signals are different from each other based on the N level-shifted signals.
  • a tenth aspect of the present invention is a signal transmission method in a signal transmission device that performs serial transmission of a plurality of types of data through a single transmission path between a transmission unit and a reception unit, N transmissions to be transmitted in synchronization with a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more) for each period of the periodically changing first clock signal.
  • the transmitter unit sequentially samples the N transmission-side data signals based on the timings of the first clock signal and the second clock signal, and changes their voltage levels.
  • the generated transmission signal is generated and transmitted from the transmitting unit to the receiving unit via one transmission path.
  • N reception-side data signals respectively corresponding to the voltage levels of the portions corresponding to the N transmission-side data signals in the transmission signal are based on the first clock signal and the second clock signal.
  • the voltage levels of the portions corresponding to the N transmission-side data signals in the transmission signal are different from each other. Based on the difference in level, for example, transmission defects can be reduced.
  • N pieces of data are reliably transmitted using one transmission path.
  • a plurality of types of data can be transmitted while suppressing an increase in cost.
  • the amount of data transmission per transmission line is increased, data transmission can be performed more efficiently than in the past.
  • N transmission-side data signals in each cycle of the first clock signal can be sampled in order.
  • the voltage level of the transmission side data signal when the voltage level of the transmission side data signal is the transmission side first level or the transmission side second level, the voltage level of the transmission side data signal is N + 1 predetermined values.
  • the type of the voltage level of the transmission signal becomes N + 1.
  • the transmitting side of the preceding transmitting side data signal out of the two transmitting side data signals in which the period to be sampled in each cycle of the first clock signal continues.
  • the voltage level after the two-level conversion is the same as the voltage level after the conversion of the transmission-side first level of the subsequent transmission-side data signal.
  • both the transmitter first level and the transmitter second level of the transmitter data signal to be sampled first in each period of the first clock signal should be sampled last in each period of the first clock signal. It is assumed that the transmission side data signal is larger than both the transmission side first level and the transmission side second level.
  • a reception unit that can generate N reception-side data signals from transmission signals having N + 1 types of voltage levels is used to change the voltage level of the transmission signal.
  • the first period of the second clock signal in each period of the first clock signal can be determined, the synchronization shift can be eliminated.
  • the transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device. For this reason, the scale of a transmission part can be reduced by sharing a common component with each other in a transmission side phase control part and a transmission signal conversion part.
  • each of the N transmission sides of the transmission signal in the first cycle to the Nth cycle of the second clock signal in each cycle of the first clock signal is sampled, and the voltage level of each of the N receiving data signals is determined based on the voltage level of the portion corresponding to the N transmitting data signals of the transmission signal.
  • the phases of N reception-side data signals can be aligned and output.
  • the transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device. For this reason, it is possible to reduce the size of the reception unit by sharing the common components in the transmission signal inverse conversion unit and the reception-side phase control unit.
  • a ninth aspect of the present invention by generating a voltage level for generating a transmission signal from N transmission-side data signals using a level shift signal generation unit, Similar effects can be achieved.
  • the same effect as in the first aspect of the present invention can be achieved.
  • 1 is a block diagram illustrating a configuration of a signal transmission system according to a first embodiment of the present invention. It is a block diagram which shows the structure of the transmission part in the said 1st Embodiment. It is a block diagram which shows the structure of the transmission side level control processor in the said 1st Embodiment. It is a block diagram which shows the structure of the receiving part in the said 1st Embodiment. It is a block diagram which shows the structure of the receiving side level control processor in the said 1st Embodiment. It is a signal waveform diagram which shows the transmission side data signal before the transmission side phase control process in the said 1st Embodiment.
  • FIG. 1 is a block diagram showing the configuration of the signal transmission system according to the present embodiment.
  • This signal transmission system is used, for example, for transmission of image data from a display control circuit in a display device to a source driver.
  • the signal transmission system includes a host 1 and a signal transmission device 2.
  • the host 1 is typically a CPU, and provides the signal transmission apparatus 2 with a transmission side control signal CT and a reception side control signal CR.
  • the three types of transmission side data signals DTa to DTc are referred to as first to third transmission side data signals, respectively, and the three types of reception side data signals DRa to DRc are respectively referred to as first to third reception side data signals. That's it.
  • the first to third transmission side data signals DTa to DTc and the first to third reception side data signals DRa to DRc are composed of bit strings.
  • system period and “sampling period”, respectively, and are denoted by symbols TA and TB, respectively, in the subsequent signal waveform diagrams.
  • the X (X is an integer of 2 or more) sampling period is represented by “XTB”.
  • the first to third sampling periods in each system period are referred to as “first to third sampling periods”, respectively.
  • the signal transmission device 2 includes a transmission unit 3, a reception unit 4, and a single transmission path 5 for connecting the transmission unit 3 and the reception unit 4 to each other.
  • the transmission line 5 may be either a differential transmission line or a single-ended transmission line.
  • “One transmission line” means a pair of transmission lines in the case of differential transmission.
  • the transmission unit 3 and the reception unit 4 are supplied with a power supply voltage by means not shown.
  • the transmission unit 3 receives the first to third transmission side data signals DTa to DTc, the system clock SYS, the sampling clock SAM, and the power supply voltage, and generates a transmission signal TS based on these.
  • the transmission signal TS is transmitted from the transmission unit 3 to the reception unit 4 via the transmission path 5.
  • the receiving unit 4 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the power supply voltage, and generates the first to third receiving side data signals DRa to DRc based on these. That is, in the signal transmission device 2, the three types of first to third transmission side data signals DTa to DTc received by the transmission unit 3 are respectively converted into three types of first to third reception side data signals DRa to DRc. Is transmitted.
  • FIG. 2 is a block diagram illustrating a configuration of the transmission unit 3 in the present embodiment.
  • the transmission unit 3 includes input terminals IT1, IT2, IT3a to IT3c, IT4a to IT4c, and IT5a to IT5c, an output terminal OT, a transmission side level shifter 30, and a transmission side level control processor 31.
  • the input terminals IT1, IT2, IT3a to IT3c correspond to transmission side input terminals.
  • the output terminal OT corresponds to the transmission side output terminal.
  • the input terminal IT1 is a terminal for receiving the system clock SYS.
  • the input terminal IT2 is a terminal for receiving the sampling clock SAM.
  • Input terminals IT3a to IT3c are terminals for receiving first to third transmission side data signals DTa to DTc, respectively.
  • Input terminals IT4a to IT4c are terminals for receiving first to third transmission side control signals CTa to CTc, respectively.
  • the input terminals IT5a to IT5c are terminals for receiving the transmission side first to third power supply voltages VHa to VHc as the power supply voltages, respectively.
  • the output terminal OT is a terminal for outputting the transmission signal TS.
  • the transmission-side first to third power supply voltages VHa to VHc have different voltage levels.
  • the voltage levels of the transmission-side first to third power supply voltages VHa to VHc may also be represented by VHa to VHc, respectively.
  • the magnitude relationship between the VHa to VHc levels is VHa> VHb> VHc.
  • the transmission side level shifter 30 receives the first to third transmission side control signals CTa to CTc and the transmission side first to third power supply voltages VHa to VHc, and sets the voltage levels of the first to third transmission side control signals CTa to CTc.
  • First to third transmission side level shift signals LSTa to LSTc which are signals shifted to VHa to VHc levels, are generated and output.
  • the voltage levels of the first to third transmission side control signals CTa to CTc are fixed when the signal transmission device 2 is in operation.
  • the voltage levels of the first to third transmission side control signals CTa to CTc may be different from each other or the same.
  • the voltage levels of the first to third transmission side control signals CTa to CTc are typically smaller than the VHa to VHc levels, respectively.
  • the transmission side level control processor 31 includes first to third transmission side data signals DTa to DTc, a system clock SYS, a sampling clock SAM, and first to third transmission side level shift signals LSTa output from the transmission side level shifter 30. LSTc is received, and based on these, a transmission signal TS is generated and output.
  • the transmission side signal processing unit is realized by the transmission side level shifter 30 and the transmission side level control processor 31.
  • FIG. 3 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment.
  • the transmission side level control processor 31 includes a transmission side input buffer 310, a transmission side delay circuit 311, a transmission side data discrimination circuit 312, a transmission signal conversion circuit 313 as a transmission signal conversion unit, and a transmission side output.
  • a buffer 314 is provided.
  • the transmission side input buffer 310 is a buffer for receiving the first to third transmission side data signals DTa to DTc.
  • the transmission side delay circuit 311 receives the first to third transmission side data signals DTa to DTc via the transmission side input buffer 310, and based on the timing of the sampling clock SAM, these first to third transmission side data signals DTa. .. DTc are output with different phases.
  • transmission side phase control process the process of making the phases of the first to third transmission side data signals DTa to DTc different from each other in this way is referred to as “transmission side phase control process”.
  • a transmission side phase control unit is realized by the transmission side delay circuit 311.
  • the transmission side data discriminating circuit 312 has the bit data (referred to as data indicating “1” or “0”) of the first to third transmission side data signals DTa to DTc after the transmission side phase control processing being “1”. Whether “0” is indicated is determined based on the timing of the sampling clock SAM, and first to third transmission side determination signals RTa to RTc are output as the determination results.
  • the voltage level of the bit data indicating “1” in each transmission side data signal corresponds to the first level on the transmission side
  • the voltage level of bit data indicating “0” corresponds to the second level on the transmission side.
  • the transmission signal conversion circuit 313 receives the first to third transmission side discrimination signals RTa to RTc, and based on the timings of the system clock SYS and the sampling clock SAM, the first to third transmission side discrimination signals RTa to RTc (that is, the first transmission side discrimination signals RTa to RTc). (Bit data of third transmission side data signals DTa to DTc) are sequentially sampled, and one transmission signal TS is generated and output by converting the voltage level of these data. Specifically, the transmission signal conversion circuit 313 is a voltage at which the first transmission side discrimination signal RTa (that is, the bit data of the first transmission side data signal DTa) sampled in the first sampling period indicates “1” or “0”.
  • the second transmission side discrimination signal RTb that is, bit data of the second transmission side data signal DTb sampled in the second sampling period is “1” or “0”.
  • the third transmission side discrimination signal RTc that is, the bit data of the third transmission side data signal DTc sampled in the third sampling period is “1” or “0”.
  • VHc level or GND level as a predetermined voltage level. Converted to le (ground level).
  • the transmission signal conversion circuit 313 arranges the first to third transmission side discrimination signals RTa to RTc in order for each system period, and also converts one transmission signal TS obtained by converting these voltage levels as described above. Generate and output.
  • portions of the transmission signal TS corresponding to the bit data of the first to third transmission side data signals DTa to DTc are referred to as “first to third transmission / reception data”, respectively, and are represented by symbols TR1 to TR3, respectively.
  • the transmission signal conversion circuit 313 may be provided with the function of the transmission side data determination circuit 312 and the transmission side data determination circuit 312 may not be provided.
  • the voltage level corresponding to “0” of the first transmission / reception data TR1 and the voltage level corresponding to “1” of the second transmission / reception data TR2 are the same VHb level.
  • the voltage level corresponding to “0” of the second transmission / reception data TR2 and the voltage level corresponding to “1” of the third transmission / reception data TR3 are the same VHc level. That is, the voltage level after conversion of “0” of the preceding transmission side data signal of the two transmission side data signals in which the period to be sampled in each system period is continuous, and “1” of the subsequent transmission side data signal.
  • the converted voltage levels are the same as each other.
  • the voltage level corresponding to “1” of the first transmission / reception data TR1 (bit data indicating “1” of the first transmission side data signal DTa sampled in the first sampling period which is the first sampling period of each system period) Is the VHa level, and the VHa level does not overlap with others.
  • the voltage level corresponding to “0” of the third transmission / reception data TR3 (the voltage level after conversion of the third transmission side data signal DTc sampled in the third sampling period which is the last sampling period of each system period) Is a GND level, and the GND level does not overlap with other.
  • the transmission side output buffer 314 is a buffer for serially outputting the transmission signal TS.
  • the transmission signal TS output from the transmission side output buffer 314 is transmitted to the receiving unit 4 via the transmission path 5.
  • FIG. 4 is a block diagram showing a configuration of the receiving unit 4 in the present embodiment.
  • the receiving unit 4 includes input terminals IR1 to IR5, output terminals ORa to ORc, a receiving side level shifter 40, and a receiving side level control processor 41.
  • the input terminals IR1 to IR3 correspond to receiving side input terminals.
  • the output terminals ORa to ORc correspond to reception side output terminals.
  • the input terminal IR1 is a terminal for receiving the system clock SYS.
  • the input terminal IR2 is a terminal for receiving the sampling clock SAM.
  • the input terminal IR3 is a terminal for receiving the transmission signal TS.
  • the input terminal IR4 is a signal for receiving the receiving side control signal CR.
  • the input terminal IR5 is a terminal for receiving the reception-side power supply voltage VH as the power supply voltage.
  • the voltage level of the reception-side power supply voltage VH may also be expressed as VH.
  • the output terminals ORa to ORc are terminals for outputting the first to third receiving side data signals DRa to DRc, respectively.
  • the reception-side level shifter 40 receives the reception-side control signal CR and the transmission-side power supply voltage VH, and generates and outputs a reception-side level shift signal LSR that is a signal obtained by shifting the voltage level of the reception-side control signal CR to the VH level.
  • the voltage level of the reception-side control signal CR is fixed when the signal transmission device 2 operates.
  • the voltage level of the reception side control signal CR is typically smaller than the VH level.
  • the receiving side level control processor 41 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the receiving side level shift signal LSR outputted from the receiving side level shifter 40, and based on these, the first to third receiving side data Generate and output signals DRa to DRc.
  • the reception side signal processing unit is realized by the reception side level shifter 40 and the reception side level control processor 41.
  • FIG. 5 is a block diagram showing a configuration of the receiving side level control processor 41 in the present embodiment.
  • the reception-side level control processor 41 includes a reception-side input buffer 410, a reception-side data determination circuit 411, a transmission signal inverse conversion circuit 412 as a transmission signal inverse conversion unit, a reception-side delay circuit 413, and a reception side.
  • a side output buffer 414 is provided.
  • the receiving side input buffer 410 is a buffer for receiving the transmission signal TS serially.
  • the reception-side data determination circuit 411 determines whether the first to third transmission / reception data TR1 to TR3 of the transmission signal TS indicate VHa to VHc or the GND level based on the timing of the sampling clock SAM, and these determinations. As a result, the receiving side discrimination signal RR is output.
  • the transmission signal inverse conversion circuit 412 receives the reception side determination signal RR and samples the reception side determination signal RR (that is, the first to third transmission / reception data TR1 to TR3) based on the timings of the system clock SYS and the sampling clock SAM. At the same time, by converting the voltage levels of the first to third transmission / reception data TR1 to TR3, the first to third reception-side data signals DRa to DRc are generated and output, respectively. Specifically, the transmission signal inverse conversion circuit 412 indicates “1” if the reception side determination signal RR is at the VHa or VHb level when the reception side determination signal RR corresponding to the first transmission / reception data TR1 is sampled.
  • a first receiving side data signal DRa having a voltage level (here, assumed to be VH level) or a voltage level indicating “0” (here, assumed to be GND level) is generated. Further, the transmission signal inverse conversion circuit 412 sets “1” or “0” if the reception side determination signal RR is at the VHb or VHc level when the reception side determination signal RR corresponding to the second transmission / reception data TR2 is sampled. The second receiving side data signal DRb having the voltage level shown is generated. In addition, the transmission signal inverse conversion circuit 412 sets “1” or “0” if the reception side determination signal RR is VHc or GND level when the reception side determination signal RR corresponding to the third transmission / reception data TR3 is sampled.
  • the third receiving side data DRc having the voltage level shown is generated.
  • the voltage level indicating “1” of the first to third receiving side data signals DRa to DRc corresponds to the receiving side first level
  • the voltage level indicating “0” corresponds to the receiving side second level.
  • the first to third receiving side data signals DRa to DRc generated here have different phases.
  • the transmission signal inverse conversion circuit 412 may be provided with the function of the reception side data determination circuit 411 and the reception side data determination circuit 411 may not be provided.
  • the reception-side delay circuit 413 receives the first to third reception-side data signals DRa to DRc output from the transmission signal inverse conversion circuit 412, and based on the timing of the sampling clock SAM, these first to third reception-side data
  • the signals DRa to DRc are output with the same phase.
  • the process of making the phases of the first to third reception-side data signals DRa to DRc identical to each other is referred to as “reception-side phase control process”.
  • a reception-side phase control unit is realized by the reception-side delay circuit 413.
  • the reception-side output buffer 414 is a buffer for outputting the first to third reception-side data signals DRa to DRc that are in phase with each other by the reception-side phase control process. These first to third reception side data signals DRa to DRc are output to the outside via the reception side output buffer 414.
  • FIG. 6 is a signal waveform diagram showing the first to third transmission side data signals DTa to DTc before the transmission side phase control processing in this embodiment.
  • each of the first to third transmission side data signals DTa to DTc represents one piece of data in units of 8 bits.
  • 8-bit data of the first transmission-side data signal DTa is represented by A0 to A7
  • 8-bit data of the second transmission-side data signal DTb is represented by B0 to B7, respectively
  • 8 of the third transmission-side data signal DTc Bit data are represented by C0 to C7, respectively.
  • Each of the first to third reception side data signals DRa to DRc is also 8-bit data, and the 8-bit data of the first reception side data signal DRa is also represented by A0 to A7, respectively.
  • the 8-bit data is also represented by B0 to B7, respectively, and the 8-bit data of the third receiving side data signal DRc is also represented by C0 to C7, respectively.
  • a first transmission side data signal DTa first reception side data signal DRa
  • a second transmission side data signal DTb The second reception side data signal DRb
  • the third transmission side data signal DTc third reception side data signal DRc
  • bit data of each transmission-side data signal is blank in two sampling periods (2 TB) for each 2-bit data.
  • such blank data is referred to as “NULL data”, and in FIG. 6 and the subsequent drawings, the data is represented by “NULL”.
  • the bit data of each reception-side data signal changes at the timing when the voltage level of the sampling clock SAM rises every two sampling periods (2TB).
  • FIG. 7 is a signal waveform diagram for explaining the operation of the transmission side delay circuit 311 in this embodiment.
  • the transmission-side delay circuit 311 performs transmission-side phase control processing based on the timing of the sampling clock SAM on the first to third transmission-side data signals DTa to DTc.
  • the first transmission side data signal DTa is subjected to processing in which the second transmission side data signal DTb and the third transmission side data signal DTc are delayed by one sampling period and two sampling periods, respectively.
  • the first to third transmission side data signals DTa to DTc after such transmission side phase control processing are given to the transmission side data determination circuit 312 and then the first to third transmission side determination signals RTa to RTc described above. Is output as
  • FIG. 8 is a signal waveform diagram for explaining the operation of the transmission signal conversion circuit 313 in this embodiment.
  • the first to third transmission side data signals DTa to DTc shown in the figure are actually equivalent to the first to third transmission side discrimination signals RTa to RTc, respectively.
  • Explanation will be given as first to third transmission side data signals DTa to DTc (the same applies to FIG. 17 described later).
  • eight consecutive system periods TA are referred to as “0th to 7th system periods”, respectively, and are represented by symbols TA0 to TA7, respectively.
  • the first to third transmission side data signals DTa to DTc for 8 bits (that is, data for a total of 24 bits) in the 0th to seventh system periods TA0 to TA7.
  • a corresponding transmission signal TS is generated.
  • the first to third transmission side data signals DTa to DTc for 8 bits are “11101101”, “01100101”, and “10111001”, respectively. ". Note that NULL data is not considered as data.
  • the transmission signal conversion circuit 313 determines the voltage level of the transmission signal TS based on the bit data of the first to third transmission side data signals DTa to DTc.
  • the bit data A0 in which the first transmission side data signal DTa to be sampled is “1” indicates the first transmission / reception data TR1 of the transmission signal TS.
  • the voltage level becomes a VHa level corresponding to “1” of the first transmission side data DTa.
  • the second transmission side data signal DTb to be sampled indicates the bit data B0 which is “0”
  • the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the second transmission side data signal. It becomes the VHc level corresponding to “0” of DTb.
  • the transmission signal TS for one system period indicates bit data for one bit of each transmission-side data signal (that is, bit data for a total of three bits).
  • bit data A1 in which the first transmission side data signal DTa to be sampled is “1” indicates the first transmission / reception data TR1 of the transmission signal TS.
  • the voltage level becomes a VHa level corresponding to “1” of the first transmission side data signal DTa.
  • bit data B1 in which the second transmission side data DTb to be sampled is “1” indicates the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the second transmission side data signal DTb.
  • the third transmission side data signal DTc to be sampled indicates bit data C0 that is “0”, so the voltage level of the third transmission / reception data TR3 of the transmission signal TS is the third transmission side data signal. It becomes the GND level corresponding to “0” of DTc.
  • the transmission signal TS is determined in the transmission signal conversion circuit 313 by determining the voltage level of each transmission / reception data of the transmission signal TS by the same procedure. Is generated.
  • the transmission signal TS generated in this way is transmitted to the receiving unit 2 via the transmission side output buffer 314 and the transmission path 5.
  • FIG. 9 is a signal waveform diagram for explaining the operation of the transmission signal inverse conversion circuit 412 in this embodiment. Note that the first to third reception side data signals DRa to DRc shown in this figure are actually obtained based on the reception side determination signal RR generated based on the transmission signal TS. In the following description, these first to third receiving side data signals DRa to DRc will be described as being obtained directly from the transmission signal TS (the same applies to FIG. 18 described later).
  • the transmission signal inverse conversion circuit 412 in this embodiment in the 0th to 7th system periods TA0 to TA7, based on the transmission signal TS, 8-bit first to third receiving side data signals DRa to DRc (ie, A total of 24 bits of data) is generated. Since the 0th to 7th system periods TA0 to TA7 are names for convenience, the timings of the 0th to 7th system periods TA0 to TA7 on the transmitting side and the receiving side do not have to coincide with each other.
  • the transmission signal inverse conversion circuit 412 samples the first to third transmission / reception data TR1 to TR3 of the transmission signal TS, and the first to third transmission / reception data TR1.
  • Bit data of the first to third receiving data signals DRa to DRa are determined based on the voltage levels of .about.TR3, respectively.
  • bit data A0 of the first reception side data signal DRa becomes “1”.
  • bit data indicating “1” is realized by the VH level
  • bit data indicating “0” is realized by the GND level.
  • the bit data B0 of the second reception side data signal DRb is “0”.
  • the bit data C0 of the third reception-side data signal DRc is “1”. In this manner, 1-bit bit data of each reception-side data signal (that is, bit data for a total of 3 bits) is obtained from the transmission signal TS for one system period.
  • the bit data A1 of the first reception side data DRa becomes “1”.
  • the bit data B1 of the second reception side data signal DRb is “1”.
  • the bit data C1 of the third reception-side data signal DRc is “0”.
  • the bit data of the first to third reception side data signals DRa to DTa is determined by the same procedure, so that the reception side phase control is performed.
  • First to third receiving side data signals DRa to DRc before processing are generated.
  • the first to third receiving side data signals DRa to DRc indicate “11101101”, “01100101”, and “10111001”, respectively. That is, the first to third reception side data signals DRa to DRc indicate the same bit data as the first to third transmission side data signals DTa to DTc, respectively.
  • NULL data is not considered as described above.
  • the first to third reception-side data signals DRa to DRc before the reception-side phase control processing generated in this way are given to the reception-side delay circuit 413.
  • FIG. 10 is a signal waveform diagram showing the first to third reception side data signals DRa to DRc before the reception side phase control processing.
  • the bit data of each reception side data signal changes at the timing when the voltage level of the sampling clock SAM rises every three sampling periods (3TB).
  • the present invention is not limited to this, and for example, NULL data is inserted in the same manner as each transmission side data signal. May be.
  • FIG. 11 is a signal waveform diagram for explaining the operation of the reception side delay circuit 413.
  • the reception-side delay circuit 413 performs reception-side phase control processing based on the timing of the sampling clock SAM on the first to third reception-side data signals DRa to DRc.
  • the second receiving side data signal DRb and the first receiving side data signal DRa are subjected to processing for delaying the first receiving side data signal DRc and the first receiving side data signal DRa by 1 sampling period and 2 sampling periods, respectively.
  • the phases of the first to third receiving data signals DRa to DRc are the same.
  • the first to third reception side data signals DRa to DRc after such reception side phase control processing are output via the reception side output buffer 414.
  • the first to third transmission / reception data TR1 to TR3 are at different voltage levels as described above. Therefore, in each of the first to third sampling periods in each system period, there are two types of voltage levels of the transmission signal TS (specifically, the reception side determination signal RR) to be sampled by the transmission signal inverse conversion circuit 412. That is, there are two types of voltage levels of the transmission signal TS (first transmission / reception data TR1) to be sampled in the first sampling period, the VHa level and the VHb level, and the transmission signal TS (second transmission / reception data) to be sampled in the second sampling period.
  • the transmission signal TS first transmission / reception data TR1
  • the voltage level of the data TR2) is two types of VHb level and VHc level
  • the voltage level of the transmission signal TS (third transmission / reception data TR3) to be sampled in the third sampling period is two types of VHc level and GND level. .
  • the VHc level or the GND level can be corrected to a VHb level close to the VHc level or the GND level among the VHa level and the VHb level corresponding to the first transmission / reception data TR1. It is also considered that a transmission defect has occurred when the voltage level of the second transmission / reception data TR2 is the VHa level or the GND level.
  • the VHa level close to the VHb level corresponding to the second transmission / reception data TR2 can be corrected to the VHb level and corrected to the GND level close to the VHc level corresponding to the second transmission / reception data TR2. It is also considered that a transmission defect has occurred when the voltage level of the third transmission / reception data TR3 is the VHa level or the VHb level. In this case, the VHa level or VHb level can be corrected to a VHc level close to the VHa level or the VHb level among the VHc level and the GND level corresponding to the third transmission / reception data TR3.
  • the first transmission / reception data TR1 which are transmission signals TS to be sampled in the third sampling period and the first sampling period before and after the switching of each system period
  • the first transmission / reception data TR1 Both the corresponding VHa level and VHb level are larger than VHc, which is the larger of the two voltage levels corresponding to the third transmission / reception data TR3.
  • the voltage level corresponding to the second transmission / reception data TR2 is the same as or smaller than the voltage level corresponding to the first transmission / reception data TR1.
  • the voltage level corresponding to the third transmission / reception data TR3 is the same as or smaller than the voltage level corresponding to the second transmission / reception data TR2.
  • the voltage level of the transmission signal TS increases only when the third sampling period shifts to the first sampling period. For this reason, even if a synchronization shift occurs, the sampling period in which the voltage level of the transmission signal TS is larger than the immediately preceding sampling period can be determined as the first sampling period, and thus the synchronization shift can be eliminated.
  • the transmission unit 3 sequentially samples the first to third transmission side data signals DTa to DTc based on the timings of the system clock SYS and the sampling clock SAM, and changes their voltage levels.
  • a transmission signal TS is generated and transmitted from the transmission unit 3 to the reception unit 4 via one transmission path 5.
  • the receiving unit 4 based on the timings of the system clock SYS and the sampling clock SAM, the first to third reception-side data signals corresponding to the voltage levels of the first to third transmission / reception data TR1 to TR3 of the transmission signal TS, respectively.
  • DRa to DRc are generated.
  • the voltage level corresponding to “0” of the first transmission / reception data TR1 and the voltage level corresponding to “1” of the second transmission / reception data TR2 are the same VHb level.
  • the voltage level corresponding to “0” of the second transmission / reception data TR2 and the voltage level corresponding to “1” of the third transmission / reception data TR3 are the same VHc level.
  • the voltage level corresponding to “1” of the first transmission / reception data TR1 is the VHa level, and the VHa level does not overlap with the others.
  • the voltage level corresponding to “0” of the third transmission / reception data TR3 is the GND level, and the GND level is not duplicated.
  • N + 1 types (four types) of voltage levels for realizing the transmission signal TS there are N + 1 types (four types) of voltage levels for realizing the transmission signal TS in the present embodiment. For this reason, even if a synchronization shift occurs, the sampling period in which the voltage level of the transmission signal TS is larger than the immediately preceding sampling period can be determined as the first sampling period, and thus the synchronization shift can be eliminated. Thereby, a plurality of types of data transmission can be transmitted more reliably.
  • the voltage level for generating the transmission signal TS from the first to third transmission side data signals DTa to DTc, and the first to third reception side data signals DRa to DRc from the transmission signal TS. can be generated using the transmission-side level shifter 30 and the reception-side level shifter 40, respectively.
  • the transmission side level shifter 30 is used, so that a plurality of voltage levels are not supplied from the host 1 (that is, the first to third transmission side control signals CTa ⁇ ). Even if the voltage levels of CTc are the same, a plurality of different voltage levels can be generated.
  • the bit data “1” and “0” of the first transmission side data signal DTa correspond to the VHa level and VHb level, respectively
  • the bit of the second transmission side data signal DTb Data “1” and “0” correspond to the VHb level and VHc level, respectively
  • bit data “1” and “0” of the third transmission side data signal DTc correspond to the VHc level and GND level, respectively.
  • the present invention is not limited to this.
  • both of the voltage levels corresponding to “1” and “0” of the bit data of each transmission side data signal and the voltage levels corresponding to “1” and “0” of the bit data of other transmission side data signals By making the two different from each other, the transmission signal TS having N ⁇ 2 types (six types in the present embodiment) of voltage levels may be generated.
  • Second Embodiment> ⁇ 2.1 Overall configuration> Since the second embodiment of the present invention has the same configuration and the like as the first embodiment except for the transmission side level control processor 31 and the reception side level control processor 41, description of the common part is omitted. In addition, the same elements as those of the first embodiment among the components of the present embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
  • FIG. 12 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment. As shown in FIG. 12, the transmission side level control processor 31 is different from that in the first embodiment in that a transmission side delay circuit 311, a transmission side data discrimination circuit 312 and a transmission signal conversion circuit 313 are converted. A processor (processing device) 315 is provided.
  • the conversion processor 315 includes the functions of the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313, and includes the transmission side delay circuit 311 and the transmission side data described in the first embodiment.
  • the operations of the determination circuit 312 and the transmission signal conversion circuit 313 are realized. That is, the conversion processor 315 receives the first to third transmission data signals DTa to DTc, the system clock SYS, the sampling clock SAM, and the first output from the transmission level shifter 30 that are input via the transmission input buffer 310.
  • the third transmission side level shift signals LSTa to LSTc are received, the transmission signal TS is generated based on these, and output to the transmission side output buffer 314.
  • the detailed operation of the conversion processor 315 is the same as the operation of the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313 in the first embodiment, and a description thereof will be omitted. To do.
  • FIG. 13 is a block diagram showing a configuration of the receiving side level control processor 41 in the present embodiment. As shown in FIG. 13, the receiving side level control processor 41 is different from that in the first embodiment in place of the receiving side data discriminating circuit 411, the transmission signal inverse converting circuit 412, and the receiving side delay circuit 413. An inverse conversion processor (processing device) 415 is provided.
  • the inverse conversion processor 415 includes functions of a reception side data determination circuit 411, a transmission signal reverse conversion circuit 412, and a reception side delay circuit 413.
  • the detailed operation of the inverse conversion processor 415 is the same as the operation of the reception side data determination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side delay circuit 413 in the first embodiment. Is omitted.
  • the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313 are converted into the reception side data determination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side delay by the conversion processor 315.
  • the circuits 413 are each realized as one component by the inverse conversion processor 415.
  • the transmission side delay circuit 311, the transmission side data discrimination circuit 312, and the transmission signal conversion circuit 313 share common components, and the reception side data discrimination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side By sharing common components in the side delay circuit 413, the circuit scale of the transmission unit 3 and the reception unit 4 can be reduced.
  • Third Embodiment> ⁇ 3.1 Overall configuration> Since the third embodiment of the present invention has the same configuration and the like as the first embodiment except for the transmission side level control processor 31 and the reception side level control processor 41, description of the common part is omitted. In addition, among the components of the present embodiment, the same elements as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
  • FIG. 14 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment.
  • the transmission-side level control processor 31 is different from that in the first embodiment, and instead of the transmission-side delay circuit 311, three FIFO (First In First Out) memories 316 a to 316 c and transmission A side readout control circuit 317 is provided.
  • the three FIFO memories 316a to 316c are referred to as “first to third transmission side FIFO memories”, respectively.
  • the first to third transmission side FIFO memories 316a to 316c are memories that perform a buffer operation of reading data written first.
  • the first to third transmission side FIFO memories 316a to 316c store bit data of the first to third transmission side data signals DTa to DTc input via the transmission side input buffer 300, respectively.
  • the first to third transmission side data signals DTa to DTc input via the transmission side input buffer 300 have NULL data inserted every two bits as in the first embodiment. It may be a thing, and the thing in which NULL data is not inserted may be sufficient.
  • the transmission side read control circuit 317 controls the read timing of the bit data of the first to third transmission side data signals DTa to DTc written in the first to third transmission side FIFO memories 316a to 316c, respectively. Specifically, the transmission side read control circuit 317 indicates the first side based on the transmission side read control signal RCT and the sampling clock SAM given from the outside (for example, the host 1) indicating the transmission side FIFO memory to be the read source. Read bit data sequentially from the third transmission side FIFO memories 316a to 316c every sampling period. The read bit data of the first to third transmission side data signals DTa to DTc are supplied to the transmission side data discrimination circuit 312.
  • the bit data of the first to third transmission side data signals DTa to DTc are read from the first to third transmission side FIFO memories 316a to 316c in order every sampling period, so that the first The first to third transmission side data signals DTa to DTc subjected to the transmission side phase control process similar to the embodiment are given to the transmission side data discrimination circuit 302.
  • the transmission-side phase control unit is realized by the first to third transmission-side FIFO memories 316 a to 316 c and the transmission-side read control circuit 317.
  • the writing of bit data to the first to third transmission side FIFO memories 316a to 316c is continuously performed, while the reading of bit data from the first to third transmission side FIFO memories 316a to 316c is 3 It is performed in turn at a frequency of once. For this reason, it is desirable that the reading speed of the bit data from each transmission side FIFO memory is three times the writing speed of the bit data to the first to third transmission side FIFO memories 316a to 316c. Thereby, the writing speed of the bit data to the first to third transmitting side FIFO memories 316a to 316c and the reading speed of the bit data from the first to third transmitting side FIFO memories 316a to 316c can be made substantially equal. it can.
  • the bit data writing speed to the first to third transmission side FIFO memories 316a to 316c and the bit data reading speed from each transmission side FIFO memory may be equal to each other.
  • the third transmission side FIFO memories 316a to 316c may run out of space for storing bit data.
  • a memory for saving data is provided in the signal transmission system by means (not shown), and the first to third transmission side data to be stored in the first to third transmission side FIFO memories 316a to 316c, respectively. It is desirable to temporarily store bit data of signals DTa to DTc. As a result, it is possible to prevent the first to third transmission side FIFO memories 316a to 316c from becoming free for storing bit data.
  • the components other than the first to third transmission side FIFO memories 316a to 316c and the transmission side read control circuit 317 of the transmission side level control processor 31 in the present embodiment are the same as those in the first embodiment. Therefore, the description is omitted.
  • FIG. 15 is a block diagram showing the configuration of the receiving side level control processor 41 in the present embodiment.
  • the receiving side level control processor 41 differs from that in the first embodiment in that it has three FIFO memories 416a to 416c and a receiving side read control circuit 417 instead of the receiving side delay circuit 413. I have.
  • the three FIFO memories 416a to 416c are referred to as “first to third reception side FIFO memories”, respectively.
  • the first to third reception side FIFO memories 416a to 416c are memories that perform the same buffer operation as the first to third transmission side FIFO memories 316a to 316c.
  • the first to third reception side FIFO memories 416a to 416c store bit data of the first to third reception side data signals DRa to DRc output from the transmission signal inverse conversion circuit 412, respectively.
  • the reception side read control circuit 417 controls the read timing of the bit data of the first to third reception side data signals DRa to DRc written in the first to third reception side FIFO memories 416a to 416c, respectively.
  • the reception-side read control circuit 417 is configured to receive first to third reception-side FIFO memories 416a to 416a based on a reception-side read control signal RCR (which may be the system clock SYS) given from the outside (for example, the host 1).
  • RCR which may be the system clock SYS
  • the bit data of the first to third receiving side data signals DRa to DRc are read from 416c at the same timing.
  • the read first to third reception side data signals DRa to DRc are applied to the reception side output buffer 414.
  • the bit data of the first to third reception side data signals DRa to DRc are read from the first to third reception side FIFO memories 416a to 416c at the same timing, so that substantially the first embodiment described above.
  • the first to third reception side data signals DRa to DRc that have been subjected to the same reception side phase control processing as described above are applied to the reception side output buffer 414.
  • the reception-side phase control unit is realized by the first to third reception-side FIFO memories 416a to 416c and the reception-side read control circuit 417.
  • the reading speed of bit data from each receiving side FIFO memory is three times the writing speed of bit data to the first to third receiving side FIFO memories 416a to 416c. It is desirable to be. It is to be noted that a data saving memory similar to that on the transmission side is provided, and the writing speed of bit data to the first to third receiving side FIFO memories 416a to 416c and the reading speed of bit data from the receiving side FIFO memory are mutually set. It may be equal.
  • FIG. 16 is a signal waveform diagram for explaining the operation of the transmission side read control circuit 307 in the present embodiment.
  • the first to third transmission side FIFO memories 316a to 316c are first to each at the timing when the voltage level of the sampling clock SAM rises.
  • the bit data of the third transmission side data signals DTa to DTc are read.
  • the transmission-side FIFO memory serving as a reading source is switched every sampling period in the order of the first to third transmission-side FIFO memories 316a to 316c.
  • the second transmission-side data signal DTb and the third transmission-side data signal DTc are each one sampling period with respect to the first transmission-side data signal DTa. And a delay of 2 sampling periods.
  • the bit data of the first to third transmission side data signals DTa to DTc read out as described above are given to the transmission side data discrimination circuit 303. Since the operation of the transmission side data discrimination circuit 303 is the same as that in the first embodiment, description thereof is omitted.
  • FIG. 17 is a signal waveform diagram for explaining the operation of the transmission signal conversion circuit 313 in this embodiment. Also in this embodiment, as in the first embodiment, the transmission signal conversion circuit 313 uses the first to third transmission side data signals DTa to DTc for 8 bits (that is, data for a total of 24 bits). Thus, a transmission signal TS is generated. Note that details of the operation of the transmission signal conversion circuit 313 are as described in the first embodiment, and a description thereof will be omitted.
  • FIG. 18 is a signal waveform diagram for explaining the operation of the transmission signal inverse conversion circuit 412 in this embodiment. Also in this embodiment, the first to third reception side data signals DRa to DRc for 8 bits before the reception side phase control processing are performed based on the transmission signal TS by the transmission signal inverse conversion circuit 412 in the first embodiment. (That is, a total of 24 bits of data) is generated. The details of the operation of the transmission signal inverse conversion circuit 412 are as described in the first embodiment, and the description thereof is omitted.
  • the first to third reception side data signals DRa to DRc generated by the transmission signal inverse conversion circuit 412 are sequentially stored in the first to third reception side FIFO memories 416a to 416c, respectively.
  • FIG. 19 is a signal waveform diagram for explaining the operation of the receiving side read control circuit 417 in the present embodiment.
  • the reception-side read control circuit 417 starts from the first to third reception-side FIFO memories 416a to 416c at the timing when the voltage level of the reception-side read control signal RCR (which may be the system clock SYS) rises.
  • the bit data of the first to third receiving side data signals DRa to DRc are read simultaneously. For this reason, as in the reception-side phase control process of the first embodiment, the phases of the first to third reception-side data signals DRa to DRc are the same.
  • the first to third reception-side data signals DRa to DRc after such reception-side phase control processing are output via the reception-side output buffer 414.
  • the first to third transmission side FIFO memories 316a to 316c and the transmission side read control circuit 317 realize the transmission side phase control unit, and the first to third reception side FIFO memories 416a to 416c and the reception side.
  • the same effects as in the first embodiment can be obtained.
  • the bit data of each transmission side data signal is set to two sampling periods, and NULL data of two sampling periods is inserted every two bits.
  • the present invention is not limited to this. Absent.
  • the bit data of each transmission side data signal may be in units of 3 sampling periods, and NULL data may not be inserted. In this case, it is not necessary to perform transmission-side phase control processing on the first to third transmission-side data signals DTa to DTc, so that the transmission-side delay circuit 311 is not provided.
  • the bit data of each transmission side data signal may be set as one sampling period unit, and NULL data of two sampling periods may be inserted between the bit data.
  • the present invention is not limited to this.
  • the present invention can also be applied to the case of transmitting two data, or the case of transmitting four or more data.
  • the frequency of the sampling clock SAM is a value obtained by multiplying the frequency of the system clock SYS by the number of data.
  • the transmission signal conversion circuit 313 and the transmission signal inverse conversion circuit 412 each use the GND level that is the ground level, but other voltage levels may be used instead.
  • the present invention it is possible to provide a signal transmission device and a signal transmission method capable of transmitting a plurality of data while suppressing an increase in cost.
  • the present invention can be applied to a signal transmission apparatus and a signal transmission method for performing a plurality of types of data transmission.
  • Reception side input buffer (reception buffer unit) 411... Reception side data discrimination circuit 412... Transmission signal reverse conversion circuit (transmission signal reverse conversion unit) 413 ... Reception side delay circuit (reception side phase control unit) 414 ... Reception side output buffer 415 ...

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Abstract

The purpose of the invention is to provide a signal transmission device capable of transmitting a plurality of data without an increase in cost. The signal transmission device (2) is provided with a transmitter (3), a receiver (4), and a data transmission path (5). The transmitter (3) samples, in sequence, bit data indicated by first to third transmission-side data signals (DTa to DTc) and converts the voltage level of the bit data, whereby a transmission signal (TS) is generated and outputted. The receiver (4) samples first to third transmission/reception data (TR1 to TR3; portions of the transmission signal (TS) that correspond to the bit data from the first to third transmission- side data signals (DTa to DTc)) on the basis of a system clock (SYS) and a sampling clock (SAM), and converts the voltage level of the first to third transmission/reception data (TR1 to TR3), whereby reception-side data signals (DRa to DRc) are generated and outputted.

Description

信号伝送装置および信号伝送方法Signal transmission apparatus and signal transmission method
　本発明は、信号伝送装置および信号伝送方法に関し、特に、複数種類のデータの伝送に好適な信号伝送装置および信号伝送方法に関する。 The present invention relates to a signal transmission device and a signal transmission method, and more particularly, to a signal transmission device and a signal transmission method suitable for transmitting a plurality of types of data.
　近年、ＴＩＡ／ＥＩＡ－６４４規格で規定されているＬＶＤＳ（Ｌｏｗ　Ｖｏｌｔａｇｅ　Ｄｉｆｆｅｒｅｎｔｉａｌ　Ｓｉｇｎａｌｉｎｇ）を用いたシリアル伝送方式が普及している。ＬＶＤＳでは、微小電圧の差動信号を用いることにより、低消費電力で比較的高速なデータ伝送が実現される。 In recent years, a serial transmission method using LVDS (Low Voltage Differential Signaling) defined in the TIA / EIA-644 standard has become widespread. In LVDS, relatively high-speed data transmission is realized with low power consumption by using a differential signal with a minute voltage.
　また、上記シリアル伝送方式に関連して、特許文献１には、ソースドライバの入力部分にレベルシフト回路を設けておき、コントローラＩＣの出力バッファからソースドライバにシリアル伝送されるデータの振幅を当該レベルシフト回路により昇圧する表示装置が開示されている。このような構成によれば、コントローラＩＣからソースドライバに伝送すべきデータの振幅を小さくできるので、上記ＬＶＤＳと同様に低消費電力なデータ伝送が実現される。 Further, in relation to the serial transmission method, in Patent Document 1, a level shift circuit is provided in the input portion of the source driver, and the amplitude of data serially transmitted from the output buffer of the controller IC to the source driver is set to the level. A display device that boosts voltage by a shift circuit is disclosed. According to such a configuration, since the amplitude of data to be transmitted from the controller IC to the source driver can be reduced, data transmission with low power consumption can be realized as in the case of the LVDS.
日本の特開２００４－４６０５４号公報Japanese Unexamined Patent Publication No. 2004-46054
　しかし、上記ＬＶＤＳによるシリアル伝送および上記特許文献１に開示されたシリアル伝送のいずれにおいても、複数のデータを伝送するためには当該データの数とそれぞれ同数の送信側インターフェース、受信側インターフェース、および伝送路が必要になる。このため、伝送するデータ数が多いほど回路規模が増大し、その結果として高コスト化を招く。 However, in both of the serial transmission based on the LVDS and the serial transmission disclosed in Patent Document 1, in order to transmit a plurality of data, the same number of transmission side interfaces, reception side interfaces, and transmissions as the number of the data respectively. A road is needed. For this reason, as the number of data to be transmitted increases, the circuit scale increases, resulting in higher costs.
　そこで、本発明は、コストの増大を抑えつつ複数のデータの伝送を可能とする信号伝送装置および信号伝送方法を提供することを目的とする。 Therefore, an object of the present invention is to provide a signal transmission device and a signal transmission method that can transmit a plurality of data while suppressing an increase in cost.
　本発明の第１の局面は、送信部と受信部との間で１本の伝送路により複数種類のデータのシリアル伝送を行う信号伝送装置であって、
　前記送信部は、
　　周期的に変化する第１クロック信号、当該第１クロック信号の周波数をＮ（Ｎは２以上の整数）逓倍した第２クロック信号、および伝送すべきＮ個の送信側データ信号を外部から受け取るための送信側入力端子と、
　　前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記Ｎ個の送信側データ信号を順にサンプリングすると共に、サンプリングした当該Ｎ個の送信側データ信号の電圧レベルを互いに異ならせることにより伝送信号を生成する送信側信号処理部と、
　　前記伝送信号を前記伝送路に出力するための送信側出力端子とを含み、
　前記受信部は、
　　前記第１クロック信号、前記第２クロック信号、および前記伝送路から前記伝送信号を受け取るための受信側入力端子と、
　　前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記伝送信号をサンプリングすると共に、サンプリングした当該伝送信号の電圧レベルを、電圧レベルが変化する前の前記Ｎ個の送信側データ信号に対応する電圧レベルに変化させることによりそれぞれＮ個の受信側データ信号を生成する受信側信号処理部と、
　　前記Ｎ個の受信側データ信号を外部に出力するための受信側出力端子とを含むことを特徴とする。 A first aspect of the present invention is a signal transmission device that serially transmits a plurality of types of data between a transmission unit and a reception unit through a single transmission line,
The transmitter is
To receive a first clock signal that periodically changes, a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more), and N transmission-side data signals to be transmitted from the outside. The sending input terminal of
The N transmission-side data signals are sequentially sampled in synchronization with the second clock signal every one cycle of the first clock signal, and the voltage levels of the sampled N transmission-side data signals are made different from each other. A transmission side signal processing unit for generating a transmission signal by
A transmission side output terminal for outputting the transmission signal to the transmission line,
The receiver is
A receiving-side input terminal for receiving the first clock signal, the second clock signal, and the transmission signal from the transmission path;
The transmission signal is sampled in synchronization with the second clock signal for each cycle of the first clock signal, and the voltage levels of the sampled transmission signal are set to the N transmission sides before the voltage level changes. A receiving-side signal processing unit that generates N receiving-side data signals by changing to a voltage level corresponding to the data signal;
A reception side output terminal for outputting the N reception side data signals to the outside.
　本発明の第２の局面は、本発明の第１の局面において、
　前記送信側信号処理部は、前記第２クロック信号に同期して、前記Ｎ個の送信側データ信号の位相を前記第２クロック信号の１周期分の期間ずつ異ならせる送信側位相制御部を含むことを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The transmission-side signal processing unit includes a transmission-side phase control unit that varies the phases of the N transmission-side data signals by a period corresponding to one cycle of the second clock signal in synchronization with the second clock signal. It is characterized by that.
　本発明の第３の局面は、本発明の第２の局面において、
　前記送信側信号処理部は、前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記Ｎ個の送信側データ信号をそれぞれサンプリングすると共に、各送信データ信号の電圧レベルが送信側第１レベルまたは送信側第２レベルであるときには、当該送信データ信号の電圧レベルを、Ｎ＋１個の所定の電圧レベルのうちのいずれか２つの電圧レベルの一方または他方にそれぞれ変換することにより、Ｎ＋１種類の電圧レベルからなる前記伝送信号を生成する伝送信号変換部をさらに含むことを特徴とする。 According to a third aspect of the present invention, in the second aspect of the present invention,
The transmission-side signal processing unit samples the N transmission-side data signals in synchronization with the second clock signal every cycle of the first clock signal, and the voltage level of each transmission data signal is transmitted. By converting the voltage level of the transmission data signal into one or the other of any two voltage levels of the N + 1 predetermined voltage levels, respectively, It further includes a transmission signal converter that generates the transmission signal having N + 1 types of voltage levels.
　本発明の第４の局面は、本発明の第３の局面において、
　前記伝送信号変換部はさらに、前記第１クロック信号の各周期においてサンプリングされるべき期間が連続する２つの前記送信側データ信号のうちの、先行の送信側データ信号の送信側第２レベルの変換後の電圧レベルと、後続の送信側データ信号の送信側第１レベルの変換後の電圧レベルとを互いに同じにすることを特徴とする。 According to a fourth aspect of the present invention, in the third aspect of the present invention,
The transmission signal converting unit further converts a transmission-side second level of a preceding transmission-side data signal out of two transmission-side data signals in which periods to be sampled in each cycle of the first clock signal are continuous. The subsequent voltage level and the voltage level after the conversion of the transmission side first level of the subsequent transmission side data signal are made the same.
　本発明の第５の局面は、本発明の第３の局面または第４の局面において、
　前記送信側位相制御部および前記伝送信号変換部は、１つの処理装置として実現されていることを特徴とする。 According to a fifth aspect of the present invention, in the third aspect or the fourth aspect of the present invention,
The transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device.
　本発明の第６の局面は、本発明の第３の局面から第５の局面までのいずれかにおいて、
　前記受信側信号処理部は、前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記伝送信号をサンプリングすると共に、サンプリングした当該伝送信号の電圧レベルのうちの、前記伝送信号変換部において前記送信側第１レベルから変換された電圧を、当該送信側第１レベルに対応する受信側第１レベルに変換し、前記送信側第２レベルから変換された電圧レベルを当該送信側第２レベルに対応する受信側第２レベルに変換することにより前記Ｎ個の受信側データ信号を生成する伝送信号逆変換部を含むことを特徴とする。 According to a sixth aspect of the present invention, in any one of the third to fifth aspects of the present invention,
The reception-side signal processing unit samples the transmission signal in synchronization with the second clock signal for each cycle of the first clock signal, and the transmission signal of the sampled voltage level of the transmission signal. The voltage converted from the first level on the transmission side in the conversion unit is converted to the first level on the reception side corresponding to the first level on the transmission side, and the voltage level converted from the second level on the transmission side is converted to the transmission side. A transmission signal inverse conversion unit that generates the N reception side data signals by converting the reception side second level corresponding to the second level is included.
　本発明の第７の局面は、本発明の第６の局面において、
　前記受信側信号処理部は、前記第２クロック信号に同期して、前記Ｎ個の受信側データ信号を互いに同位相にする受信側位相制御部をさらに含むことを特徴とする。 A seventh aspect of the present invention is the sixth aspect of the present invention,
The reception-side signal processing unit further includes a reception-side phase control unit that synchronizes the N reception-side data signals with each other in synchronization with the second clock signal.
　本発明の第８の局面は、本発明の第７の局面において、
　前記伝送信号逆変換部および前記受信側位相制御部は、１つの処理装置として実現されていることを特徴とする。 According to an eighth aspect of the present invention, in the seventh aspect of the present invention,
The transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device.
　本発明の第９の局面は、本発明の第１の局面において、
　前記送信部は、互いに電圧レベルの異なるＮ個のレベルシフト信号を生成するレベルシフト信号生成部をさらに含み、
　前記送信側信号処理部は、サンプリングした前記Ｎ個の送信側データ信号の電圧レベルを前記Ｎ個のレベルシフト信号に基づいて互いに異ならせることを特徴とする。 According to a ninth aspect of the present invention, in the first aspect of the present invention,
The transmission unit further includes a level shift signal generation unit that generates N level shift signals having different voltage levels.
The transmission-side signal processing unit is characterized in that the voltage levels of the sampled N transmission-side data signals are different from each other based on the N level-shifted signals.
　本発明の第１０の局面は、送信部と受信部との間で１本の伝送路により複数種類のデータのシリアル伝送を行う信号伝送装置における信号伝送方法であって、
　周期的に変化する第１クロック信号の１周期毎に、当該第１クロック信号の周波数をＮ（Ｎは２以上の整数）逓倍した第２クロック信号に同期して、伝送すべきＮ個の送信側データ信号を順にサンプリングすると共に、サンプリングした当該Ｎ個の送信側データ信号の電圧レベルを互いに異ならせることにより伝送信号を生成するステップと、
　前記伝送信号を、前記伝送路を介して前記送信部から前記受信部に伝送するステップと、
　前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記伝送信号をサンプリングすると共に、サンプリングした当該伝送信号の電圧レベルを、電圧レベルが変化する前の前記Ｎ個の送信側データ信号に対応する電圧レベルに変化させることによりそれぞれＮ個の受信側データ信号を生成し出力するステップとを備えることを特徴とする。 A tenth aspect of the present invention is a signal transmission method in a signal transmission device that performs serial transmission of a plurality of types of data through a single transmission path between a transmission unit and a reception unit,
N transmissions to be transmitted in synchronization with a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more) for each period of the periodically changing first clock signal. Sampling the side data signals in order, and generating a transmission signal by making the voltage levels of the sampled N transmission side data signals different from each other;
Transmitting the transmission signal from the transmitter to the receiver via the transmission path;
The transmission signal is sampled in synchronization with the second clock signal for each cycle of the first clock signal, and the voltage levels of the sampled transmission signal are set to the N transmission sides before the voltage level changes. And generating and outputting N receiving-side data signals by changing to a voltage level corresponding to the data signal.
　本発明の第１の局面によれば、送信部において、第１クロック信号および第２クロック信号のタイミングに基づいてＮ個の送信側データ信号を順にサンプリングすると共にこれらの電圧レベルを変化させることにより生成された伝送信号が生成され、当該送信部から受信部に１本の伝送路を介して伝送される。そして、受信部において、第１クロック信号および第２クロック信号に基づいて、伝送信号のうちのＮ個の送信側データ信号に対応する部分の電圧レベルにそれぞれ応じたＮ個の受信側データ信号が生成される。すなわち、第１クロック信号および第２クロック信号によって同期をとるのみならず、伝送信号のうちのＮ個の送信側データ信号に対応する部分の電圧レベルをそれぞれ異ならせているので、このような電圧レベルの相違に基づいて、例えば伝送欠陥を低減することができる。このため、Ｎ個のデータが１本の伝送路を用いて確実に伝送される。これにより、回路規模の増大を抑制できるので、コストの増大を抑えつつ複数種類のデータを伝送できる。また、換言すると、伝送路１本あたりのデータ伝送量が増加されるので、従来よりも効率的にデータ伝送を行うことができる。 According to the first aspect of the present invention, the transmitter unit sequentially samples the N transmission-side data signals based on the timings of the first clock signal and the second clock signal, and changes their voltage levels. The generated transmission signal is generated and transmitted from the transmitting unit to the receiving unit via one transmission path. Then, in the receiving unit, N reception-side data signals respectively corresponding to the voltage levels of the portions corresponding to the N transmission-side data signals in the transmission signal are based on the first clock signal and the second clock signal. Generated. That is, not only the first clock signal and the second clock signal are synchronized, but also the voltage levels of the portions corresponding to the N transmission-side data signals in the transmission signal are different from each other. Based on the difference in level, for example, transmission defects can be reduced. For this reason, N pieces of data are reliably transmitted using one transmission path. Thereby, since an increase in circuit scale can be suppressed, a plurality of types of data can be transmitted while suppressing an increase in cost. In other words, since the amount of data transmission per transmission line is increased, data transmission can be performed more efficiently than in the past.
　本発明の第２の局面によれば、Ｎ個の送信側データ信号の位相が第２クロック信号の１周期分の期間ずつずれるので、第１クロック信号の各周期においてＮ個の送信側データ信号を順にサンプリングできる。 According to the second aspect of the present invention, since the phases of the N transmission-side data signals are shifted by a period of one cycle of the second clock signal, N transmission-side data signals in each cycle of the first clock signal. Can be sampled in order.
　本発明の第３の局面によれば、送信側データ信号の電圧レベルが送信側第１レベルまたは送信側第２レベルであるときに、当該送信側データ信号の電圧レベルが、Ｎ＋１個の所定の電圧レベルのうちのいずれか２つの電圧レベルの一方または他方にそれぞれ変換されることにより、伝送信号の電圧レベルの種類がＮ＋１種類になる。このようなＮ＋１種類の電圧レベルからなる伝送信号を用いることにより、伝送信号における電圧レベルの相違に基づいて、例えば伝送結果の低減および／または同期ずれを解消できる。 According to the third aspect of the present invention, when the voltage level of the transmission side data signal is the transmission side first level or the transmission side second level, the voltage level of the transmission side data signal is N + 1 predetermined values. By converting each of the two voltage levels to one or the other of the two voltage levels, the type of the voltage level of the transmission signal becomes N + 1. By using such a transmission signal composed of N + 1 types of voltage levels, for example, a reduction in transmission result and / or a synchronization shift can be eliminated based on the difference in voltage level in the transmission signal.
　本発明の第４の局面によれば、送信部において、第１クロック信号の各周期においてサンプリングされるべき期間が連続する２つの送信側データ信号のうちの先行の送信側データ信号の送信側第２レベルの変換後の電圧レベルと、後続の送信側データ信号の送信側第１レベルの変換後の電圧レベルとが互いに同じになる。例えば、第１クロック信号の各周期において最初にサンプリングされるべき送信側データ信号の送信側第１レベルおよび送信側第２レベルの双方が、第１クロック信号の各周期において最後にサンプリングされるべき送信側データ信号の送信側第１レベルおよび送信側第２レベルの双方よりも大きいとする。このような場合、同期ずれが生じたとしても、Ｎ＋１種類の電圧レベルからなる伝送信号からＮ個の受信側データ信号を生成可能な受信部を用いることにより、伝送信号の電圧レベルの変化に基づいて、第１クロック信号の各周期における第２クロック信号の最初の周期を判別できるので、同期ずれを解消できる。 According to the fourth aspect of the present invention, in the transmitting unit, the transmitting side of the preceding transmitting side data signal out of the two transmitting side data signals in which the period to be sampled in each cycle of the first clock signal continues. The voltage level after the two-level conversion is the same as the voltage level after the conversion of the transmission-side first level of the subsequent transmission-side data signal. For example, both the transmitter first level and the transmitter second level of the transmitter data signal to be sampled first in each period of the first clock signal should be sampled last in each period of the first clock signal. It is assumed that the transmission side data signal is larger than both the transmission side first level and the transmission side second level. In such a case, even if a synchronization shift occurs, a reception unit that can generate N reception-side data signals from transmission signals having N + 1 types of voltage levels is used to change the voltage level of the transmission signal. Thus, since the first period of the second clock signal in each period of the first clock signal can be determined, the synchronization shift can be eliminated.
　本発明の第５の局面によれば、送信側位相制御部および伝送信号変換部が１つの処理装置として実現される。このため、送信側位相制御部および伝送信号変換部で互いに共通する構成要素を共有化することにより、送信部の規模を削減することができる。 According to the fifth aspect of the present invention, the transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device. For this reason, the scale of a transmission part can be reduced by sharing a common component with each other in a transmission side phase control part and a transmission signal conversion part.
　本発明の第６の局面によれば、受信部において、第１クロック信号の各周期における第２クロック信号の第１の周期～第Ｎの周期でそれぞれ、伝送信号のうちのＮ個の送信側データ信号に対応する部分がサンプリングされると共に、当該伝送信号のうちのＮ個の送信側データ信号に対応する部分の電圧レベルに基づいてそれぞれＮ個の受信側データ信号の電圧レベルが決定される。このような受信部を用いることによって、本発明の第３の局面から第５の局面までのいずれかと同様の効果を奏することができる。 According to the sixth aspect of the present invention, in the receiving unit, each of the N transmission sides of the transmission signal in the first cycle to the Nth cycle of the second clock signal in each cycle of the first clock signal. The portion corresponding to the data signal is sampled, and the voltage level of each of the N receiving data signals is determined based on the voltage level of the portion corresponding to the N transmitting data signals of the transmission signal. . By using such a receiving unit, it is possible to achieve the same effect as any of the third to fifth aspects of the present invention.
　本発明の第７の局面によれば、受信側位相制御部を用いることにより、Ｎ個の受信側データ信号の位相をそろえて出力することができる。 According to the seventh aspect of the present invention, by using the reception-side phase control unit, the phases of N reception-side data signals can be aligned and output.
　本発明の第８の局面によれば、伝送信号逆変換部および受信側位相制御部が１つの処理装置として実現される。このため、伝送信号逆変換部および受信側位相制御部で互いに共通する構成要素を共有化することにより、受信部の規模を削減することができる。 According to the eighth aspect of the present invention, the transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device. For this reason, it is possible to reduce the size of the reception unit by sharing the common components in the transmission signal inverse conversion unit and the reception-side phase control unit.
　本発明の第９の局面によれば、Ｎ個の送信側データ信号から伝送信号を生成するための電圧レベルをレベルシフト信号生成部を用いて生成することにより、本発明の第１の局面と同様の効果を奏することができる。 According to a ninth aspect of the present invention, by generating a voltage level for generating a transmission signal from N transmission-side data signals using a level shift signal generation unit, Similar effects can be achieved.
　本発明の第１０の局面によれば、信号伝送方法において、本発明の第１の局面と同様の効果を奏することができる。 According to the tenth aspect of the present invention, in the signal transmission method, the same effect as in the first aspect of the present invention can be achieved.
本発明の第１の実施形態に係る信号伝送システムの構成を示すブロック図である。1 is a block diagram illustrating a configuration of a signal transmission system according to a first embodiment of the present invention. 上記第１の実施形態における送信部の構成を示すブロック図である。It is a block diagram which shows the structure of the transmission part in the said 1st Embodiment. 上記第１の実施形態における送信側レベルコントロールプロセッサの構成を示すブロック図である。It is a block diagram which shows the structure of the transmission side level control processor in the said 1st Embodiment. 上記第１の実施形態における受信部の構成を示すブロック図である。It is a block diagram which shows the structure of the receiving part in the said 1st Embodiment. 上記第１の実施形態における受信側レベルコントロールプロセッサの構成を示すブロック図である。It is a block diagram which shows the structure of the receiving side level control processor in the said 1st Embodiment. 上記第１の実施形態における送信側位相制御処理前の送信側データ信号を示す信号波形図である。It is a signal waveform diagram which shows the transmission side data signal before the transmission side phase control process in the said 1st Embodiment. 上記第１の実施形態における送信側遅延回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the transmission side delay circuit in the said 1st Embodiment. 上記第１の実施形態における伝送信号変換回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the transmission signal converter circuit in the said 1st Embodiment. 上記第１の実施形態における伝送信号逆変換回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the transmission signal reverse conversion circuit in the said 1st Embodiment. 上記第１の実施形態における受信側位相制御処理前の受信側データ信号を示す信号波形図である。It is a signal waveform diagram which shows the receiving side data signal before the receiving side phase control process in the said 1st Embodiment. 上記第１の実施形態における受信側遅延回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the receiving side delay circuit in the said 1st Embodiment. 本発明の第２の実施形態における送信側レベルコントロールプロセッサの構成を示すブロック図である。It is a block diagram which shows the structure of the transmission side level control processor in the 2nd Embodiment of this invention. 上記第２の実施形態における受信側レベルコントロールプロセッサの構成を示すブロック図である。It is a block diagram which shows the structure of the receiving side level control processor in the said 2nd Embodiment. 本発明の第３の実施形態における送信側レベルコントロールプロセッサの構成を示すブロック図である。It is a block diagram which shows the structure of the transmission side level control processor in the 3rd Embodiment of this invention. 上記第３の実施形態における受信側レベルコントロールプロセッサの構成を示すブロック図である。It is a block diagram which shows the structure of the receiving side level control processor in the said 3rd Embodiment. 上記第３の実施形態における送信側読み出し制御回路の動作ついて説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the transmission side read-out control circuit in the said 3rd Embodiment. 上記第３の実施形態における伝送信号変換回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the transmission signal converter circuit in the said 3rd Embodiment. 上記第３の実施形態における伝送信号逆変換回路の動作を説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the transmission signal reverse conversion circuit in the said 3rd Embodiment. 上記第３の実施形態における受信側読み出し制御回路の動作について説明するための信号波形図である。It is a signal waveform diagram for demonstrating operation | movement of the receiving side read-out control circuit in the said 3rd Embodiment.
　以下、添付図面を参照しながら、本発明の実施形態について説明する。
　＜１．第１の実施形態＞
　＜１．１　全体構成＞
　図１は、本実施形態に係る信号伝送システムの構成を示すブロック図である。本信号伝送システムは、例えば、表示装置における表示制御回路からソースドライバへの画像データの伝送に用いられる。図１に示すように、本信号伝送システムは、ホスト１および信号伝送装置２を備えている。ホスト１は、典型的にはＣＰＵであり、信号伝送装置２に送信側制御信号ＣＴおよび受信側制御信号ＣＲを与える。送信側制御信号ＣＴは、より詳細には、Ｎ（Ｎ＝３）個の第１～第３送信側制御信号ＣＴａ～ＣＴｃからなっている。信号伝送装置２は、Ｎ（Ｎ＝３）種類の送信側データ信号ＤＴａ～ＤＴｃ、第１クロック信号としてのシステムクロックＳＹＳ、および第２クロック信号としてのサンプリングクロックＳＡＭを受け取り、これらの信号と上記送信側制御信号ＣＴおよび受信側制御信号ＣＲとに基づいてＮ（Ｎ＝３）種類の受信側データ信号ＤＲａ～ＤＲｃを出力する。なお、以下では、３種類の送信側データ信号ＤＴａ～ＤＴｃをそれぞれ第１～第３送信側データ信号といい、３種類の受信側データ信号ＤＲａ～ＤＲｃをそれぞれ第１～第３受信側データ信号という。第１～第３送信側データ信号ＤＴａ～ＤＴｃおよび第１～第３受信側データ信号ＤＲａ～ＤＲｃはビット列からなっている。 Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall configuration>
FIG. 1 is a block diagram showing the configuration of the signal transmission system according to the present embodiment. This signal transmission system is used, for example, for transmission of image data from a display control circuit in a display device to a source driver. As shown in FIG. 1, the signal transmission system includes a host 1 and a signal transmission device 2. The host 1 is typically a CPU, and provides the signal transmission apparatus 2 with a transmission side control signal CT and a reception side control signal CR. More specifically, the transmission side control signal CT includes N (N = 3) first to third transmission side control signals CTa to CTc. The signal transmission device 2 receives N (N = 3) types of transmission side data signals DTa to DTc, a system clock SYS as a first clock signal, and a sampling clock SAM as a second clock signal, and these signals and the above N (N = 3) types of reception side data signals DRa to DRc are output based on the transmission side control signal CT and the reception side control signal CR. In the following, the three types of transmission side data signals DTa to DTc are referred to as first to third transmission side data signals, respectively, and the three types of reception side data signals DRa to DRc are respectively referred to as first to third reception side data signals. That's it. The first to third transmission side data signals DTa to DTc and the first to third reception side data signals DRa to DRc are composed of bit strings.
　上記システムクロックＳＹＳおよびサンプリングクロックＳＡＭのそれぞれは周期的にハイレベルとローレベルとを繰り返す。サンプリングクロックＳＡＭはシステムクロックＳＹＳをＮ（Ｎ＝３）逓倍した信号である。以下では、システムクロックＳＹＳおよびサンプリングクロックＳＡＭの１周期分の期間をそれぞれ「システム期間」および「サンプリング期間」といい、以降の信号波形図中ではそれぞれ符号ＴＡおよびＴＢで表す。また、以降の信号波形図中では、Ｘ（Ｘは２以上の整数）サンプリング期間を「ＸＴＢ」で表す。さらに、各システム期間における１番目～３番目のサンプリング期間をそれぞれ「第１～第３サンプリング期間」という。 Each of the system clock SYS and the sampling clock SAM periodically repeats a high level and a low level. The sampling clock SAM is a signal obtained by multiplying the system clock SYS by N (N = 3). In the following, periods of one cycle of the system clock SYS and the sampling clock SAM are referred to as “system period” and “sampling period”, respectively, and are denoted by symbols TA and TB, respectively, in the subsequent signal waveform diagrams. In the following signal waveform diagrams, the X (X is an integer of 2 or more) sampling period is represented by “XTB”. Further, the first to third sampling periods in each system period are referred to as “first to third sampling periods”, respectively.
　信号伝送装置２は、送信部３、受信部４、および送信部３と受信部４とを互いに接続するための１本の伝送路５を備えている。ここで、伝送路５は差動伝送用またはシングルエンド伝送用のいずれの伝送路でも良い。また、「１本の伝送路」とは、差動伝送用の場合には１対の伝送路をいう。送信部３および受信部４には、図示しない手段で電源電圧が与えられている。送信部３は、上記第１～第３送信側データ信号ＤＴａ～ＤＴｃ、システムクロックＳＹＳ、サンプリングクロックＳＡＭ、および電源電圧を受け取り、これらに基づいて伝送信号ＴＳを生成する。伝送信号ＴＳは、伝送路５を介して、送信部３から受信部４に伝送される。受信部４は、伝送信号ＴＳ、システムクロックＳＹＳ、サンプリングクロックＳＡＭ、および電源電圧を受け取り、これらに基づいて上記第１～第３受信側データ信号ＤＲａ～ＤＲｃを生成する。すなわち、信号伝送装置２では、送信部３が受け取った３種類の第１～第３送信側データ信号ＤＴａ～ＤＴｃがそれぞれ３種類の第１～第３受信側データ信号ＤＲａ～ＤＲｃとして受信部４に伝送される。 The signal transmission device 2 includes a transmission unit 3, a reception unit 4, and a single transmission path 5 for connecting the transmission unit 3 and the reception unit 4 to each other. Here, the transmission line 5 may be either a differential transmission line or a single-ended transmission line. “One transmission line” means a pair of transmission lines in the case of differential transmission. The transmission unit 3 and the reception unit 4 are supplied with a power supply voltage by means not shown. The transmission unit 3 receives the first to third transmission side data signals DTa to DTc, the system clock SYS, the sampling clock SAM, and the power supply voltage, and generates a transmission signal TS based on these. The transmission signal TS is transmitted from the transmission unit 3 to the reception unit 4 via the transmission path 5. The receiving unit 4 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the power supply voltage, and generates the first to third receiving side data signals DRa to DRc based on these. That is, in the signal transmission device 2, the three types of first to third transmission side data signals DTa to DTc received by the transmission unit 3 are respectively converted into three types of first to third reception side data signals DRa to DRc. Is transmitted.
　＜１．１．１　送信部の構成＞
　図２は、本実施形態における送信部３の構成を示すブロック図である。図２に示すように、送信部３は、入力端子ＩＴ１、ＩＴ２、ＩＴ３ａ～ＩＴ３ｃ、ＩＴ４ａ～ＩＴ４ｃ、およびＩＴ５ａ～ＩＴ５ｃと、出力端子ＯＴと、送信側レベルシフタ３０と、送信側レベルコントロールプロセッサ３１とを備えている。ここで、入力端子ＩＴ１、ＩＴ２、ＩＴ３ａ～ＩＴ３ｃは送信側入力端子に対応している。出力端子ＯＴは送信側出力端子に対応している。 <1.1.1 Configuration of Transmitter>
FIG. 2 is a block diagram illustrating a configuration of the transmission unit 3 in the present embodiment. As shown in FIG. 2, the transmission unit 3 includes input terminals IT1, IT2, IT3a to IT3c, IT4a to IT4c, and IT5a to IT5c, an output terminal OT, a transmission side level shifter 30, and a transmission side level control processor 31. It has. Here, the input terminals IT1, IT2, IT3a to IT3c correspond to transmission side input terminals. The output terminal OT corresponds to the transmission side output terminal.
　入力端子ＩＴ１はシステムクロックＳＹＳを受け取るための端子である。入力端子ＩＴ２はサンプリングクロックＳＡＭを受け取るための端子である。入力端子ＩＴ３ａ～ＩＴ３ｃはそれぞれ第１～第３送信側データ信号ＤＴａ～ＤＴｃを受け取るための端子である。入力端子ＩＴ４ａ～ＩＴ４ｃはそれぞれ第１～第３送信側制御信号ＣＴａ～ＣＴｃを受け取るための端子である。入力端子ＩＴ５ａ～ＩＴ５ｃはそれぞれ上記電源電圧としての送信側第１～第３電源電圧ＶＨａ～ＶＨｃを受け取るための端子である。出力端子ＯＴは伝送信号ＴＳを出力するための端子である。送信側第１～第３電源電圧ＶＨａ～ＶＨｃは互いに電圧レベルが異なっている。以下では、送信側第１～第３電源電圧ＶＨａ～ＶＨｃの電圧レベルのことをもそれぞれＶＨａ～ＶＨｃで表すことがある。ここで、ＶＨａ～ＶＨｃレベルの大小関係は、ＶＨａ＞ＶＨｂ＞ＶＨｃである。 The input terminal IT1 is a terminal for receiving the system clock SYS. The input terminal IT2 is a terminal for receiving the sampling clock SAM. Input terminals IT3a to IT3c are terminals for receiving first to third transmission side data signals DTa to DTc, respectively. Input terminals IT4a to IT4c are terminals for receiving first to third transmission side control signals CTa to CTc, respectively. The input terminals IT5a to IT5c are terminals for receiving the transmission side first to third power supply voltages VHa to VHc as the power supply voltages, respectively. The output terminal OT is a terminal for outputting the transmission signal TS. The transmission-side first to third power supply voltages VHa to VHc have different voltage levels. Hereinafter, the voltage levels of the transmission-side first to third power supply voltages VHa to VHc may also be represented by VHa to VHc, respectively. Here, the magnitude relationship between the VHa to VHc levels is VHa> VHb> VHc.
　送信側レベルシフタ３０は、第１～第３送信側制御信号ＣＴａ～ＣＴｃおよび送信側第１～第３電源電圧ＶＨａ～ＶＨｃを受け取り、第１～第３送信側制御信号ＣＴａ～ＣＴｃの電圧レベルをそれぞれＶＨａ～ＶＨｃレベルにシフトさせた信号である第１～第３送信側レベルシフト信号ＬＳＴａ～ＬＳＴｃを生成し出力する。ここで、第１～第３送信側制御信号ＣＴａ～ＣＴｃの電圧レベルは、信号伝送装置２の動作時には固定されている。第１～第３送信側制御信号ＣＴａ～ＣＴｃの電圧レベルは互いに異なっていても良く、互いに同じであっても良い。ただし、第１～第３送信側制御信号ＣＴａ～ＣＴｃの電圧レベルは、典型的には、ＶＨａ～ＶＨｃレベルよりもそれぞれ小さい。 The transmission side level shifter 30 receives the first to third transmission side control signals CTa to CTc and the transmission side first to third power supply voltages VHa to VHc, and sets the voltage levels of the first to third transmission side control signals CTa to CTc. First to third transmission side level shift signals LSTa to LSTc, which are signals shifted to VHa to VHc levels, are generated and output. Here, the voltage levels of the first to third transmission side control signals CTa to CTc are fixed when the signal transmission device 2 is in operation. The voltage levels of the first to third transmission side control signals CTa to CTc may be different from each other or the same. However, the voltage levels of the first to third transmission side control signals CTa to CTc are typically smaller than the VHa to VHc levels, respectively.
　送信側レベルコントロールプロセッサ３１は、第１～第３送信側データ信号ＤＴａ～ＤＴｃ、システムクロックＳＹＳ、サンプリングクロックＳＡＭ、および送信側レベルシフタ３０から出力された第１～第３送信側レベルシフト信号ＬＳＴａ～ＬＳＴｃを受け取り、これらに基づいて伝送信号ＴＳを生成し出力する。 The transmission side level control processor 31 includes first to third transmission side data signals DTa to DTc, a system clock SYS, a sampling clock SAM, and first to third transmission side level shift signals LSTa output from the transmission side level shifter 30. LSTc is received, and based on these, a transmission signal TS is generated and output.
　本実施形態では、送信側レベルシフタ３０および送信側レベルコントロールプロセッサ３１により送信側信号処理部が実現されている。 In this embodiment, the transmission side signal processing unit is realized by the transmission side level shifter 30 and the transmission side level control processor 31.
　図３は、本実施形態における送信側レベルコントロールプロセッサ３１の構成を示すブロック図である。図３に示すように、送信側レベルコントロールプロセッサ３１は、送信側入力バッファ３１０、送信側遅延回路３１１、送信側データ判別回路３１２、伝送信号変換部としての伝送信号変換回路３１３、および送信側出力バッファ３１４を備えている。 FIG. 3 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment. As shown in FIG. 3, the transmission side level control processor 31 includes a transmission side input buffer 310, a transmission side delay circuit 311, a transmission side data discrimination circuit 312, a transmission signal conversion circuit 313 as a transmission signal conversion unit, and a transmission side output. A buffer 314 is provided.
　送信側入力バッファ３１０は、第１～第３送信側データ信号ＤＴａ～ＤＴｃを受け取るためのバッファである。 The transmission side input buffer 310 is a buffer for receiving the first to third transmission side data signals DTa to DTc.
　送信側遅延回路３１１は、第１～第３送信側データ信号ＤＴａ～ＤＴｃを送信側入力バッファ３１０を介して受け取り、サンプリングクロックＳＡＭのタイミングに基づいてこれらの第１～第３送信側データ信号ＤＴａ～ＤＴｃの位相を互いに異ならせ出力する。以下では、このように第１～第３送信側データ信号ＤＴａ～ＤＴｃの位相を互いに異ならせる処理のことを「送信側位相制御処理」という。本実施形態では、送信側遅延回路３１１により送信側位相制御部が実現されている。 The transmission side delay circuit 311 receives the first to third transmission side data signals DTa to DTc via the transmission side input buffer 310, and based on the timing of the sampling clock SAM, these first to third transmission side data signals DTa. .. DTc are output with different phases. Hereinafter, the process of making the phases of the first to third transmission side data signals DTa to DTc different from each other in this way is referred to as “transmission side phase control process”. In the present embodiment, a transmission side phase control unit is realized by the transmission side delay circuit 311.
　送信側データ判別回路３１２は、送信側位相制御処理後の第１～第３送信側データ信号ＤＴａ～ＤＴｃのそれぞれのビットデータ（“１”または“０”を示すデータをいう）が“１”または“０”のいずれを示すかをサンプリングクロックＳＡＭのタイミングに基づいて判別し、その判別結果としての第１～第３送信側判別信号ＲＴａ～ＲＴｃを出力する。ここで、各送信側データ信号の“１”を示すビットデータの電圧レベルは送信側第１レベルに相当し、“０”を示すビットデータの電圧レベルは送信側第２レベルに相当する。 The transmission side data discriminating circuit 312 has the bit data (referred to as data indicating “1” or “0”) of the first to third transmission side data signals DTa to DTc after the transmission side phase control processing being “1”. Whether “0” is indicated is determined based on the timing of the sampling clock SAM, and first to third transmission side determination signals RTa to RTc are output as the determination results. Here, the voltage level of the bit data indicating “1” in each transmission side data signal corresponds to the first level on the transmission side, and the voltage level of bit data indicating “0” corresponds to the second level on the transmission side.
　伝送信号変換回路３１３は、第１～第３送信側判別信号ＲＴａ～ＲＴｃを受け取り、システムクロックＳＹＳおよびサンプリングクロックＳＡＭのタイミングに基づいて第１～第３送信側判別信号ＲＴａ～ＲＴｃ（すなわち第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータ）を順にサンプリングすると共に、これらのデータの電圧レベルを変換することにより１つの伝送信号ＴＳを生成し出力する。具体的には、伝送信号変換回路３１３は、第１サンプリング期間でサンプリングした第１送信側判別信号ＲＴａ（すなわち第１送信側データ信号ＤＴａのビットデータ）が“１”または“０”を示す電圧レベルであればそれぞれＶＨａレベルまたはＶＨｂレベルに変換し、第２サンプリング期間でサンプリングした第２送信側判別信号ＲＴｂ（すなわち第２送信側データ信号ＤＴｂのビットデータ）が“１”または“０”を示す電圧レベルであればそれぞれＶＨｂレベルまたはＶＨｃレベルに変換し、第３サンプリング期間でサンプリングした第３送信側判別信号ＲＴｃ（すなわち第３送信側データ信号ＤＴｃのビットデータ）が“１”または“０”を示す電圧レベルであればそれぞれＶＨｃレベルまたは所定の電圧レベルとしてのＧＮＤレベル（接地レベル）に変換する。このようにして、伝送信号変換回路３１３は、第１～第３送信側判別信号ＲＴａ～ＲＴｃを１システム期間毎に順に並べると共にこれらの電圧レベルを上述のように変換した１つの伝送信号ＴＳを生成し出力する。以下では、伝送信号ＴＳのうちの、第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータに対応する部分をそれぞれ「第１～第３送受信データ」といい、それぞれ符号ＴＲ１～ＴＲ３で表す。なお、伝送信号変換回路３１３に送信側データ判別回路３１２の機能を設け、送信側データ判別回路３１２を設けない構成としても良い。 The transmission signal conversion circuit 313 receives the first to third transmission side discrimination signals RTa to RTc, and based on the timings of the system clock SYS and the sampling clock SAM, the first to third transmission side discrimination signals RTa to RTc (that is, the first transmission side discrimination signals RTa to RTc). (Bit data of third transmission side data signals DTa to DTc) are sequentially sampled, and one transmission signal TS is generated and output by converting the voltage level of these data. Specifically, the transmission signal conversion circuit 313 is a voltage at which the first transmission side discrimination signal RTa (that is, the bit data of the first transmission side data signal DTa) sampled in the first sampling period indicates “1” or “0”. If it is level, it is converted to VHa level or VHb level, respectively, and the second transmission side discrimination signal RTb (that is, bit data of the second transmission side data signal DTb) sampled in the second sampling period is “1” or “0”. If the voltage level shown in the figure is converted to the VHb level or the VHc level, the third transmission side discrimination signal RTc (that is, the bit data of the third transmission side data signal DTc) sampled in the third sampling period is “1” or “0”. "VHc level" or GND level as a predetermined voltage level. Converted to le (ground level). In this way, the transmission signal conversion circuit 313 arranges the first to third transmission side discrimination signals RTa to RTc in order for each system period, and also converts one transmission signal TS obtained by converting these voltage levels as described above. Generate and output. Hereinafter, portions of the transmission signal TS corresponding to the bit data of the first to third transmission side data signals DTa to DTc are referred to as “first to third transmission / reception data”, respectively, and are represented by symbols TR1 to TR3, respectively. . The transmission signal conversion circuit 313 may be provided with the function of the transmission side data determination circuit 312 and the transmission side data determination circuit 312 may not be provided.
　ここで、第１送受信データＴＲ１の“０”に対応する電圧レベルおよび第２送受信データＴＲ２の“１”に対応する電圧レベルは、互いに同じＶＨｂレベルである。第２送受信データＴＲ２の“０”に対応する電圧レベルおよび第３送受信データＴＲ３の“１”に対応する電圧レベルは、互いに同じＶＨｃレベルである。すなわち、各システム期間においてサンプリングされるべき期間が連続する２つの送信側データ信号のうちの先行の送信側データ信号の“０”の変換後の電圧レベルと、後続の送信側データ信号の“１”の変換後の電圧レベルとが互いに同じになっている。なお、第１送受信データＴＲ１の“１”に対応する電圧レベル（各システム期間の最初のサンプリング期間である第１サンプリング期間にサンプリングされる第１送信側データ信号ＤＴａの“１”を示すビットデータの変換後の電圧レベル）はＶＨａレベルであり、当該ＶＨａレベルは他と重複していない。同様に、第３送受信データＴＲ３の“０”に対応する電圧レベル（各システム期間の最後のサンプリング期間である第３サンプリング期間にサンプリングされる第３送信側データ信号ＤＴｃの変換後の電圧レベル）はＧＮＤレベルであり、当該ＧＮＤレベルは他の重複していない。このようにして、本実施形態における伝送信号ＴＳを実現する電圧レベルの種類は、Ｎ＋１種類（４種類）になる。 Here, the voltage level corresponding to “0” of the first transmission / reception data TR1 and the voltage level corresponding to “1” of the second transmission / reception data TR2 are the same VHb level. The voltage level corresponding to “0” of the second transmission / reception data TR2 and the voltage level corresponding to “1” of the third transmission / reception data TR3 are the same VHc level. That is, the voltage level after conversion of “0” of the preceding transmission side data signal of the two transmission side data signals in which the period to be sampled in each system period is continuous, and “1” of the subsequent transmission side data signal. The converted voltage levels are the same as each other. The voltage level corresponding to “1” of the first transmission / reception data TR1 (bit data indicating “1” of the first transmission side data signal DTa sampled in the first sampling period which is the first sampling period of each system period) Is the VHa level, and the VHa level does not overlap with others. Similarly, the voltage level corresponding to “0” of the third transmission / reception data TR3 (the voltage level after conversion of the third transmission side data signal DTc sampled in the third sampling period which is the last sampling period of each system period) Is a GND level, and the GND level does not overlap with other. In this way, there are N + 1 types (four types) of voltage levels for realizing the transmission signal TS in the present embodiment.
　送信側出力バッファ３１４は、伝送信号ＴＳをシリアルに出力するためのバッファである。送信側出力バッファ３１４から出力された伝送信号ＴＳは、伝送路５を介して受信部４に伝送される。 The transmission side output buffer 314 is a buffer for serially outputting the transmission signal TS. The transmission signal TS output from the transmission side output buffer 314 is transmitted to the receiving unit 4 via the transmission path 5.
　＜１．１．２　受信部の構成＞
　図４は、本実施形態における受信部４の構成を示すブロック図である。図４に示すように、受信部４は、入力端子ＩＲ１～ＩＲ５と、出力端子ＯＲａ～ＯＲｃと、受信側レベルシフタ４０と、受信側レベルコントロールプロセッサ４１とを備えている。ここで、入力端子ＩＲ１～ＩＲ３は受信側入力端子に対応している。出力端子ＯＲａ～ＯＲｃは受信側出力端子に対応している。 <1.1.2 Configuration of receiving unit>
FIG. 4 is a block diagram showing a configuration of the receiving unit 4 in the present embodiment. As shown in FIG. 4, the receiving unit 4 includes input terminals IR1 to IR5, output terminals ORa to ORc, a receiving side level shifter 40, and a receiving side level control processor 41. Here, the input terminals IR1 to IR3 correspond to receiving side input terminals. The output terminals ORa to ORc correspond to reception side output terminals.
　入力端子ＩＲ１はシステムクロックＳＹＳを受け取るための端子である。入力端子ＩＲ２はサンプリングクロックＳＡＭを受け取るための端子である。入力端子ＩＲ３は伝送信号ＴＳを受け取るための端子である。入力端子ＩＲ４は受信側制御信号ＣＲを受け取るための信号である。入力端子ＩＲ５は上記電源電圧としての受信側電源電圧ＶＨを受け取るための端子である。以下では、受信側電源電圧ＶＨの電圧レベルのことをもＶＨで表すことがある。また、出力端子ＯＲａ～ＯＲｃはそれぞれ第１～第３受信側データ信号ＤＲａ～ＤＲｃを出力するための端子である。 The input terminal IR1 is a terminal for receiving the system clock SYS. The input terminal IR2 is a terminal for receiving the sampling clock SAM. The input terminal IR3 is a terminal for receiving the transmission signal TS. The input terminal IR4 is a signal for receiving the receiving side control signal CR. The input terminal IR5 is a terminal for receiving the reception-side power supply voltage VH as the power supply voltage. Hereinafter, the voltage level of the reception-side power supply voltage VH may also be expressed as VH. The output terminals ORa to ORc are terminals for outputting the first to third receiving side data signals DRa to DRc, respectively.
　受信側レベルシフタ４０は、受信側制御信号ＣＲおよび送信側電源電圧ＶＨを受け取り、受信側制御信号ＣＲの電圧レベルをＶＨレベルにシフトさせた信号である受信側レベルシフト信号ＬＳＲを生成し出力する。ここで、受信側制御信号ＣＲの電圧レベルは、信号伝送装置２の動作時には固定されている。受信側制御信号ＣＲの電圧レベルは、典型的には、ＶＨレベルよりも小さい。 The reception-side level shifter 40 receives the reception-side control signal CR and the transmission-side power supply voltage VH, and generates and outputs a reception-side level shift signal LSR that is a signal obtained by shifting the voltage level of the reception-side control signal CR to the VH level. Here, the voltage level of the reception-side control signal CR is fixed when the signal transmission device 2 operates. The voltage level of the reception side control signal CR is typically smaller than the VH level.
　受信側レベルコントロールプロセッサ４１は、伝送信号ＴＳ、システムクロックＳＹＳ、サンプリングクロックＳＡＭ、および受信側レベルシフタ４０から出力された受信側レベルシフト信号ＬＳＲを受け取り、これらに基づいて第１～第３受信側データ信号ＤＲａ～ＤＲｃを生成し出力する。 The receiving side level control processor 41 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the receiving side level shift signal LSR outputted from the receiving side level shifter 40, and based on these, the first to third receiving side data Generate and output signals DRa to DRc.
　本実施形態では、受信側レベルシフタ４０および受信側レベルコントロールプロセッサ４１により受信側信号処理部が実現されている。 In the present embodiment, the reception side signal processing unit is realized by the reception side level shifter 40 and the reception side level control processor 41.
　図５は、本実施形態における受信側レベルコントロールプロセッサ４１の構成を示すブロック図である。図５に示すように、受信側レベルコントロールプロセッサ４１は、受信側入力バッファ４１０、受信側データ判別回路４１１、伝送信号逆変換部としての伝送信号逆変換回路４１２、受信側遅延回路４１３、および受信側出力バッファ４１４を備えている。 FIG. 5 is a block diagram showing a configuration of the receiving side level control processor 41 in the present embodiment. As illustrated in FIG. 5, the reception-side level control processor 41 includes a reception-side input buffer 410, a reception-side data determination circuit 411, a transmission signal inverse conversion circuit 412 as a transmission signal inverse conversion unit, a reception-side delay circuit 413, and a reception side. A side output buffer 414 is provided.
　受信側入力バッファ４１０は、伝送信号ＴＳをシリアルに受信するためのバッファである。 The receiving side input buffer 410 is a buffer for receiving the transmission signal TS serially.
　受信側データ判別回路４１１は、伝送信号ＴＳの第１～第３送受信データＴＲ１～ＴＲ３が、ＶＨａ～ＶＨｃまたはＧＮＤレベルのいずれを示すかをサンプリングクロックＳＡＭのタイミングに基づいて判別し、これらの判別結果としての受信側判別信号ＲＲを出力する。 The reception-side data determination circuit 411 determines whether the first to third transmission / reception data TR1 to TR3 of the transmission signal TS indicate VHa to VHc or the GND level based on the timing of the sampling clock SAM, and these determinations. As a result, the receiving side discrimination signal RR is output.
　伝送信号逆変換回路４１２は、受信側判別信号ＲＲを受け取り、システムクロックＳＹＳおよびサンプリングクロックＳＡＭのタイミングに基づいて、受信側判別信号ＲＲ（すなわち第１～第３送受信データＴＲ１～ＴＲ３）をサンプリングすると共に、第１～第３送受信データＴＲ１～ＴＲ３の電圧レベルを変換することによりそれぞれ第１～第３受信側データ信号ＤＲａ～ＤＲｃを生成し出力する。具体的には、伝送信号逆変換回路４１２は、第１送受信データＴＲ１に対応する受信側判別信号ＲＲのサンプリング時に、受信側判別信号ＲＲがＶＨａまたはＶＨｂレベルであれば、それぞれ“１”を示す電圧レベル（ここではＶＨレベルであるものとする）または“０”を示す電圧レベル（ここではＧＮＤレベルであるものとする）の第１受信側データ信号ＤＲａを生成する。また、伝送信号逆変換回路４１２は、第２送受信データＴＲ２に対応する受信側判別信号ＲＲのサンプリング時に、受信側判別信号ＲＲがＶＨｂまたはＶＨｃレベルであれば、それぞれ“１”または“０”を示す電圧レベルの第２受信側データ信号ＤＲｂを生成する。また、伝送信号逆変換回路４１２は、第３送受信データＴＲ３に対応する受信側判別信号ＲＲのサンプリング時に、受信側判別信号ＲＲがＶＨｃまたはＧＮＤレベルであれば、それぞれ“１”または“０”を示す電圧レベルの第３受信側データＤＲｃを生成する。ここで、第１～第３受信側データ信号ＤＲａ～ＤＲｃの“１”を示す電圧レベルは受信側第１レベルに相当し、“０”を示す電圧レベルは受信側第２レベルに相当する。ここで生成される第１～第３受信側データ信号ＤＲａ～ＤＲｃは、互いに位相が異なっている。なお、伝送信号逆変換回路４１２に受信側データ判別回路４１１の機能を設け、受信側データ判別回路４１１を設けない構成としても良い。 The transmission signal inverse conversion circuit 412 receives the reception side determination signal RR and samples the reception side determination signal RR (that is, the first to third transmission / reception data TR1 to TR3) based on the timings of the system clock SYS and the sampling clock SAM. At the same time, by converting the voltage levels of the first to third transmission / reception data TR1 to TR3, the first to third reception-side data signals DRa to DRc are generated and output, respectively. Specifically, the transmission signal inverse conversion circuit 412 indicates “1” if the reception side determination signal RR is at the VHa or VHb level when the reception side determination signal RR corresponding to the first transmission / reception data TR1 is sampled. A first receiving side data signal DRa having a voltage level (here, assumed to be VH level) or a voltage level indicating “0” (here, assumed to be GND level) is generated. Further, the transmission signal inverse conversion circuit 412 sets “1” or “0” if the reception side determination signal RR is at the VHb or VHc level when the reception side determination signal RR corresponding to the second transmission / reception data TR2 is sampled. The second receiving side data signal DRb having the voltage level shown is generated. In addition, the transmission signal inverse conversion circuit 412 sets “1” or “0” if the reception side determination signal RR is VHc or GND level when the reception side determination signal RR corresponding to the third transmission / reception data TR3 is sampled. The third receiving side data DRc having the voltage level shown is generated. Here, the voltage level indicating “1” of the first to third receiving side data signals DRa to DRc corresponds to the receiving side first level, and the voltage level indicating “0” corresponds to the receiving side second level. The first to third receiving side data signals DRa to DRc generated here have different phases. The transmission signal inverse conversion circuit 412 may be provided with the function of the reception side data determination circuit 411 and the reception side data determination circuit 411 may not be provided.
　受信側遅延回路４１３は、伝送信号逆変換回路４１２から出力された第１～第３受信側データ信号ＤＲａ～ＤＲｃを受け取り、サンプリングクロックＳＡＭのタイミングに基づいてこれらの第１～第３受信側データ信号ＤＲａ～ＤＲｃの位相を互いに同一にし出力する。以下では、このように第１～第３受信側データ信号ＤＲａ～ＤＲｃの位相を互いに同一にする処理のことを「受信側位相制御処理」という。本実施形態では、受信側遅延回路４１３により受信側位相制御部が実現されている。 The reception-side delay circuit 413 receives the first to third reception-side data signals DRa to DRc output from the transmission signal inverse conversion circuit 412, and based on the timing of the sampling clock SAM, these first to third reception-side data The signals DRa to DRc are output with the same phase. Hereinafter, the process of making the phases of the first to third reception-side data signals DRa to DRc identical to each other is referred to as “reception-side phase control process”. In the present embodiment, a reception-side phase control unit is realized by the reception-side delay circuit 413.
　受信側出力バッファ４１４は、受信側位相制御処理により互いに同位相になった第１～第３受信側データ信号ＤＲａ～ＤＲｃを出力するためのバッファである。これらの第１～第３受信側データ信号ＤＲａ～ＤＲｃは、受信側出力バッファ４１４を介して外部に出力される。 The reception-side output buffer 414 is a buffer for outputting the first to third reception-side data signals DRa to DRc that are in phase with each other by the reception-side phase control process. These first to third reception side data signals DRa to DRc are output to the outside via the reception side output buffer 414.
　＜１．２　動作＞
　以上に示した構成により実現される本実施形態に係る信号伝送システムの動作について、送信側と受信側とに分けて説明する。 <1.2 Operation>
The operation of the signal transmission system according to the present embodiment realized by the configuration described above will be described separately for the transmission side and the reception side.
　＜１．２．１　送信側の動作＞
　図６は、本実施形態における送信側位相制御処理前の第１～第３送信側データ信号ＤＴａ～ＤＴｃを示す信号波形図である。本明細書では、第１～第３送信側データ信号ＤＴａ～ＤＴｃのそれぞれが８ビットデータ単位で１つのデータを表すものとする。ここで、第１送信側データ信号ＤＴａの８ビットデータをそれぞれＡ０～Ａ７で表し、第２送信側データ信号ＤＴｂの８ビットデータをそれぞれＢ０～Ｂ７で表し、第３送信側データ信号ＤＴｃの８ビットデータをそれぞれＣ０～Ｃ７で表す。なお、第１～第３受信側データ信号ＤＲａ～ＤＲｃのそれぞれも８ビットデータであり、第１受信側データ信号ＤＲａの８ビットデータもそれぞれＡ０～Ａ７で表し、第２受信側データ信号ＤＲｂの８ビットデータもそれぞれＢ０～Ｂ７で表し、第３受信側データ信号ＤＲｃの８ビットデータもそれぞれＣ０～Ｃ７で表す。本信号伝送システムが表示装置における表示制御回路からソースドライバへの画像データの伝送に用いられる場合、第１送信側データ信号ＤＴａ（第１受信側データ信号ＤＲａ）、第２送信側データ信号ＤＴｂ（第２受信側データ信号ＤＲｂ）、および第３送信側データ信号ＤＴｃ（第３受信側データ信号ＤＲｃ）は例えばそれぞれＲ用、Ｇ用、およびＢ用の８ビットの画像データに対応する。 <1.2.1 Operation on transmitting side>
FIG. 6 is a signal waveform diagram showing the first to third transmission side data signals DTa to DTc before the transmission side phase control processing in this embodiment. In this specification, it is assumed that each of the first to third transmission side data signals DTa to DTc represents one piece of data in units of 8 bits. Here, 8-bit data of the first transmission-side data signal DTa is represented by A0 to A7, 8-bit data of the second transmission-side data signal DTb is represented by B0 to B7, respectively, and 8 of the third transmission-side data signal DTc. Bit data are represented by C0 to C7, respectively. Each of the first to third reception side data signals DRa to DRc is also 8-bit data, and the 8-bit data of the first reception side data signal DRa is also represented by A0 to A7, respectively. The 8-bit data is also represented by B0 to B7, respectively, and the 8-bit data of the third receiving side data signal DRc is also represented by C0 to C7, respectively. When this signal transmission system is used for transmission of image data from a display control circuit to a source driver in a display device, a first transmission side data signal DTa (first reception side data signal DRa), a second transmission side data signal DTb ( The second reception side data signal DRb) and the third transmission side data signal DTc (third reception side data signal DRc) correspond to, for example, 8-bit image data for R, G, and B, respectively.
　図６に示すように、各送信側データ信号のビットデータは、２ビットデータ毎の２サンプリング期間（２ＴＢ）において空白になっている。以下では、このように空白となっているデータを「ＮＵＬＬデータ」といい、図６および以降の図では符号「ＮＵＬＬ」で表している。また、各受信側データ信号のビットデータは、２サンプリング期間（２ＴＢ）毎に、サンプリングクロックＳＡＭの電圧レベルが立ち上がるタイミングで変化する。 As shown in FIG. 6, the bit data of each transmission-side data signal is blank in two sampling periods (2 TB) for each 2-bit data. Hereinafter, such blank data is referred to as “NULL data”, and in FIG. 6 and the subsequent drawings, the data is represented by “NULL”. In addition, the bit data of each reception-side data signal changes at the timing when the voltage level of the sampling clock SAM rises every two sampling periods (2TB).
　図７は、本実施形態における送信側遅延回路３１１の動作を説明するための信号波形図である。図７に示すように、送信側遅延回路３１１は、第１～第３送信側データ信号ＤＴａ～ＤＴｃに対してサンプリングクロックＳＡＭのタイミングに基づいた送信側位相制御処理を施す。具体的には、第１送信側データ信号ＤＴａに対して、第２送信側データ信号ＤＴｂおよび第３送信側データ信号ＤＴｃがそれぞれ１サンプリング期間および２サンプリング期間遅延する処理を施す。このような送信側位相制御処理後の第１～第３送信側データ信号ＤＴａ～ＤＴｃは、送信側データ判別回路３１２に与えられた後、上述の第１～第３送信側判別信号ＲＴａ～ＲＴｃとして出力される。 FIG. 7 is a signal waveform diagram for explaining the operation of the transmission side delay circuit 311 in this embodiment. As shown in FIG. 7, the transmission-side delay circuit 311 performs transmission-side phase control processing based on the timing of the sampling clock SAM on the first to third transmission-side data signals DTa to DTc. Specifically, the first transmission side data signal DTa is subjected to processing in which the second transmission side data signal DTb and the third transmission side data signal DTc are delayed by one sampling period and two sampling periods, respectively. The first to third transmission side data signals DTa to DTc after such transmission side phase control processing are given to the transmission side data determination circuit 312 and then the first to third transmission side determination signals RTa to RTc described above. Is output as
　図８は、本実施形態における伝送信号変換回路３１３の動作を説明するための信号波形図である。なお、本図で示される第１～第３送信側データ信号ＤＴａ～ＤＴｃは実際にはそれぞれ第１～第３送信側判別信号ＲＴａ～ＲＴｃに相当するものであるが、便宜上、以下ではこれらを第１～第３送信側データ信号ＤＴａ～ＤＴｃとして説明する（後述の図１７でも同様である）。また、以下では、連続する８つのシステム期間ＴＡをそれぞれ「第０～第７システム期間」といい、それぞれ符号ＴＡ０～ＴＡ７で表す。 FIG. 8 is a signal waveform diagram for explaining the operation of the transmission signal conversion circuit 313 in this embodiment. Note that the first to third transmission side data signals DTa to DTc shown in the figure are actually equivalent to the first to third transmission side discrimination signals RTa to RTc, respectively. Explanation will be given as first to third transmission side data signals DTa to DTc (the same applies to FIG. 17 described later). In the following, eight consecutive system periods TA are referred to as “0th to 7th system periods”, respectively, and are represented by symbols TA0 to TA7, respectively.
　本実施形態における伝送信号生成回路３１３では、第０～第７システム期間ＴＡ０～ＴＡ７において、８ビット分の第１～第３送信側データ信号ＤＴａ～ＤＴｃ（すなわち、合計２４ビット分のデータ）に相当する伝送信号ＴＳが生成される。なお、本実施形態および後述の第３の実施形態では図８に示すように、８ビット分の第１～第３送信側データ信号ＤＴａ～ＤＴｃはそれぞれ「１１１０１１０１」、「０１１００１０１」、および「１０１１１００１」を示すものとする。なお、ＮＵＬＬデータはデータとして考慮されない。 In the transmission signal generation circuit 313 according to the present embodiment, the first to third transmission side data signals DTa to DTc for 8 bits (that is, data for a total of 24 bits) in the 0th to seventh system periods TA0 to TA7. A corresponding transmission signal TS is generated. In this embodiment and the third embodiment to be described later, as shown in FIG. 8, the first to third transmission side data signals DTa to DTc for 8 bits are “11101101”, “01100101”, and “10111001”, respectively. ". Note that NULL data is not considered as data.
　各システム期間における第１～第３サンプリング期間では、伝送信号変換回路３１３によって、第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータにそれぞれ基づいて伝送信号ＴＳの電圧レベルが決定される。 In the first to third sampling periods in each system period, the transmission signal conversion circuit 313 determines the voltage level of the transmission signal TS based on the bit data of the first to third transmission side data signals DTa to DTc.
　まず、第０システム期間ＴＡ０において、第１サンプリング期間では、サンプリングすべき第１送信側データ信号ＤＴａが“１”であるビットデータＡ０を示しているので、伝送信号ＴＳの第１送受信データＴＲ１の電圧レベルは第１送信側データＤＴａの“１”に対応するＶＨａレベルになる。第２サンプリング期間では、サンプリングすべき第２送信側データ信号ＤＴｂが“０”であるビットデータＢ０を示しているので、伝送信号ＴＳの第２送受信データＴＲ２の電圧レベルは第２送信側データ信号ＤＴｂの“０”に対応するＶＨｃレベルになる。第３サンプリング期間では、サンプリングすべき第３送信側データ信号ＤＴｃが“１”であるビットデータＣ０を示しているので、伝送信号ＴＳの第３送受信データＴＲ３の電圧レベルは第３送信側データＤＴｃの“１”に対応するＶＨｃレベルになる。このようにして、１システム期間分の伝送信号ＴＳは、各送信側データ信号の１ビット分のビットデータ（すなわち、合計３ビット分のビットデータ）を示すことになる。 First, in the 0th system period TA0, in the first sampling period, the bit data A0 in which the first transmission side data signal DTa to be sampled is “1” indicates the first transmission / reception data TR1 of the transmission signal TS. The voltage level becomes a VHa level corresponding to “1” of the first transmission side data DTa. In the second sampling period, since the second transmission side data signal DTb to be sampled indicates the bit data B0 which is “0”, the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the second transmission side data signal. It becomes the VHc level corresponding to “0” of DTb. In the third sampling period, since the third transmission side data signal DTc to be sampled indicates the bit data C0 of “1”, the voltage level of the third transmission / reception data TR3 of the transmission signal TS is the third transmission side data DTc. VHc level corresponding to “1”. In this way, the transmission signal TS for one system period indicates bit data for one bit of each transmission-side data signal (that is, bit data for a total of three bits).
　次に、第１システム期間ＴＡ１において、第１サンプリング期間では、サンプリングすべき第１送信側データ信号ＤＴａが“１”であるビットデータＡ１を示しているので、伝送信号ＴＳの第１送受信データＴＲ１の電圧レベルは第１送信側データ信号ＤＴａの“１”に対応するＶＨａレベルになる。第２サンプリング期間では、サンプリングすべき第２送信側データＤＴｂが“１”であるビットデータＢ１を示しているので、伝送信号ＴＳの第２送受信データＴＲ２の電圧レベルは第２送信側データ信号ＤＴｂの“１”に対応するＶＨｂレベルになる。第３サンプリング期間では、サンプリングすべき第３送信側データ信号ＤＴｃが“０”であるビットデータＣ０を示しているので、伝送信号ＴＳの第３送受信データＴＲ３の電圧レベルは第３送信側データ信号ＤＴｃの“０”に対応するＧＮＤレベルになる。 Next, in the first system period TA1, in the first sampling period, the bit data A1 in which the first transmission side data signal DTa to be sampled is “1” indicates the first transmission / reception data TR1 of the transmission signal TS. The voltage level becomes a VHa level corresponding to “1” of the first transmission side data signal DTa. In the second sampling period, bit data B1 in which the second transmission side data DTb to be sampled is “1” indicates the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the second transmission side data signal DTb. VHb level corresponding to “1”. In the third sampling period, the third transmission side data signal DTc to be sampled indicates bit data C0 that is “0”, so the voltage level of the third transmission / reception data TR3 of the transmission signal TS is the third transmission side data signal. It becomes the GND level corresponding to “0” of DTc.
　第２システム期間ＴＡ２～第７システム期間ＴＡ７、および後続の各システム期間においても同様の手順により伝送信号ＴＳの各送受信データの電圧レベルが決定されることにより、伝送信号変換回路３１３において伝送信号ＴＳが生成される。このようにして生成された伝送信号ＴＳは、送信側出力バッファ３１４および伝送路５を介して受信部２に伝送される。 In the second system period TA2 to the seventh system period TA7 and each subsequent system period, the transmission signal TS is determined in the transmission signal conversion circuit 313 by determining the voltage level of each transmission / reception data of the transmission signal TS by the same procedure. Is generated. The transmission signal TS generated in this way is transmitted to the receiving unit 2 via the transmission side output buffer 314 and the transmission path 5.
　＜１．２．２　受信側の動作＞
　図９は、本実施形態における伝送信号逆変換回路４１２の動作を説明するための信号波形図である。なお、本図で示される第１～第３受信側データ信号ＤＲａ～ＤＲｃは実際には、伝送信号ＴＳに基づいて生成された受信側判別信号ＲＲに基づいて得られるものであるが、便宜上、以下の説明では、これらの第１～第３受信側データ信号ＤＲａ～ＤＲｃが伝送信号ＴＳから直接得られるものとして説明する（後述の図１８でも同様である）。 <1.2.2 Operation on receiving side>
FIG. 9 is a signal waveform diagram for explaining the operation of the transmission signal inverse conversion circuit 412 in this embodiment. Note that the first to third reception side data signals DRa to DRc shown in this figure are actually obtained based on the reception side determination signal RR generated based on the transmission signal TS. In the following description, these first to third receiving side data signals DRa to DRc will be described as being obtained directly from the transmission signal TS (the same applies to FIG. 18 described later).
　本実施形態における伝送信号逆変換回路４１２では、第０～第７システム期間ＴＡ０～ＴＡ７において、伝送信号ＴＳに基づいて、８ビット分の第１～第３受信側データ信号ＤＲａ～ＤＲｃ（すなわち、合計２４ビット分のデータ）が生成される。なお、第０～第７システム期間ＴＡ０～ＴＡ７は便宜上の名称であるので、送信側と受信側との第０～第７システム期間ＴＡ０～ＴＡ７のタイミングは互いに一致する必要はない。 In the transmission signal inverse conversion circuit 412 in this embodiment, in the 0th to 7th system periods TA0 to TA7, based on the transmission signal TS, 8-bit first to third receiving side data signals DRa to DRc (ie, A total of 24 bits of data) is generated. Since the 0th to 7th system periods TA0 to TA7 are names for convenience, the timings of the 0th to 7th system periods TA0 to TA7 on the transmitting side and the receiving side do not have to coincide with each other.
　各システム期間における第１～第３サンプリング期間ではそれぞれ、伝送信号逆変換回路４１２によって、伝送信号ＴＳの第１～第３送受信データＴＲ１～ＴＲ３がサンプリングされると共に、第１～第３送受信データＴＲ１～ＴＲ３の電圧レベルに基づいてそれぞれ第１～第３受信側データ信号ＤＲａ～ＤＲａのビットデータが決定される。 In the first to third sampling periods in each system period, the transmission signal inverse conversion circuit 412 samples the first to third transmission / reception data TR1 to TR3 of the transmission signal TS, and the first to third transmission / reception data TR1. Bit data of the first to third receiving data signals DRa to DRa are determined based on the voltage levels of .about.TR3, respectively.
　まず、第０システム期間ＴＡ０において、第１サンプリング期間では伝送信号ＴＳの第１送受信データＴＲ１の電圧レベルがＶＨａレベルであるので、第１受信側データ信号ＤＲａのビットデータＡ０は“１”になる。なお、受信側では、“１”を示すビットデータはＶＨレベルにより、“０”を示すビットデータはＧＮＤレベルにより実現される。第２サンプリング期間では伝送信号ＴＳの第２送受信データＴＲ２の電圧レベルがＶＨｃレベルであるので、第２受信側データ信号ＤＲｂのビットデータＢ０は“０”になる。第３サンプリング期間では伝送信号ＴＳの第３送受信データＴＲ３の電圧レベルがＶＨｃレベルであるので、第３受信側データ信号ＤＲｃのビットデータＣ０は“１”になる。このようにして、１システム期間分の伝送信号ＴＳにより、各受信側データ信号の１ビット分のビットデータ（すなわち、合計３ビット分のビットデータ）が得られる。 First, in the 0th system period TA0, since the voltage level of the first transmission / reception data TR1 of the transmission signal TS is the VHa level in the first sampling period, the bit data A0 of the first reception side data signal DRa becomes “1”. . On the receiving side, bit data indicating “1” is realized by the VH level, and bit data indicating “0” is realized by the GND level. In the second sampling period, since the voltage level of the second transmission / reception data TR2 of the transmission signal TS is the VHc level, the bit data B0 of the second reception side data signal DRb is “0”. In the third sampling period, since the voltage level of the third transmission / reception data TR3 of the transmission signal TS is the VHc level, the bit data C0 of the third reception-side data signal DRc is “1”. In this manner, 1-bit bit data of each reception-side data signal (that is, bit data for a total of 3 bits) is obtained from the transmission signal TS for one system period.
　次に、第１システム期間ＴＡ１において、第１サンプリング期間では伝送信号ＴＳの第１送受信データＴＲ１の電圧レベルがＶＨａレベルであるので、第１受信側データＤＲａのビットデータＡ１は“１”になる。第２サンプリング期間では伝送信号ＴＳの第２送受信データＴＲ２の電圧レベルがＶＨｂであるので、第２受信側データ信号ＤＲｂのビットデータＢ１は“１”になる。第３サンプリング期間では伝送信号ＴＳの第３送受信データＴＲ３の電圧レベルがＧＮＤレベルであるので、第３受信側データ信号ＤＲｃのビットデータＣ１は“０”になる。 Next, in the first system period TA1, since the voltage level of the first transmission / reception data TR1 of the transmission signal TS is the VHa level in the first sampling period, the bit data A1 of the first reception side data DRa becomes “1”. . In the second sampling period, since the voltage level of the second transmission / reception data TR2 of the transmission signal TS is VHb, the bit data B1 of the second reception side data signal DRb is “1”. In the third sampling period, since the voltage level of the third transmission / reception data TR3 of the transmission signal TS is the GND level, the bit data C1 of the third reception-side data signal DRc is “0”.
　第２システム期間ＴＡ２～第７システム期間ＴＡ７、および後続の各システム期間においても同様の手順により第１～第３受信側データ信号ＤＲａ～ＤＴａのビットデータが決定されることにより、受信側位相制御処理前の第１～第３受信側データ信号ＤＲａ～ＤＲｃが生成される。図９に示すように、第１～第３受信側データ信号ＤＲａ～ＤＲｃはそれぞれ、「１１１０１１０１」、「０１１００１０１」、および「１０１１１００１」を示している。すなわち、第１～第３受信側データ信号ＤＲａ～ＤＲｃはそれぞれ第１～第３送信側データ信号ＤＴａ～ＤＴｃと同じビットデータを示している。なお、上述のようにＮＵＬＬデータは考慮されない。このようにして生成された受信側位相制御処理前の第１～第３受信側データ信号ＤＲａ～ＤＲｃは、受信側遅延回路４１３に与えられる。 In the second system period TA2 to the seventh system period TA7 and each subsequent system period, the bit data of the first to third reception side data signals DRa to DTa is determined by the same procedure, so that the reception side phase control is performed. First to third receiving side data signals DRa to DRc before processing are generated. As shown in FIG. 9, the first to third receiving side data signals DRa to DRc indicate “11101101”, “01100101”, and “10111001”, respectively. That is, the first to third reception side data signals DRa to DRc indicate the same bit data as the first to third transmission side data signals DTa to DTc, respectively. Note that NULL data is not considered as described above. The first to third reception-side data signals DRa to DRc before the reception-side phase control processing generated in this way are given to the reception-side delay circuit 413.
　図１０は、受信側位相制御処理前の第１～第３受信側データ信号ＤＲａ～ＤＲｃを示す信号波形図である。図１０に示すように、各受信側データ信号のビットデータは、３サンプリング期間（３ＴＢ）毎に、サンプリングクロックＳＡＭの電圧レベルが立ち上がるタイミングで変化する。なお、本実施形態では各受信側データ信号にはＮＵＬＬデータが含まれないものとしているが、本発明はこれに限定されるものではなく、例えば各送信側データ信号と同様にＮＵＬＬデータが挿入されていても良い。 FIG. 10 is a signal waveform diagram showing the first to third reception side data signals DRa to DRc before the reception side phase control processing. As shown in FIG. 10, the bit data of each reception side data signal changes at the timing when the voltage level of the sampling clock SAM rises every three sampling periods (3TB). In this embodiment, it is assumed that NULL data is not included in each reception side data signal. However, the present invention is not limited to this, and for example, NULL data is inserted in the same manner as each transmission side data signal. May be.
　図１１は、受信側遅延回路４１３の動作を説明するための信号波形図である。図１１に示すように、受信側遅延回路４１３は、第１～第３受信側データ信号ＤＲａ～ＤＲｃに対してサンプリングクロックＳＡＭのタイミングに基づいた受信側位相制御処理を施す。具体的には、第３受信側データ信号ＤＲｃに対して、第２受信側データ信号ＤＲｂおよび第１受信側データ信号ＤＲａがそれぞれ１サンプリング期間および２サンプリング期間遅延する処理を施す。これにより、第１～第３受信側データ信号ＤＲａ～ＤＲｃの位相が互いに同一になる。このような受信側位相制御処理後の第１～第３受信側データ信号ＤＲａ～ＤＲｃは、受信側出力バッファ４１４を介して出力される。 FIG. 11 is a signal waveform diagram for explaining the operation of the reception side delay circuit 413. As shown in FIG. 11, the reception-side delay circuit 413 performs reception-side phase control processing based on the timing of the sampling clock SAM on the first to third reception-side data signals DRa to DRc. Specifically, the second receiving side data signal DRb and the first receiving side data signal DRa are subjected to processing for delaying the first receiving side data signal DRc and the first receiving side data signal DRa by 1 sampling period and 2 sampling periods, respectively. As a result, the phases of the first to third receiving data signals DRa to DRc are the same. The first to third reception side data signals DRa to DRc after such reception side phase control processing are output via the reception side output buffer 414.
　以上のようにして、本実施形態に係る信号伝送システムの動作が実現される。 As described above, the operation of the signal transmission system according to the present embodiment is realized.
　ところで、ビットデータ“１”および“０”について、上述のように第１～第３送受信データＴＲ１～ＴＲ３は互いに異なる電圧レベルになっている。このため、各システム期間における第１～第３サンプリング期間のそれぞれにおいて、伝送信号逆変換回路４１２でサンプリングすべき伝送信号ＴＳ（詳細には受信側判別信号ＲＲ）の電圧レベルは２種類となる。すなわち、第１サンプリング期間においてサンプリングすべき伝送信号ＴＳ（第１送受信データＴＲ１）の電圧レベルはＶＨａレベルおよびＶＨｂレベルの２種類であり、第２サンプリング期間においてサンプリングすべき伝送信号ＴＳ（第２送受信データＴＲ２）の電圧レベルはＶＨｂレベルおよびＶＨｃレベルの２種類であり、第３サンプリング期間においてサンプリングすべき伝送信号ＴＳ（第３送受信データＴＲ３）の電圧レベルはＶＨｃレベルおよびＧＮＤレベルの２種類である。 Incidentally, for the bit data “1” and “0”, the first to third transmission / reception data TR1 to TR3 are at different voltage levels as described above. Therefore, in each of the first to third sampling periods in each system period, there are two types of voltage levels of the transmission signal TS (specifically, the reception side determination signal RR) to be sampled by the transmission signal inverse conversion circuit 412. That is, there are two types of voltage levels of the transmission signal TS (first transmission / reception data TR1) to be sampled in the first sampling period, the VHa level and the VHb level, and the transmission signal TS (second transmission / reception data) to be sampled in the second sampling period. The voltage level of the data TR2) is two types of VHb level and VHc level, and the voltage level of the transmission signal TS (third transmission / reception data TR3) to be sampled in the third sampling period is two types of VHc level and GND level. .
　このような設定において、例えば、第１送受信データＴＲ１の電圧レベルがＶＨｃレベルまたはＧＮＤレベルであるときには伝送欠陥が生じていると考えられる。この場合、ＶＨｃレベルまたはＧＮＤレベルを、第１送受信データＴＲ１に対応するＶＨａレベルおよびＶＨｂレベルのうち、ＶＨｃレベルまたはＧＮＤレベルに近いＶＨｂレベルに訂正することができる。また、第２送受信データＴＲ２の電圧レベルがＶＨａレベルまたはＧＮＤレベルであるときにも伝送欠陥が生じていると考えられる。この場合、第２送受信データＴＲ２に対応するＶＨｂレベルに近いＶＨａレベルはＶＨｂレベルに訂正し、第２送受信データＴＲ２に対応するＶＨｃレベルに近いＧＮＤレベルに訂正することができる。また、第３送受信データＴＲ３の電圧レベルがＶＨａレベルまたはＶＨｂレベルであるときにも伝送欠陥が生じていると考えられる。この場合、ＶＨａレベルまたはＶＨｂレベルを、第３送受信データＴＲ３に対応するＶＨｃレベルおよびＧＮＤレベルのうち、ＶＨａレベルまたはＶＨｂレベルに近いＶＨｃレベルに訂正することができる。 In such a setting, for example, when the voltage level of the first transmission / reception data TR1 is the VHc level or the GND level, it is considered that a transmission defect has occurred. In this case, the VHc level or the GND level can be corrected to a VHb level close to the VHc level or the GND level among the VHa level and the VHb level corresponding to the first transmission / reception data TR1. It is also considered that a transmission defect has occurred when the voltage level of the second transmission / reception data TR2 is the VHa level or the GND level. In this case, the VHa level close to the VHb level corresponding to the second transmission / reception data TR2 can be corrected to the VHb level and corrected to the GND level close to the VHc level corresponding to the second transmission / reception data TR2. It is also considered that a transmission defect has occurred when the voltage level of the third transmission / reception data TR3 is the VHa level or the VHb level. In this case, the VHa level or VHb level can be corrected to a VHc level close to the VHa level or the VHb level among the VHc level and the GND level corresponding to the third transmission / reception data TR3.
　また、各システム期間の切り替わり前後である第３サンプリング期間および第１サンプリング期間にそれぞれサンプリングすべき伝送信号ＴＳである第３送受信データＴＲ３および第１送受信データＴＲ１に着目すると、第１送受信データＴＲ１に対応するＶＨａレベルおよびＶＨｂレベルのいずれも、第３送受信データＴＲ３に対応する２つの電圧レベルのうちの大きい方であるＶＨｃよりも大きい。一方で、第１送受信データＴＲ１および第２送受信データＴＲ２に着目すると、第２送受信データＴＲ２に対応する電圧レベルは第１送受信データＴＲ１に対応する電圧レベルと同じであるか、または小さい。同様に、第２送受信データＴＲ２および第３送受信データＴＲ３に着目すると、第３送受信データＴＲ３に対応する電圧レベルは第２送受信データＴＲ２に対応する電圧レベルと同じであるか、または小さい。このように、第３サンプリング期間から第１サンプリング期間に移行するときにのみ、伝送信号ＴＳの電圧レベルが大きくなる。このため、同期ずれが生じたとしても、伝送信号ＴＳの電圧レベルが直前のサンプリング期間よりも大きくなったサンプリング期間を第１サンプリング期間であると判別できるので、同期ずれを解消できる。 Further, when attention is paid to the third transmission / reception data TR3 and the first transmission / reception data TR1 which are transmission signals TS to be sampled in the third sampling period and the first sampling period before and after the switching of each system period, the first transmission / reception data TR1 Both the corresponding VHa level and VHb level are larger than VHc, which is the larger of the two voltage levels corresponding to the third transmission / reception data TR3. On the other hand, focusing on the first transmission / reception data TR1 and the second transmission / reception data TR2, the voltage level corresponding to the second transmission / reception data TR2 is the same as or smaller than the voltage level corresponding to the first transmission / reception data TR1. Similarly, paying attention to the second transmission / reception data TR2 and the third transmission / reception data TR3, the voltage level corresponding to the third transmission / reception data TR3 is the same as or smaller than the voltage level corresponding to the second transmission / reception data TR2. Thus, the voltage level of the transmission signal TS increases only when the third sampling period shifts to the first sampling period. For this reason, even if a synchronization shift occurs, the sampling period in which the voltage level of the transmission signal TS is larger than the immediately preceding sampling period can be determined as the first sampling period, and thus the synchronization shift can be eliminated.
　＜１．３　効果＞
　本実施形態によれば、送信部３において、システムクロックＳＹＳおよびサンプリングクロックＳＡＭのタイミングに基づいて第１～第３送信側データ信号ＤＴａ～ＤＴｃを順にサンプリングすると共にこれらの電圧レベルを変化させることにより伝送信号ＴＳが生成され、当該送信部３から受信部４に１本の伝送路５を介して伝送される。そして、受信部４において、システムクロックＳＹＳおよびサンプリングクロックＳＡＭのタイミングに基づいて、伝送信号ＴＳの第１～第３送受信データＴＲ１～ＴＲ３の電圧レベルにそれぞれ応じた第１～第３受信側データ信号ＤＲａ～ＤＲｃが生成される。また、システムクロックＳＹＳおよびサンプリングクロックＳＡＭによって同期をとるのみならず、第１～第３送受信データＴＲ１～ＴＲ３の電圧レベルを互いに異ならせているので、このような電圧レベルの相違に基づいて、例えば伝送欠陥を低減することができる。このため、複数のデータが１本の伝送路５を用いて確実に伝送される。これにより、回路規模の増大を抑制できるので、コストの増大を抑えつつ複数種類のデータを伝送できる。また、換言すると、伝送路１本あたりのデータ伝送量が増加されるので、従来よりも効率的にデータ伝送を行うことができる。なお、本実施形態では、ＬＶＤＳのような微小電圧を用いる必要がないので、一般的に高価なＬＶＤＳ用の回路が必要とされない。その結果、さらなる低コスト化を図ることができる。 <1.3 Effect>
According to the present embodiment, the transmission unit 3 sequentially samples the first to third transmission side data signals DTa to DTc based on the timings of the system clock SYS and the sampling clock SAM, and changes their voltage levels. A transmission signal TS is generated and transmitted from the transmission unit 3 to the reception unit 4 via one transmission path 5. Then, in the receiving unit 4, based on the timings of the system clock SYS and the sampling clock SAM, the first to third reception-side data signals corresponding to the voltage levels of the first to third transmission / reception data TR1 to TR3 of the transmission signal TS, respectively. DRa to DRc are generated. Further, not only synchronization is achieved by the system clock SYS and the sampling clock SAM, but the voltage levels of the first to third transmission / reception data TR1 to TR3 are different from each other. Transmission defects can be reduced. For this reason, a plurality of data are reliably transmitted using one transmission path 5. Thereby, since an increase in circuit scale can be suppressed, a plurality of types of data can be transmitted while suppressing an increase in cost. In other words, since the amount of data transmission per transmission line is increased, data transmission can be performed more efficiently than in the past. In this embodiment, since it is not necessary to use a minute voltage like LVDS, generally an expensive circuit for LVDS is not required. As a result, further cost reduction can be achieved.
　また、本実施形態によれば、第１送受信データＴＲ１の“０”に対応する電圧レベルおよび第２送受信データＴＲ２の“１”に対応する電圧レベルは、互いに同じＶＨｂレベルである。第２送受信データＴＲ２の“０”に対応する電圧レベルおよび第３送受信データＴＲ３の“１”に対応する電圧レベルは、互いに同じＶＨｃレベルである。そして、第１送受信データＴＲ１の“１”に対応する電圧レベルはＶＨａレベルであり、当該ＶＨａレベルは他と重複していない。同様に、第３送受信データＴＲ３の“０”に対応する電圧レベルはＧＮＤレベルであり、当該ＧＮＤレベルは他の重複していない。このように、本実施形態における伝送信号ＴＳを実現する電圧レベルの種類は、Ｎ＋１種類（４種類）になっている。このため、同期ずれが生じたとしても、伝送信号ＴＳの電圧レベルが直前のサンプリング期間よりも大きくなったサンプリング期間を第１サンプリング期間であると判別できるので、同期ずれを解消できる。これにより、より確実に複数種類のデータ伝送を伝送することができる。 Further, according to the present embodiment, the voltage level corresponding to “0” of the first transmission / reception data TR1 and the voltage level corresponding to “1” of the second transmission / reception data TR2 are the same VHb level. The voltage level corresponding to “0” of the second transmission / reception data TR2 and the voltage level corresponding to “1” of the third transmission / reception data TR3 are the same VHc level. The voltage level corresponding to “1” of the first transmission / reception data TR1 is the VHa level, and the VHa level does not overlap with the others. Similarly, the voltage level corresponding to “0” of the third transmission / reception data TR3 is the GND level, and the GND level is not duplicated. Thus, there are N + 1 types (four types) of voltage levels for realizing the transmission signal TS in the present embodiment. For this reason, even if a synchronization shift occurs, the sampling period in which the voltage level of the transmission signal TS is larger than the immediately preceding sampling period can be determined as the first sampling period, and thus the synchronization shift can be eliminated. Thereby, a plurality of types of data transmission can be transmitted more reliably.
　また、本実施形態によれば、第１～第３送信側データ信号ＤＴａ～ＤＴｃから伝送信号ＴＳを生成するための電圧レベル、および伝送信号ＴＳから第１～第３受信側データ信号ＤＲａ～ＤＲｃを生成するための電圧レベルをそれぞれ送信側レベルシフタ３０および受信側レベルシフタ４０を用いて生成することができる。特に、互いに異なる複数の電圧レベルが必要な送信側では、送信側レベルシフタ３０を用いることにより、ホスト１から複数の電圧レベルを供給せずとも（すなわち、第１～第３送信側制御信号ＣＴａ～ＣＴｃの電圧レベルが互いに同一でも）、互いに異なる複数の電圧レベルを生成することができる。 Further, according to the present embodiment, the voltage level for generating the transmission signal TS from the first to third transmission side data signals DTa to DTc, and the first to third reception side data signals DRa to DRc from the transmission signal TS. Can be generated using the transmission-side level shifter 30 and the reception-side level shifter 40, respectively. In particular, on the transmission side that requires a plurality of different voltage levels, the transmission side level shifter 30 is used, so that a plurality of voltage levels are not supplied from the host 1 (that is, the first to third transmission side control signals CTa˜). Even if the voltage levels of CTc are the same, a plurality of different voltage levels can be generated.
　ところで、本実施形態では、伝送信号ＴＳにおいて、第１送信側データ信号ＤＴａのビットデータの“１”および“０”をそれぞれＶＨａレベルおよびＶＨｂレベルに対応させ、第２送信側データ信号ＤＴｂのビットデータの“１”および“０”をそれぞれＶＨｂレベルおよびＶＨｃレベルに対応させ、第３送信側データ信号ＤＴｃのビットデータの“１”および“０”をそれぞれＶＨｃレベルおよびＧＮＤレベルに対応させている。すなわち、各送信側データ信号のビットデータの“１”および／または“０”に対応する電圧レベルと、他の送信側データ信号のビットデータの“０”および／または“１”に対応する電圧レベルとを重複させているが、本発明はこれに限定されるものではない。例えば、各送信側データ信号のビットデータの“１”および“０”に対応する電圧レベルの双方と、他の送信側データ信号のビットデータの“１”および“０”に対応する電圧レベルの双方とを互いに異ならせることにより、Ｎ×２種類（本実施形態では６種類）の電圧レベルからなる伝送信号ＴＳを生成するようにしても良い。この場合、必要となる電圧レベルの数が増えはするが、例えば同期ずれが生じた場合でも、受信側データ信号間のビットデータの混同を確実に防止されるので、より確実に複数種類のデータを伝送することができる。 By the way, in the present embodiment, in the transmission signal TS, the bit data “1” and “0” of the first transmission side data signal DTa correspond to the VHa level and VHb level, respectively, and the bit of the second transmission side data signal DTb Data “1” and “0” correspond to the VHb level and VHc level, respectively, and bit data “1” and “0” of the third transmission side data signal DTc correspond to the VHc level and GND level, respectively. . That is, the voltage level corresponding to “1” and / or “0” of the bit data of each transmission side data signal and the voltage corresponding to “0” and / or “1” of the bit data of the other transmission side data signal Although the level is overlapped, the present invention is not limited to this. For example, both of the voltage levels corresponding to “1” and “0” of the bit data of each transmission side data signal and the voltage levels corresponding to “1” and “0” of the bit data of other transmission side data signals By making the two different from each other, the transmission signal TS having N × 2 types (six types in the present embodiment) of voltage levels may be generated. In this case, although the number of required voltage levels increases, for example, even if a synchronization error occurs, it is possible to reliably prevent the bit data from being confused between the receiving side data signals, so that more types of data can be more reliably obtained. Can be transmitted.
　＜２．第２の実施形態＞
　＜２．１　全体構成＞
　本発明の第２の実施形態は、送信側レベルコントロールプロセッサ３１および受信側レベルコントロールプロセッサ４１を除き上記第１の実施形態と構成等が共通するので、当該共通部分についての説明を省略する。また、本実施形態の構成要素のうちの第１の実施形態と同一の要素については、同一の参照符号を付して適宜説明を省略する。 <2. Second Embodiment>
<2.1 Overall configuration>
Since the second embodiment of the present invention has the same configuration and the like as the first embodiment except for the transmission side level control processor 31 and the reception side level control processor 41, description of the common part is omitted. In addition, the same elements as those of the first embodiment among the components of the present embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
　＜２．１．１　送信側レベルコントロールプロセッサの構成＞
　図１２は、本実施形態における送信側レベルコントロールプロセッサ３１の構成を示すブロック図である。図１２に示すように、この送信側レベルコントロールプロセッサ３１は上記第１の実施形態におけるものと異なり、送信側遅延回路３１１、送信側データ判別回路３１２、および伝送信号変換回路３１３に代えて、変換プロセッサ（処理装置）３１５を備えている。 <2.1.1 Configuration of transmitting side level control processor>
FIG. 12 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment. As shown in FIG. 12, the transmission side level control processor 31 is different from that in the first embodiment in that a transmission side delay circuit 311, a transmission side data discrimination circuit 312 and a transmission signal conversion circuit 313 are converted. A processor (processing device) 315 is provided.
　変換プロセッサ３１５は、送信側遅延回路３１１、送信側データ判別回路３１２、および伝送信号変換回路３１３の機能を備えるものであり、上記第１の実施形態で示した送信側遅延回路３１１、送信側データ判別回路３１２、および伝送信号変換回路３１３の動作を実現する。すなわち、変換プロセッサ３１５は、送信側入力バッファ３１０を介して入力された第１～第３送信側データ信号ＤＴａ～ＤＴｃ、システムクロックＳＹＳ、サンプリングクロックＳＡＭ、および送信側レベルシフタ３０から出力された第１～第３送信側レベルシフト信号ＬＳＴａ～ＬＳＴｃを受け取り、これらに基づいて伝送信号ＴＳを生成し、送信側出力バッファ３１４に出力する。なお、変換プロセッサ３１５の詳細な動作については、上記第１の実施形態における送信側遅延回路３１１、送信側データ判別回路３１２、および伝送信号変換回路３１３の動作と同様であるので、その説明を省略する。 The conversion processor 315 includes the functions of the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313, and includes the transmission side delay circuit 311 and the transmission side data described in the first embodiment. The operations of the determination circuit 312 and the transmission signal conversion circuit 313 are realized. That is, the conversion processor 315 receives the first to third transmission data signals DTa to DTc, the system clock SYS, the sampling clock SAM, and the first output from the transmission level shifter 30 that are input via the transmission input buffer 310. The third transmission side level shift signals LSTa to LSTc are received, the transmission signal TS is generated based on these, and output to the transmission side output buffer 314. The detailed operation of the conversion processor 315 is the same as the operation of the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313 in the first embodiment, and a description thereof will be omitted. To do.
　＜２．１．２　受信側レベルコントロールプロセッサの構成＞
　図１３は、本実施形態における受信側レベルコントロールプロセッサ４１の構成を示すブロック図である。図１３に示すように、この受信側レベルコントロールプロセッサ４１は上記第１の実施形態におけるものと異なり、受信側データ判別回路４１１、伝送信号逆変換回路４１２、および受信側遅延回路４１３に代えて、逆変換プロセッサ（処理装置）４１５を備えている。 <2.1.2 Configuration of receiving side level control processor>
FIG. 13 is a block diagram showing a configuration of the receiving side level control processor 41 in the present embodiment. As shown in FIG. 13, the receiving side level control processor 41 is different from that in the first embodiment in place of the receiving side data discriminating circuit 411, the transmission signal inverse converting circuit 412, and the receiving side delay circuit 413. An inverse conversion processor (processing device) 415 is provided.
　逆変換プロセッサ４１５は、受信側データ判別回路４１１、伝送信号逆変換回路４１２、および受信側遅延回路４１３の機能を備えるものであり、上記第１の実施形態で示した受信側データ判別回路４１１、伝送信号逆変換回路４１２、および受信側遅延回路４１３の動作を実現する。すなわち、逆変換プロセッサ４１５は、受信側入力バッファ４１０を介して入力された伝送信号ＴＳ、システムクロックＳＹＳ、サンプリングクロックＳＡＭ、および受信側レベルシフタ４０から出力された受信側レベルシフト信号ＬＳＲを受け取り、これらに基づいて第１～第３受信側データ信号ＤＲａ～ＤＲｃを生成し、受信側出力バッファ４１４に出力する。なお、逆変換プロセッサ４１５の詳細な動作については、上記第１の実施形態における受信側データ判別回路４１１、伝送信号逆変換回路４１２、および受信側遅延回路４１３の動作と同様であるので、その説明を省略する。 The inverse conversion processor 415 includes functions of a reception side data determination circuit 411, a transmission signal reverse conversion circuit 412, and a reception side delay circuit 413. The reception side data determination circuit 411 described in the first embodiment, The operations of the transmission signal inverse conversion circuit 412 and the reception side delay circuit 413 are realized. That is, the inverse conversion processor 415 receives the transmission signal TS, the system clock SYS, the sampling clock SAM, and the reception-side level shift signal LSR output from the reception-side level shifter 40, which are input via the reception-side input buffer 410. Based on the first to third receiving side data signals DRa to DRc, and outputs them to the receiving side output buffer 414. The detailed operation of the inverse conversion processor 415 is the same as the operation of the reception side data determination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side delay circuit 413 in the first embodiment. Is omitted.
　＜２．２　効果＞
　本実施形態によれば、送信側遅延回路３１１、送信側データ判別回路３１２、および伝送信号変換回路３１３が変換プロセッサ３１５により、受信側データ判別回路４１１、伝送信号逆変換回路４１２、および受信側遅延回路４１３が逆変換プロセッサ４１５によりそれぞれ１つの構成要素として実現される。このため、送信側遅延回路３１１、送信側データ判別回路３１２、および伝送信号変換回路３１３で互いに共通する構成要素を共有化し、また、受信側データ判別回路４１１、伝送信号逆変換回路４１２、および受信側遅延回路４１３で互いに共通する構成要素を共有化することにより、送信部３および受信部４の回路規模を削減することができる。 <2.2 Effect>
According to the present embodiment, the transmission side delay circuit 311, the transmission side data determination circuit 312, and the transmission signal conversion circuit 313 are converted into the reception side data determination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side delay by the conversion processor 315. The circuits 413 are each realized as one component by the inverse conversion processor 415. For this reason, the transmission side delay circuit 311, the transmission side data discrimination circuit 312, and the transmission signal conversion circuit 313 share common components, and the reception side data discrimination circuit 411, the transmission signal inverse conversion circuit 412, and the reception side By sharing common components in the side delay circuit 413, the circuit scale of the transmission unit 3 and the reception unit 4 can be reduced.
　＜３．第３の実施形態＞
　＜３．１　全体構成＞
　本発明の第３の実施形態は、送信側レベルコントロールプロセッサ３１および受信側レベルコントロールプロセッサ４１を除き上記第１の実施形態と構成等が共通するので、当該共通部分についての説明を省略する。また、また、本実施形態の構成要素のうちの第１の実施形態と同一の要素については、同一の参照符号を付して適宜説明を省略する。 <3. Third Embodiment>
<3.1 Overall configuration>
Since the third embodiment of the present invention has the same configuration and the like as the first embodiment except for the transmission side level control processor 31 and the reception side level control processor 41, description of the common part is omitted. In addition, among the components of the present embodiment, the same elements as those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
　＜３．１．１　送信側レベルコントロールプロセッサの構成＞
　図１４は、本実施形態における送信側レベルコントロールプロセッサ３１の構成を示すブロック図である。図１４に示すように、この送信側レベルコントロールプロセッサ３１は上記第１の実施形態におけるものと異なり、送信側遅延回路３１１に代えて、３つのＦＩＦＯ（Ｆｉｒｓｔ　Ｉｎ　Ｆｉｒｓｔ　Ｏｕｔ）メモリ３１６ａ～３１６ｃおよび送信側読み出し制御回路３１７を備えている。以下では、３つのＦＩＦＯメモリ３１６ａ～３１６ｃをそれぞれ「第１～第３送信側ＦＩＦＯメモリ」という。 <3.1.1 Configuration of Transmission Level Control Processor>
FIG. 14 is a block diagram showing a configuration of the transmission side level control processor 31 in the present embodiment. As shown in FIG. 14, the transmission-side level control processor 31 is different from that in the first embodiment, and instead of the transmission-side delay circuit 311, three FIFO (First In First Out) memories 316 a to 316 c and transmission A side readout control circuit 317 is provided. Hereinafter, the three FIFO memories 316a to 316c are referred to as “first to third transmission side FIFO memories”, respectively.
　第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃは、先に書き込んだデータを先に読み出すバッファ動作をするメモリである。第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃは、送信側入力バッファ３００を介して入力された第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータをそれぞれ記憶する。なお、本実施形態において送信側入力バッファ３００を介して入力される第１～第３送信側データ信号ＤＴａ～ＤＴｃは、上記第１の実施形態のように２ビット毎にＮＵＬＬデータが挿入されたものでも良く、ＮＵＬＬデータが挿入されていないものでも良い。 The first to third transmission side FIFO memories 316a to 316c are memories that perform a buffer operation of reading data written first. The first to third transmission side FIFO memories 316a to 316c store bit data of the first to third transmission side data signals DTa to DTc input via the transmission side input buffer 300, respectively. In the present embodiment, the first to third transmission side data signals DTa to DTc input via the transmission side input buffer 300 have NULL data inserted every two bits as in the first embodiment. It may be a thing, and the thing in which NULL data is not inserted may be sufficient.
　送信側読み出し制御回路３１７は、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃにそれぞれ書き込まれた第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータの読み出しタイミングを制御する。具体的には、送信側読み出し制御回路３１７は、読み出し元になるべき送信側ＦＩＦＯメモリを示す、外部（例えばホスト１）から与えられる送信側読み出し制御信号ＲＣＴおよびサンプリングクロックＳＡＭに基づいて、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃから１サンプリング期間毎に順にビットデータを読み出す。読み出された第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータは送信側データ判別回路３１２に与えられる。このため、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃから１サンプリング期間毎に順に第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータが読み出されることにより、実質的に上記第１の実施形態と同様の送信側位相制御処理が施された第１～第３送信側データ信号ＤＴａ～ＤＴｃが送信側データ判別回路３０２に与えられることになる。このように本実施形態では、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃおよび送信側読み出し制御回路３１７により送信側位相制御部が実現されている。 The transmission side read control circuit 317 controls the read timing of the bit data of the first to third transmission side data signals DTa to DTc written in the first to third transmission side FIFO memories 316a to 316c, respectively. Specifically, the transmission side read control circuit 317 indicates the first side based on the transmission side read control signal RCT and the sampling clock SAM given from the outside (for example, the host 1) indicating the transmission side FIFO memory to be the read source. Read bit data sequentially from the third transmission side FIFO memories 316a to 316c every sampling period. The read bit data of the first to third transmission side data signals DTa to DTc are supplied to the transmission side data discrimination circuit 312. Therefore, the bit data of the first to third transmission side data signals DTa to DTc are read from the first to third transmission side FIFO memories 316a to 316c in order every sampling period, so that the first The first to third transmission side data signals DTa to DTc subjected to the transmission side phase control process similar to the embodiment are given to the transmission side data discrimination circuit 302. As described above, in this embodiment, the transmission-side phase control unit is realized by the first to third transmission-side FIFO memories 316 a to 316 c and the transmission-side read control circuit 317.
　ここで、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃへのビットデータの書き込みは連続して行われる一方で、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃからのビットデータの読み出しは３回に１回の頻度で順番に行われる。このため、各送信側ＦＩＦＯメモリからのビットデータの読み出し速度は、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃへのビットデータの書き込み速度の３倍であることが望ましい。これにより、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃへのビットデータの書き込み速度と第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃからのビットデータの読み出し速度を実質的に等しくすることができる。なお、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃへのビットデータの書き込み速度と各送信側ＦＩＦＯメモリからのビットデータの読み出し速度とを互いに等しくしても良いが、この場合、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃにビットデータを記憶するための空きがなくなるおそれがある。この場合は、本信号伝送システムに図示しない手段によりデータ退避用のメモリを設け、当該メモリに、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃにそれぞれ格納すべき第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータを一時的に格納するようにすることが望ましい。これにより、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃにビットデータを記憶するための空きがなくなることを防止できる。 Here, the writing of bit data to the first to third transmission side FIFO memories 316a to 316c is continuously performed, while the reading of bit data from the first to third transmission side FIFO memories 316a to 316c is 3 It is performed in turn at a frequency of once. For this reason, it is desirable that the reading speed of the bit data from each transmission side FIFO memory is three times the writing speed of the bit data to the first to third transmission side FIFO memories 316a to 316c. Thereby, the writing speed of the bit data to the first to third transmitting side FIFO memories 316a to 316c and the reading speed of the bit data from the first to third transmitting side FIFO memories 316a to 316c can be made substantially equal. it can. The bit data writing speed to the first to third transmission side FIFO memories 316a to 316c and the bit data reading speed from each transmission side FIFO memory may be equal to each other. There is a possibility that the third transmission side FIFO memories 316a to 316c may run out of space for storing bit data. In this case, a memory for saving data is provided in the signal transmission system by means (not shown), and the first to third transmission side data to be stored in the first to third transmission side FIFO memories 316a to 316c, respectively. It is desirable to temporarily store bit data of signals DTa to DTc. As a result, it is possible to prevent the first to third transmission side FIFO memories 316a to 316c from becoming free for storing bit data.
　なお、本実施形態における送信側レベルコントロールプロセッサ３１の第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃおよび送信側読み出し制御回路３１７以外の構成要素については上記第１の実施形態におけるものと同様であるので、その説明を省略する。 The components other than the first to third transmission side FIFO memories 316a to 316c and the transmission side read control circuit 317 of the transmission side level control processor 31 in the present embodiment are the same as those in the first embodiment. Therefore, the description is omitted.
　＜３．１．２　受信側レベルコントロールプロセッサの構成＞
　図１５は、本実施形態における受信側レベルコントロールプロセッサ４１の構成を示すブロック図である。図１５に示すように、この受信側レベルコントロールプロセッサ４１は上記第１の実施形態におけるものと異なり、受信側遅延回路４１３に代えて、３つのＦＩＦＯメモリ４１６ａ～４１６ｃおよび受信側読み出し制御回路４１７を備えている。以下では、３つのＦＩＦＯメモリ４１６ａ～４１６ｃをそれぞれ「第１～第３受信側ＦＩＦＯメモリ」という。 <3.1.2 Configuration of Receiver Level Control Processor>
FIG. 15 is a block diagram showing the configuration of the receiving side level control processor 41 in the present embodiment. As shown in FIG. 15, the receiving side level control processor 41 differs from that in the first embodiment in that it has three FIFO memories 416a to 416c and a receiving side read control circuit 417 instead of the receiving side delay circuit 413. I have. Hereinafter, the three FIFO memories 416a to 416c are referred to as “first to third reception side FIFO memories”, respectively.
　第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃは、上記第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃと同様のバッファ動作をするメモリである。第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃは、伝送信号逆変換回路４１２から出力された第１～第３受信側データ信号ＤＲａ～ＤＲｃのビットデータをそれぞれ記憶する。 The first to third reception side FIFO memories 416a to 416c are memories that perform the same buffer operation as the first to third transmission side FIFO memories 316a to 316c. The first to third reception side FIFO memories 416a to 416c store bit data of the first to third reception side data signals DRa to DRc output from the transmission signal inverse conversion circuit 412, respectively.
　受信側読み出し制御回路４１７は、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃにそれぞれ書き込まれた第１～第３受信側データ信号ＤＲａ～ＤＲｃのビットデータの読み出しタイミングを制御する。具体的には、受信側読み出し制御回路４１７は、外部（例えばホスト１）から与えられる受信側読み出し制御信号ＲＣＲ（システムクロックＳＹＳでも良い）に基づいて、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃから第１～第３受信側データ信号ＤＲａ～ＤＲｃのビットデータを互いに同じタイミングで読み出す。読み出された第１～第３受信側データ信号ＤＲａ～ＤＲｃは受信側出力バッファ４１４に与えられる。このため、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃから第１～第３受信側データ信号ＤＲａ～ＤＲｃのビットデータを互いに同じタイミングで読み出されることにより、実質的に上記第１の実施形態と同様の受信側位相制御処理が施された第１～第３受信側データ信号ＤＲａ～ＤＲｃが受信側出力バッファ４１４に与えられることになる。このように本実施形態では、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃおよび受信側読み出し制御回路４１７により受信側位相制御部が実現されている。 The reception side read control circuit 417 controls the read timing of the bit data of the first to third reception side data signals DRa to DRc written in the first to third reception side FIFO memories 416a to 416c, respectively. Specifically, the reception-side read control circuit 417 is configured to receive first to third reception-side FIFO memories 416a to 416a based on a reception-side read control signal RCR (which may be the system clock SYS) given from the outside (for example, the host 1). The bit data of the first to third receiving side data signals DRa to DRc are read from 416c at the same timing. The read first to third reception side data signals DRa to DRc are applied to the reception side output buffer 414. For this reason, the bit data of the first to third reception side data signals DRa to DRc are read from the first to third reception side FIFO memories 416a to 416c at the same timing, so that substantially the first embodiment described above. The first to third reception side data signals DRa to DRc that have been subjected to the same reception side phase control processing as described above are applied to the reception side output buffer 414. As described above, in this embodiment, the reception-side phase control unit is realized by the first to third reception-side FIFO memories 416a to 416c and the reception-side read control circuit 417.
　ここで、受信側では、送信側と同様に、各受信側ＦＩＦＯメモリからのビットデータの読み出し速度は、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃへのビットデータの書き込み速度の３倍であることが望ましい。なお、送信側と同様のデータ退避用のメモリを設けて、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃへのビットデータの書き込み速度と受信側ＦＩＦＯメモリからのビットデータの読み出し速度とを互いに等しくしても良い。 Here, on the receiving side, similarly to the transmitting side, the reading speed of bit data from each receiving side FIFO memory is three times the writing speed of bit data to the first to third receiving side FIFO memories 416a to 416c. It is desirable to be. It is to be noted that a data saving memory similar to that on the transmission side is provided, and the writing speed of bit data to the first to third receiving side FIFO memories 416a to 416c and the reading speed of bit data from the receiving side FIFO memory are mutually set. It may be equal.
　＜３．２　動作＞
　以上に示した構成により実現される本実施形態に係る信号伝送システムの動作について、送信側と受信側とに分けて説明する。なお、上記第１の実施形態と共通する部分については上述のように適宜説明を省略する。 <3.2 Operation>
The operation of the signal transmission system according to the present embodiment realized by the configuration described above will be described separately for the transmission side and the reception side. Note that description of parts common to the first embodiment is appropriately omitted as described above.
　＜３．２．１　送信側の動作＞
　図１６は、本実施形態における送信側読み出し制御回路３０７の動作について説明するための信号波形図である。図１６において、送信側読み出し制御信号ＲＣＴで符号Ａ～Ｃが付された１サンプリング期間では、サンプリングクロックＳＡＭの電圧レベルが立ち上がるタイミングで第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃからそれぞれ第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータが読み出される。送信側読み出し制御信号ＲＣＴによって、読み出し元になる送信側ＦＩＦＯメモリは、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃの順に１サンプリング期間毎に切り替わる。このため、上記第１の実施形態の送信側位相制御処理と同様に、第１送信側データ信号ＤＴａに対して、第２送信側データ信号ＤＴｂおよび第３送信側データ信号ＤＴｃがそれぞれ１サンプリング期間および２サンプリング期間遅延することになる。 <3.2.1 Operation on transmitting side>
FIG. 16 is a signal waveform diagram for explaining the operation of the transmission side read control circuit 307 in the present embodiment. In FIG. 16, in one sampling period indicated by reference signs A to C in the transmission side read control signal RCT, the first to third transmission side FIFO memories 316a to 316c are first to each at the timing when the voltage level of the sampling clock SAM rises. The bit data of the third transmission side data signals DTa to DTc are read. In accordance with the transmission-side read control signal RCT, the transmission-side FIFO memory serving as a reading source is switched every sampling period in the order of the first to third transmission-side FIFO memories 316a to 316c. For this reason, similarly to the transmission-side phase control processing of the first embodiment, the second transmission-side data signal DTb and the third transmission-side data signal DTc are each one sampling period with respect to the first transmission-side data signal DTa. And a delay of 2 sampling periods.
　本実施形態では、図１６に示すように、各サンプリング期間ＴＢにおいて第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータのうちのいずれか１つのみが読み出され、残りの２つは読み出されない（ＮＵＬＬデータとなる）ようになっている。このため、送信側読み出し制御回路３０７と送信側データ判別回路３０２との間の伝送は実質的に１本の伝送路により実現することができるので、回路規模を削減することができる。ただし、本発明はこれに限定されるものではなく、第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータが互いに１サンプリング期間毎にずれると共に平行して読み出される（すなわち、ＮＵＬＬデータがない）ようにしても良い。以上のようにして読み出された第１～第３送信側データ信号ＤＴａ～ＤＴｃのビットデータは送信側データ判別回路３０３に与えられる。なお、送信側データ判別回路３０３の動作は上記第１の実施形態におけるものと同様であるので、その説明を省略する。 In this embodiment, as shown in FIG. 16, only one of the bit data of the first to third transmitting side data signals DTa to DTc is read in each sampling period TB, and the remaining two are It is not read (becomes NULL data). For this reason, transmission between the transmission-side read control circuit 307 and the transmission-side data discrimination circuit 302 can be realized substantially by a single transmission line, so that the circuit scale can be reduced. However, the present invention is not limited to this, and the bit data of the first to third transmission side data signals DTa to DTc are shifted from each other every sampling period and read in parallel (that is, there is no NULL data). You may do it. The bit data of the first to third transmission side data signals DTa to DTc read out as described above are given to the transmission side data discrimination circuit 303. Since the operation of the transmission side data discrimination circuit 303 is the same as that in the first embodiment, description thereof is omitted.
　図１７は、本実施形態における伝送信号変換回路３１３の動作を説明するための信号波形図である。本実施形態においても上記第１の実施形態と同様に、伝送信号変換回路３１３によって、８ビット分の第１～第３送信側データ信号ＤＴａ～ＤＴｃ（すなわち、合計２４ビット分のデータ）に基づいて伝送信号ＴＳが生成される。なお、伝送信号変換回路３１３の動作の詳細は上記第１の実施形態において述べた通りなので、その説明を省略する。 FIG. 17 is a signal waveform diagram for explaining the operation of the transmission signal conversion circuit 313 in this embodiment. Also in this embodiment, as in the first embodiment, the transmission signal conversion circuit 313 uses the first to third transmission side data signals DTa to DTc for 8 bits (that is, data for a total of 24 bits). Thus, a transmission signal TS is generated. Note that details of the operation of the transmission signal conversion circuit 313 are as described in the first embodiment, and a description thereof will be omitted.
　＜３．２．２　受信側の動作＞
　図１８は、本実施形態における伝送信号逆変換回路４１２の動作を説明するための信号波形図である。本実施形態においても上記第１の実施形態に、伝送信号逆変換回路４１２によって、伝送信号ＴＳに基づいて受信側位相制御処理前の８ビット分の第１～第３受信側データ信号ＤＲａ～ＤＲｃ（すなわち、合計２４ビット分のデータ）が生成される。なお、伝送信号逆変換回路４１２の動作の詳細は上記第１の実施形態において述べた通りなので、その説明を省略する。 <3.2.2 Receiving side operation>
FIG. 18 is a signal waveform diagram for explaining the operation of the transmission signal inverse conversion circuit 412 in this embodiment. Also in this embodiment, the first to third reception side data signals DRa to DRc for 8 bits before the reception side phase control processing are performed based on the transmission signal TS by the transmission signal inverse conversion circuit 412 in the first embodiment. (That is, a total of 24 bits of data) is generated. The details of the operation of the transmission signal inverse conversion circuit 412 are as described in the first embodiment, and the description thereof is omitted.
　伝送信号逆変換回路４１２によって生成された第１～第３受信側データ信号ＤＲａ～ＤＲｃはそれぞれ、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃに順次記憶される。 The first to third reception side data signals DRa to DRc generated by the transmission signal inverse conversion circuit 412 are sequentially stored in the first to third reception side FIFO memories 416a to 416c, respectively.
　図１９は、本実施形態における受信側読み出し制御回路４１７の動作について説明するための信号波形図である。図１９に示すように、受信側読み出し制御回路４１７は、受信側読み出し制御信号ＲＣＲ（システムクロックＳＹＳでも良い）の電圧レベルが立ち上がるタイミングで、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃから第１～第３受信側データ信号ＤＲａ～ＤＲｃのビットデータを同時に読み出す。このため、上記第１の実施形態の受信側位相制御処理と同様に、第１～第３受信側データ信号ＤＲａ～ＤＲｃの位相が互いに同一になる。このような受信側位相制御処理後の第１～第３受信側データ信号ＤＲａ～ＤＲｃは、受信側出力バッファ４１４を介して出力される。 FIG. 19 is a signal waveform diagram for explaining the operation of the receiving side read control circuit 417 in the present embodiment. As shown in FIG. 19, the reception-side read control circuit 417 starts from the first to third reception-side FIFO memories 416a to 416c at the timing when the voltage level of the reception-side read control signal RCR (which may be the system clock SYS) rises. The bit data of the first to third receiving side data signals DRa to DRc are read simultaneously. For this reason, as in the reception-side phase control process of the first embodiment, the phases of the first to third reception-side data signals DRa to DRc are the same. The first to third reception-side data signals DRa to DRc after such reception-side phase control processing are output via the reception-side output buffer 414.
　以上のようにして、本実施形態に係る信号伝送システムの動作が実現される。 As described above, the operation of the signal transmission system according to the present embodiment is realized.
　＜３．３　効果＞
　本実施形態によれば、第１～第３送信側ＦＩＦＯメモリ３１６ａ～３１６ｃおよび送信側読み出し制御回路３１７により送信側位相制御部を実現し、第１～第３受信側ＦＩＦＯメモリ４１６ａ～４１６ｃおよび受信側読み出し制御回路４１７により受信側位相制御部を実現することにより、上記第１の実施形態と同様の効果を奏することができる。 <3.3 Effects>
According to this embodiment, the first to third transmission side FIFO memories 316a to 316c and the transmission side read control circuit 317 realize the transmission side phase control unit, and the first to third reception side FIFO memories 416a to 416c and the reception side. By realizing the reception-side phase control unit by the side readout control circuit 417, the same effects as in the first embodiment can be obtained.
　＜４．その他＞
　上記第１の実施形態では各送信側データ信号のビットデータを２サンプリング期間単位にし、２ビット毎に２サンプリング期間単位のＮＵＬＬデータを挿入しているが、本発明はこれに限定されるものではない。例えば、各送信側データ信号のビットデータを３サンプリング期間単位にし、ＮＵＬＬデータを挿入しないようにしても良い。この場合、第１～第３送信側データ信号ＤＴａ～ＤＴｃに送信側位相制御処理を施す必要はないので、送信側遅延回路３１１は設けられない。また、各送信側データ信号のビットデータを１サンプリング期間単位とし、ビットデータ間に２サンプリング期間単位のＮＵＬＬデータを挿入しても良い。 <4. Other>
In the first embodiment, the bit data of each transmission side data signal is set to two sampling periods, and NULL data of two sampling periods is inserted every two bits. However, the present invention is not limited to this. Absent. For example, the bit data of each transmission side data signal may be in units of 3 sampling periods, and NULL data may not be inserted. In this case, it is not necessary to perform transmission-side phase control processing on the first to third transmission-side data signals DTa to DTc, so that the transmission-side delay circuit 311 is not provided. Further, the bit data of each transmission side data signal may be set as one sampling period unit, and NULL data of two sampling periods may be inserted between the bit data.
　上記各実施形態において、３つのデータを伝送する例を挙げて説明したが、本発明はこれに限定されるものではない。２つのデータを伝送する場合、または４つ以上のデータを伝送する場合にも本発明を適用することができる。この場合、サンプリングクロックＳＡＭの周波数は、システムクロックＳＹＳの周波数をデータ数分だけ逓倍した値になる。 In each of the above embodiments, an example of transmitting three data has been described, but the present invention is not limited to this. The present invention can also be applied to the case of transmitting two data, or the case of transmitting four or more data. In this case, the frequency of the sampling clock SAM is a value obtained by multiplying the frequency of the system clock SYS by the number of data.
　上記各実施形態において、伝送信号変換回路３１３および伝送信号逆変換回路４１２のそれぞれで、接地レベルであるＧＮＤレベルを用いていたが、これに代えて他の電圧レベルを用いても良い。 In each of the above embodiments, the transmission signal conversion circuit 313 and the transmission signal inverse conversion circuit 412 each use the GND level that is the ground level, but other voltage levels may be used instead.
　その他、本発明の趣旨を逸脱しない範囲で上記各実施形態を種々変形して実施することができる。 In addition, the above embodiments can be variously modified and implemented without departing from the spirit of the present invention.
　以上により、本発明によれば、コストの増大を抑えつつ複数のデータの伝送を可能とする信号伝送装置および信号伝送方法を提供することができる。 As described above, according to the present invention, it is possible to provide a signal transmission device and a signal transmission method capable of transmitting a plurality of data while suppressing an increase in cost.
　本発明は、複数種類のデータ伝送を行う信号伝送装置および信号伝送方法に適用することができる。 The present invention can be applied to a signal transmission apparatus and a signal transmission method for performing a plurality of types of data transmission.
１…ホスト
２…信号伝送装置
３…送信部
４…受信部
５…伝送路
３０…送信側レベルシフタ（レベルシフト信号生成部）
３１…送信側レベルコントロールプロセッサ
４０…受信側レベルシフタ
４１…受信側レベルコントロールプロセッサ
３１０…送信側入力バッファ
３１１…送信側遅延回路（送信側位相制御部）
３１２…送信側データ判別回路
３１３…伝送信号変換回路（伝送信号変換部）
３１４…送信側出力バッファ（送信バッファ部）
３１５…変換プロセッサ
３１６ａ～３１６ｃ…第１～第３送信側ＦＩＦＯメモリ
３１７…送信側読み出し制御回路
４１０…受信側入力バッファ（受信バッファ部）
４１１…受信側データ判別回路
４１２…伝送信号逆変換回路（伝送信号逆変換部）
４１３…受信側遅延回路（受信側位相制御部）
４１４…受信側出力バッファ
４１５…逆変換プロセッサ
４１６ａ～４１６ｃ…第１～第３受信側ＦＩＦＯメモリ
ＤＴａ～ＤＴｃ…第１～第３送信側データ信号
ＤＲａ～ＤＲｃ…第１～第３受信側データ信号
ＳＹＳ…システムクロック（第１クロック信号）
ＳＡＭ…サンプリングクロック（第２クロック信号）
ＴＳ…伝送信号
ＬＳＴａ～ＬＳＴｃ…第１～第３送信側レベルシフト信号
ＬＳＲ…受信側レベルシフト信号 DESCRIPTION OF SYMBOLS 1 ... Host 2 ... Signal transmission apparatus 3 ... Transmission part 4 ... Reception part 5 ... Transmission path 30 ... Transmission side level shifter (level shift signal generation part)
31 ... Transmission side level control processor 40 ... Reception side level shifter 41 ... Reception side level control processor 310 ... Transmission side input buffer 311 ... Transmission side delay circuit (transmission side phase control unit)
312 ... Transmission side data discrimination circuit 313 ... Transmission signal conversion circuit (transmission signal conversion unit)
314: Transmission side output buffer (transmission buffer unit)
315: Conversion processors 316a to 316c ... First to third transmission side FIFO memories 317 ... Transmission side read control circuit 410 ... Reception side input buffer (reception buffer unit)
411... Reception side data discrimination circuit 412... Transmission signal reverse conversion circuit (transmission signal reverse conversion unit)
413 ... Reception side delay circuit (reception side phase control unit)
414 ... Reception side output buffer 415 ... Inverse conversion processors 416a to 416c ... First to third reception side FIFO memories DTa to DTc ... First to third transmission side data signals DRa to DRc ... First to third reception side data signals SYS: System clock (first clock signal)
SAM: Sampling clock (second clock signal)
TS ... Transmission signals LSTa to LSTc ... First to third transmission side level shift signal LSR ... Reception side level shift signal

Claims (10)

  1. 　送信部と受信部との間で１本の伝送路により複数種類のデータのシリアル伝送を行う信号伝送装置であって、
    　前記送信部は、
    　　周期的に変化する第１クロック信号、当該第１クロック信号の周波数をＮ（Ｎは２以上の整数）逓倍した第２クロック信号、および伝送すべきＮ個の送信側データ信号を外部から受け取るための送信側入力端子と、
    　　前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記Ｎ個の送信側データ信号を順にサンプリングすると共に、サンプリングした当該Ｎ個の送信側データ信号の電圧レベルを互いに異ならせることにより伝送信号を生成する送信側信号処理部と、
    　　前記伝送信号を前記伝送路に出力するための送信側出力端子とを含み、
    　前記受信部は、
    　　前記第１クロック信号、前記第２クロック信号、および前記伝送路から前記伝送信号を受け取るための受信側入力端子と、
    　　前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記伝送信号をサンプリングすると共に、サンプリングした当該伝送信号の電圧レベルを、電圧レベルが変化する前の前記Ｎ個の送信側データ信号に対応する電圧レベルに変化させることによりそれぞれＮ個の受信側データ信号を生成する受信側信号処理部と、
    　　前記Ｎ個の受信側データ信号を外部に出力するための受信側出力端子とを含むことを特徴とする、信号伝送装置。     A signal transmission device for serially transmitting a plurality of types of data through a single transmission path between a transmission unit and a reception unit,
    The transmitter is
    To receive a first clock signal that periodically changes, a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more), and N transmission-side data signals to be transmitted from the outside. The sending input terminal of
    The N transmission-side data signals are sequentially sampled in synchronization with the second clock signal every one cycle of the first clock signal, and the voltage levels of the sampled N transmission-side data signals are made different from each other. A transmission side signal processing unit for generating a transmission signal by
    A transmission side output terminal for outputting the transmission signal to the transmission line,
    The receiver is
    A receiving-side input terminal for receiving the first clock signal, the second clock signal, and the transmission signal from the transmission path;
    The transmission signal is sampled in synchronization with the second clock signal for each cycle of the first clock signal, and the voltage levels of the sampled transmission signal are set to the N transmission sides before the voltage level changes. A receiving-side signal processing unit that generates N receiving-side data signals by changing to a voltage level corresponding to the data signal;
    A signal transmission apparatus comprising: a reception-side output terminal for outputting the N reception-side data signals to the outside.
  2. 　前記送信側信号処理部は、前記第２クロック信号に同期して、前記Ｎ個の送信側データ信号の位相を前記第２クロック信号の１周期分の期間ずつ異ならせる送信側位相制御部を含むことを特徴とする、請求項１に記載の信号伝送装置。 The transmission-side signal processing unit includes a transmission-side phase control unit that varies the phases of the N transmission-side data signals by a period corresponding to one cycle of the second clock signal in synchronization with the second clock signal. The signal transmission device according to claim 1, wherein:
  3. 　前記送信側信号処理部は、前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記Ｎ個の送信側データ信号をそれぞれサンプリングすると共に、各送信データ信号の電圧レベルが送信側第１レベルまたは送信側第２レベルであるときには、当該送信データ信号の電圧レベルを、Ｎ＋１個の所定の電圧レベルのうちのいずれか２つの電圧レベルの一方または他方にそれぞれ変換することにより、Ｎ＋１種類の電圧レベルからなる前記伝送信号を生成する伝送信号変換部をさらに含むことを特徴とする、請求項２に記載の信号伝送装置。 The transmission-side signal processing unit samples the N transmission-side data signals in synchronization with the second clock signal every cycle of the first clock signal, and the voltage level of each transmission data signal is transmitted. By converting the voltage level of the transmission data signal to one or the other of any two voltage levels of the N + 1 predetermined voltage levels, respectively, when the transmission side first level or the transmission side second level is obtained, The signal transmission apparatus according to claim 2, further comprising a transmission signal conversion unit that generates the transmission signal having N + 1 types of voltage levels.
  4. 　前記伝送信号変換部はさらに、前記第１クロック信号の各周期においてサンプリングされるべき期間が連続する２つの前記送信側データ信号のうちの、先行の送信側データ信号の送信側第２レベルの変換後の電圧レベルと、後続の送信側データ信号の送信側第１レベルの変換後の電圧レベルとを互いに同じにすることを特徴とする、請求項３に記載の信号伝送装置。 The transmission signal converting unit further converts a transmission-side second level of a preceding transmission-side data signal out of two transmission-side data signals in which periods to be sampled in each cycle of the first clock signal are continuous. 4. The signal transmission device according to claim 3, wherein the subsequent voltage level and the voltage level after conversion of the first transmission level of the subsequent transmission data signal are made the same.
  5. 　前記送信側位相制御部および前記伝送信号変換部は、１つの処理装置として実現されていることを特徴とする、請求項３または４に記載の信号伝送装置。 The signal transmission device according to claim 3 or 4, wherein the transmission-side phase control unit and the transmission signal conversion unit are realized as one processing device.
  6. 　前記受信側信号処理部は、前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記伝送信号をサンプリングすると共に、サンプリングした当該伝送信号の電圧レベルのうちの、前記伝送信号変換部において前記送信側第１レベルから変換された電圧を、当該送信側第１レベルに対応する受信側第１レベルに変換し、前記送信側第２レベルから変換された電圧レベルを当該送信側第２レベルに対応する受信側第２レベルに変換することにより前記Ｎ個の受信側データ信号を生成する伝送信号逆変換部を含むことを特徴とする、請求項３から５までのいずれか１項に記載の信号伝送装置。 The reception-side signal processing unit samples the transmission signal in synchronization with the second clock signal for each cycle of the first clock signal, and the transmission signal of the sampled voltage level of the transmission signal. The voltage converted from the first level on the transmission side in the conversion unit is converted to the first level on the reception side corresponding to the first level on the transmission side, and the voltage level converted from the second level on the transmission side is converted to the transmission side. 6. The transmission signal inverse conversion unit for generating the N reception-side data signals by converting to a reception-side second level corresponding to the second level. The signal transmission device according to item.
  7. 　前記受信側信号処理部は、前記第２クロック信号に同期して、前記Ｎ個の受信側データ信号を互いに同位相にする受信側位相制御部をさらに含むことを特徴とする、請求項６に記載の信号伝送装置。 The reception side signal processing unit further includes a reception side phase control unit that synchronizes the N reception side data signals with each other in synchronization with the second clock signal. The signal transmission device described.
  8. 　前記伝送信号逆変換部および前記受信側位相制御部は、１つの処理装置として実現されていることを特徴とする、請求項７に記載の信号伝送装置。 The signal transmission device according to claim 7, wherein the transmission signal inverse conversion unit and the reception-side phase control unit are realized as one processing device.
  9. 　前記送信部は、互いに電圧レベルの異なるＮ個のレベルシフト信号を生成するレベルシフト信号生成部をさらに含み、
    　前記送信側信号処理部は、サンプリングした前記Ｎ個の送信側データ信号の電圧レベルを前記Ｎ個のレベルシフト信号に基づいて互いに異ならせることを特徴とする、請求項１に記載の信号伝送装置。     The transmission unit further includes a level shift signal generation unit that generates N level shift signals having different voltage levels.
    2. The signal transmission device according to claim 1, wherein the transmission-side signal processing unit varies the voltage levels of the sampled N transmission-side data signals based on the N level-shifted signals. .
  10. 　送信部と受信部との間で１本の伝送路により複数種類のデータのシリアル伝送を行う信号伝送装置における信号伝送方法であって、
    　周期的に変化する第１クロック信号の１周期毎に、当該第１クロック信号の周波数をＮ（Ｎは２以上の整数）逓倍した第２クロック信号に同期して、伝送すべきＮ個の送信側データ信号を順にサンプリングすると共に、サンプリングした当該Ｎ個の送信側データ信号の電圧レベルを互いに異ならせることにより伝送信号を生成するステップと、
    　前記伝送信号を、前記伝送路を介して前記送信部から前記受信部に伝送するステップと、
    　前記第１クロック信号の１周期毎に前記第２クロック信号に同期して前記伝送信号をサンプリングすると共に、サンプリングした当該伝送信号の電圧レベルを、電圧レベルが変化する前の前記Ｎ個の送信側データ信号に対応する電圧レベルに変化させることによりそれぞれＮ個の受信側データ信号を生成し出力するステップとを備えることを特徴とする、信号伝送方法。     A signal transmission method in a signal transmission apparatus for serially transmitting a plurality of types of data through a single transmission path between a transmission unit and a reception unit,
    N transmissions to be transmitted in synchronization with a second clock signal obtained by multiplying the frequency of the first clock signal by N (N is an integer of 2 or more) for each period of the periodically changing first clock signal. Sampling the side data signals in order, and generating a transmission signal by making the voltage levels of the sampled N transmission side data signals different from each other;
    Transmitting the transmission signal from the transmitter to the receiver via the transmission path;
    The transmission signal is sampled in synchronization with the second clock signal for each cycle of the first clock signal, and the voltage levels of the sampled transmission signal are set to the N transmission sides before the voltage level changes. And a step of generating and outputting N reception-side data signals by changing to a voltage level corresponding to the data signal, respectively.
PCT/JP2012/072697 2011-09-13 2012-09-06 Signal transmission device and signal transmission method WO2013038978A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004046054A (en) * 2001-10-03 2004-02-12 Nec Corp Displaying device and semiconductor device
WO2006038660A1 (en) * 2004-10-06 2006-04-13 Matsushita Electric Industrial Co., Ltd. Data communication system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004046054A (en) * 2001-10-03 2004-02-12 Nec Corp Displaying device and semiconductor device
WO2006038660A1 (en) * 2004-10-06 2006-04-13 Matsushita Electric Industrial Co., Ltd. Data communication system

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