KR20150001424A

KR20150001424A - Liquid Crystal Display Capable Of Driving High Voltage

Info

Publication number: KR20150001424A
Application number: KR1020130074638A
Authority: KR
Inventors: 김규진
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-06-27
Filing date: 2013-06-27
Publication date: 2015-01-06
Also published as: KR102016561B1

Abstract

The present invention relates to a liquid crystal display device for driving with a high voltage, capable of minimizing the reduction of an opening area. Any one among pixels which are arranged in an i-th horizontal pixel line (i is a positive integer over 2) in which a first gate line to which a first scan signal is applied and a second gate line to which a second scan signal whose phase is lagged more than the phase of the first scan signal includes a liquid crystal capacitor which is connected between a first node of a first pixel electrode and a second node of a second pixel electrode, a first storage capacitor which is connected between the first node and a third node, a second storage capacitor which is connected between the second node and the third node, a first TFT which is switched according to the first scan signal and applies a first data voltage on a first data line among the data lines to the first node, a second TFT which is switched according to the first scan signal and applies a second data voltage on a second data line among the data lines to the second node, a third TFT which is switched according to the first scan signal and applies the second data voltage to the third node, a fourth TFT which is switched according to the second scan signal and applies the first data voltage to the third node, and a fifth TFT which is switched according to the second scan signal and applies the second data voltage to the second node.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display

The present invention relates to a liquid crystal display device capable of driving at a high voltage.

BACKGROUND ART [0002] Liquid crystal display devices are used in various display devices such as portable information devices, office equipment, computers, and televisions. The liquid crystal display device includes a liquid crystal display panel for image display and a driver for driving the liquid crystal display panel. In the liquid crystal display panel, a plurality of data lines and a plurality of gate lines are formed, and a pixel including a liquid crystal capacitor is formed in each of the crossing areas. The driver includes a source driver for driving the data lines and a gate driver for driving the gate lines. When a data voltage is applied from the data lines in response to a gate signal from the gate lines, each liquid crystal capacitor of the pixels charges the data voltage. The liquid crystals are driven by the potential difference between the two ends of the liquid crystal capacitor to implement the gradation on a pixel basis.

Recently, as a new liquid crystal material that is driven in a wider voltage range than conventional liquid crystals has been developed, researches on a liquid crystal display device for high voltage driving using this new liquid crystal material have been actively studied. For high-voltage driving, the voltage range of the pixel driving voltage applied to the liquid crystal must be widened. The easiest way to widen the voltage range of the pixel drive voltage is to change the structure of the source driver to widen the output voltage range of the source driver. However, redesigning the source driver is expensive.

Therefore, the conventional high voltage driving liquid crystal display device changes the structure of the pixel instead of the source driver to widen the voltage range of the pixel driving voltage applied to the liquid crystal capacitor. That is, the conventional high voltage driving liquid crystal display device has a relatively complicated pixel for receiving the pixel driving voltage of the first range from the source driver and driving the liquid crystal with the pixel driving voltage of the second range wider than the first range. This pixel includes six thin film transistors (hereinafter referred to as TFTs), a liquid crystal capacitor, and a liquid crystal capacitor connected in series to both ends of the liquid crystal capacitor in order to boost the pixel drive voltage in the first range to the pixel drive voltage in the second range And four storage capacitors. The pixels are operated by the first and second scan signals of different phases. (E.g., Vdd including a first data voltage located on the upper side and a second data voltage located on the lower side with a reference voltage interposed therebetween) in a first range when the first scan signal is activated, And uses a coupling effect of the storage capacitors when the second scan signal is activated to reflect a first change (a rise from the reference voltage to the first data voltage) to one side of the liquid crystal capacitor, (The falling of the reference voltage to the second data voltage) is applied to the other side of the liquid crystal capacitor to boost the primary charged voltage of the liquid crystal capacitor to the pixel driving voltage of the second range.

The storage capacitor is formed in a wiring region existing between upper and lower neighboring pixels. In the conventional high voltage driving liquid crystal display device, a predetermined wiring region is divided into four to constitute four storage capacitors. At this time, there is a gap between neighboring storage capacitors in order to secure a process margin, and the capacitances of the storage capacitors are reduced due to these gaps. When the wiring area is designed to be wide in order to increase the capacity of the storage capacitors, there is a problem that the opening area for image display is reduced.

In the conventional high voltage driving liquid crystal display device, the reference voltage supply lines for supplying the reference voltage to the pixels are necessary for the above boosting operation. These reference voltage supply lines also contribute to reducing the opening area.

Therefore, an object of the present invention is to provide a high-voltage driving liquid crystal display device which boosts a pixel driving voltage in a first range to a pixel driving voltage in a second range using a charging characteristic of a pixel, .

In order to achieve the above object, according to an embodiment of the present invention, there is a liquid crystal display panel in which a plurality of horizontal pixel lines in which pixels are arranged, and a plurality of data lines and two gate lines are allocated to each horizontal pixel line In a liquid crystal display device for driving a high voltage, a first gate line to which a first scan signal is applied and a second gate line to which a second scan signal, which is out of phase with respect to the first scan signal, One of the pixels arranged in the horizontal pixel line is a liquid crystal capacitor connected between the first node of the first pixel electrode and the second node of the second pixel electrode; A first storage capacitor connected between the first node and the third node; A second storage capacitor connected between the second node and the third node; A first TFT switched according to the first scan signal to apply a first data voltage on a first one of the data lines to the first node; A second TFT which is switched in accordance with the first scan signal to apply a second data voltage on a second one of the data lines to the second node; A third TFT switched according to the first scan signal to apply the second data voltage to the third node; A fourth TFT switched according to the second scan signal to apply the first data voltage to the third node; And a fifth TFT which is switched according to the second scan signal and applies the second data voltage to the second node.

One of the pixels arranged in the ith horizontal pixel line includes a first auxiliary capacitor for stabilizing the potential of the first node; And a second auxiliary capacitor for stabilizing the potential of the second node; One side of the first auxiliary capacitor is connected to the first node, and the other side of the first auxiliary capacitor is connected to a scan signal whose phase is out of the third gate line and the fourth gate line assigned to the (i-1) Connected to the fourth gate line to be applied; One side of the second auxiliary capacitor is connected to the second node, and the other side of the second auxiliary capacitor is connected to the fourth gate line.

A third scan signal having a phase earlier than the first scan signal is applied to the third gate line, a fourth gate signal having a phase lower than that of the third scan signal, A signal is applied; The first to fourth scan signals have the same pulse width and are not overlapped with each other.

A third scan signal having a phase earlier than that of the first scan signal is applied to the third gate line, and a third scan signal having a phase opposite to that of the first scan signal, 4 gate signal is applied; Wherein the first and third scan signals have the same first pulse width and the second and fourth scan signals have the same second pulse width; The first pulse width is wider than the second pulse width, and the first scan signal and the fourth scan signal overlap each other.

A liquid crystal display device for high voltage driving having a liquid crystal display panel in which a plurality of horizontal pixel lines in which pixels are arranged according to an embodiment of the present invention and a plurality of data lines and two gate lines are allocated to each horizontal pixel line (I is a positive integer of 2 or more) horizontal pixels to which a first gate line to which a first scan signal is applied and a second gate line to which a second scan signal that is out of phase with respect to the first scan signal are applied, Wherein one of the pixels arranged in the line includes a liquid crystal capacitor connected between a first node of the first pixel electrode and a second node of the second pixel electrode; A first storage capacitor connected between the first node and the third node; A second storage capacitor connected between the second node and the third node; A third storage capacitor connected between the second node and the fourth node; A first TFT switched according to the first scan signal to apply a first data voltage on a first one of the data lines to the first node; A second TFT which is switched in accordance with the first scan signal to apply a second data voltage on a second one of the data lines to the second node; A third TFT switched according to the first scan signal to apply the second data voltage to the third node; A fourth TFT switched according to the second scan signal to apply the first data voltage to the third node; A fifth TFT which is switched according to the second scan signal to apply the second data voltage to the fourth node; And a sixth TFT that is switched according to the first scan signal and applies the first data voltage to the fourth node.

The pixels of the present invention do not require a reference voltage as in the prior art for the boosting operation. In the present invention, the reference voltage supply line does not need to be formed, and further, only (N-1) storage capacitors are required to boost the pixel drive voltage by (N-1) times. Therefore, when the boosting magnification of the present invention is the same as that of the prior art, the present invention is much easier to secure the opening area than the prior art. The present invention can further enhance the boosting magnification by adding a conductive film and a TFT in the pixel design without increasing the number of gate lines assigned to the pixels.

1 is a block diagram showing a liquid crystal display device for driving a high voltage according to an embodiment of the present invention.
2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
3 is a schematic diagram for explaining the capacity increase of the storage capacitors shown in FIG. 2;
4A and 4B are diagrams showing an equivalent circuit and an operation waveform of a pixel in a precharge period, respectively.
5A and 5B are diagrams showing an equivalent circuit and an operation waveform of a pixel in the boosting period, respectively.
FIG. 6 is a diagram illustrating an example of a scan signal applied to the pixel of FIG. 2. FIG.
FIG. 7 is a view showing another example of a scan signal applied to the pixel of FIG. 2. FIG.
FIG. 8A is a view showing a change in the charging voltage of the liquid crystal capacitor due to the scan signal of FIG. 6; FIG.
FIG. 8B is a view showing a change in the charging voltage of the liquid crystal capacitor due to the scan signal of FIG. 7; FIG.
9 is an equivalent circuit diagram of a pixel according to another embodiment of the present invention.
10 is a schematic view for explaining the capacity increase of the storage capacitors shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 10. FIG.

1 is a block diagram showing a liquid crystal display device for high voltage driving according to an embodiment of the present invention.

1, a liquid crystal display device for high voltage driving according to the present invention includes a liquid crystal display panel 10, a timing controller 11, a source driver 12, a gate driver 13, and a host system 14 .

In the liquid crystal display panel 10, a pixel array including pixels arranged in a matrix form by the intersection structure of the data lines 15 and the gate lines 16 is formed. The pixel array includes a plurality of horizontal pixel lines (L # 1 to L # k). Two gate lines 16 are allocated to the horizontal pixel lines L # 1 to L # k. A plurality of pixels arranged in the same horizontal pixel line are connected in common to two gate lines assigned to the horizontal pixel line. The pixels can receive the first scan signal from the first gate line of the two gate lines and the second scan signal out of phase with respect to the first scan signal from the second gate line of the two gate lines Can receive.

Each of the pixels is driven by the first driver circuit 12 to boost the pixel driving voltage of the first range inputted from the source driver 12 to a second range of the pixel driving voltage of the second range, A liquid crystal capacitor including a pixel electrode and a second pixel electrode, a plurality of TFTs for driving a liquid crystal capacitor, and a plurality of storage capacitors. Each of the pixels is assigned a first data line for supplying a first data voltage to the first pixel electrode and a second data line for supplying a second data voltage to the second pixel electrode. Here, the pixel driving voltage of the first range is implemented by the first data voltage and the second data voltage.

The liquid crystal capacitor of each pixel pre-charges the pixel driving voltage of the first range in response to the first scan signal, and supplies the precharged pixel driving voltage of the first range to the pixels of the second range in response to the second scan signal. Boost with the driving voltage. For this boosting operation, (N-1) storage capacitors are formed by N conductive films (N is a positive integer of 3 or more) stacked with a dielectric layer sandwiched therebetween, in each of the pixels. In this case, the pixel driving voltage in the second range can be boosted by about (N-1) times as much as the pixel driving voltage in the first range. In FIGS. 2 to 8B, an example in which pixel driving voltage is doubled by using two storage capacitors formed by three conductive films will be described. In FIGS. 9 and 10, an example of boosting the pixel driving voltage by three times using three storage capacitors formed by four conductive films will be described. The pixels of the present invention do not require a reference voltage as in the prior art for the boosting operation. In the present invention, the reference voltage supply line does not need to be formed, and further, only (N-1) storage capacitors are required to boost the pixel drive voltage by (N-1) times. Therefore, when the boosting magnification of the present invention is the same as that of the prior art, the present invention is much easier to secure the opening area than the prior art. The present invention can further enhance the boosting magnification by adding a conductive film and a TFT in the pixel design without increasing the number of gate lines assigned to the pixels.

The pixels of the present invention may include an R pixel including a red color filter for red implementation, a G pixel including a green color filter for green implementation, and a B pixel including a blue color filter for blue implementation. The liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS . The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 receives digital video data RGB of an input image from the host system 14 through a low voltage differential signaling (LVDS) interface method and converts the digital video data RGB of the input video into mini-LVDS And supplies it to the source driver 12 through the interface method. The timing controller 11 arranges the digital video data RGB input from the host system 14 in accordance with the arrangement order of the R pixel, the G pixel and the B pixel in the pixel array, and supplies the digital video data RGB to the source driver 12. [

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 14, And generates control signals for controlling the operation timings of the driver 12 and the gate driver 13. [ The control signals include a gate timing control signal for controlling the operation timing of the gate driver 13 and a source timing control signal for controlling the operation timing of the source driver 12. [

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to a gate drive IC (integrated circuit) generating a first gate pulse to control the gate drive IC so that a first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The source timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the source driver 12. [ The source sampling clock SSC is a clock signal for controlling the sampling timing of data in the source driver 12 on the basis of the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages sequentially output from each of the source drive ICs. The source output enable signal SOE controls the output timing of the source driver 12.

The source driver 12 includes a shift register, a latch array, a digital-analog converter, an output circuit, and the like. The source driver 12 latches the digital video data RGB according to the source timing control signal and then converts the latched data into an analog positive / negative gamma compensation voltage to convert the data voltages whose polarities are reversed in a predetermined cycle to a plurality of To the data lines 15 through the output channels.

The gate driver 13 sequentially supplies the scan signals to the gate lines 16 according to the gate timing control signals using the shift register and the level shifter. The shift register of the gate driver 13 may be formed directly on the lower glass substrate according to a gate-driver in panel (GIP) scheme.

2 shows an example of a pixel according to an embodiment of the present invention in detail. 3 is a schematic diagram for explaining the capacity increase of the storage capacitors shown in FIG.

FIG. 2 shows one of the pixels arranged in the second horizontal pixel line L # 2. The pixel according to an embodiment of the present invention is connected to the first gate line 162-1 and the second gate line 162-2 allocated to the second horizontal pixel line L # The first scan signal Vg2-1 from the line 162-1 and the second scan signal Vg2-2 that is out of phase with the first scan signal Vg2-1 from the second gate line 162-2, ).

A pixel according to an embodiment of the present invention includes a liquid crystal capacitor Clc, first to fifth TFTs M1 to M5, and first and second storage capacitors Cst1 and Cst2.

The liquid crystal capacitor Clc is connected between the first node N1 of the first pixel electrode and the second node N2 of the second pixel electrode. The first range of pixel drive voltages pre-charged in the liquid crystal capacitor Clc in accordance with the first scan signal Vg2-1 is applied to the second range of the second range in response to the second scan signal Vg2-2, Of the pixel driving voltage. The gradation of the pixel is implemented by the pixel driving voltage in the second range charged in the liquid crystal capacitor Clc.

The first storage capacitor Cst1 is connected between the first node N1 and the third node N3. When the potential VN3 of the third node N3 changes by a predetermined value, the first storage capacitor Cst1 reflects the change to the potential VN1 of the first node N1.

The second storage capacitor Cst2 is connected between the second node N2 and the third node N3. The second storage capacitor Cst2 stabilizes the potential VN3 of the third node N3.

The first TFT M1 is switched according to the first scan signal Vg2-1 to apply the first data voltage Vd + on the first data line 151 to the first node N1. The gate electrode of the first TFT M1 is connected to the first gate line 162-1 to which the first scan signal Vg2-1 is supplied and the drain electrode thereof is connected to the first data line 151, The electrode is connected to the first node N1.

The second TFT M2 is switched in accordance with the first scan signal Vg2-1 to apply the second data voltage Vd- on the second data line 152 to the second node N2. Here, the second data voltage Vd- together with the first data voltage Vd + implements a first range of pixel drive voltages. The gate electrode of the second TFT M2 is connected to the first gate line 162-1 to which the first scan signal Vg2-1 is supplied and the drain electrode thereof is connected to the second data line 152, And the electrode is connected to the second node N2.

The third TFT M3 is switched according to the first scan signal Vg2-1 to apply the second data voltage Vd- on the second data line 152 to the third node N3. The gate electrode of the third TFT M3 is connected to the first gate line 162-1 to which the first scan signal Vg2-1 is supplied and the drain electrode thereof is connected to the second data line 152, And the electrode is connected to the third node N3.

The fourth TFT M4 is switched according to the second scan signal Vg2-2 to apply the first data voltage Vd + on the first data line 151 to the third node N3. The gate electrode of the fourth TFT M4 is connected to the second gate line 162-2 to which the second scan signal Vg2-2 is supplied, the drain electrode is connected to the first data line 151, And the electrode is connected to the third node N3.

The fifth TFT M5 is switched according to the second scan signal Vg2-2 to apply the second data voltage Vd- on the second data line 152 to the second node N2. The gate electrode of the fifth TFT M5 is connected to the second gate line 162-2 to which the second scan signal Vg2-2 is supplied and the drain electrode thereof is connected to the second data line 152, And the electrode is connected to the second node N2.

The pixel according to an embodiment of the present invention may further include first and second auxiliary capacitors Cref1 and Cref2 for stabilizing the potentials VN1 and VN2 of the first and second nodes N1 and N2 .

One side of the first auxiliary capacitor Cref1 is connected to the first node N1 and the other side of the first auxiliary capacitor Cref1 is connected to the third gate line (not shown) assigned to the first horizontal pixel line L # And the fourth gate line 161-2 are applied to the fourth gate line 161-2 to which the out-of-phase scan signal is applied. When the first scan signal Vg2-1 is changed from the gate high voltage of the turn-on level to the gate low voltage of the turn-off level, the first auxiliary capacitor Cref1 is turned on, And serves to stably maintain the voltage (Vd +).

One side of the second auxiliary capacitor Cref2 is connected to the second node N2 and the other side of the second auxiliary capacitor Cref2 is connected to the fourth gate line 161 -2). When the first scan signal Vg2-1 is changed from the gate high voltage of the turn-on level to the gate low voltage of the turn-off level, the second auxiliary capacitor Cref2 is turned on, And serves to stably maintain the voltage Vd-.

As shown in FIG. 3, the pixel according to an embodiment of the present invention includes three conductive films L1, L2, and L3 stacked with a dielectric layer (not shown, formed of an insulating film, a protective film, etc.) A first storage capacitor Cst1 connected between the first conductive film L1 and the third conductive film L3 and a second storage capacitor Cst2 connected between the third conductive film L3 and the second conductive film L2. And the pixel driving voltage is doubled by using the capacitor Cst2. The present invention can reduce the number of storage capacitors compared to the prior art, and it is not necessary to divide each conductive film in order to increase the number of storage capacitors. According to the present invention, the electrode area of the storage capacitor can be approximately twice as large as that of the conventional storage capacitor, and the distance between the electrodes of the storage capacitor can be reduced to about 1/2 times that of the conventional storage capacitor. It can be increased four times. Therefore, the present invention is advantageous in that it is not necessary to design a wider wiring area in order to increase the capacity of the storage capacitor, so that the opening for image display can be widened.

4A and 4B show the equivalent circuit and the operation waveform of the pixel in the precharge period, respectively. 5A and 5B show the equivalent circuit and the operation waveform of the pixel in the boosting period, respectively.

As shown in Figs. 4A and 4B, in the precharge period P1, the first TFT M1, the second TFT M2, and the third TFT M2 are turned on in response to the first scan signal Vg2-1 of the turn- 3 TFT (M3) is turned on. In the precharge period P1, the fourth TFT M4 and the fifth TFT M5 are turned off by the second scan signal Vg2-2 of the turn-off level. As a result, the first data voltage Vd + is applied to the first node N1 and the second data voltage Vd- is applied to the second and third nodes N2 and N3. Accordingly, the liquid crystal capacitor Clc is primarily charged with the pixel drive voltage Vdd of the first range, which is realized by the first data voltage Vd + and the second data voltage Vd-.

5A and 5B, the fourth TFT M4 and the fifth TFT M5 are turned on in response to the second scan signal Vg2-2 of the turn-on level in the boosting period P2 . In the boosting period P2, the first TFT M1, the second TFT M2, and the third TFT M3 are turned off by the first scan signal Vg2-1 of the turn-off level.

In the boosting period P2, the potential VN3 of the third node N3 is changed from the second data voltage Vd- to the first data voltage Vd +, and the variation (Vd-) - (Vd + ) Is reflected to the potential VN1 of the first node N1 by the coupling effect of the first storage capacitor Cst1. Therefore, in the boosting period P2, the potential VN1 of the first node N1 corresponds to the potential change (Vd -) - (Vd +) of the third node N3, Of the pixel driving voltage Vdd. Accordingly, the liquid crystal capacitor Clc is finally charged with the pixel drive voltage Vdd in the second range and the pixel drive voltage in the second range (approximately 2Vdd) determined by adding the boosting voltage Vdd to the second range. The pixel realizes the gradation according to the pixel driving voltage in the second range.

6 and 7 show examples of scan signals applied to the pixel of FIG. 8A shows a change in the charging voltage of the liquid crystal capacitor due to the scan signal of FIG. FIG. 8B shows a change in the charging voltage of the liquid crystal capacitor due to the scan signal of FIG.

The third and fourth scan signals Vg1-1 and Vg1-2 in FIG. 6 are respectively applied to the third gate line and the fourth gate line assigned to the first horizontal pixel line L # 1, The second scan signals Vg2-1 and Vg2-2 are applied to the first gate line and the second gate line respectively assigned to the second horizontal pixel line L # 2.

6, the phase of the third scan signal Vg1-1 is the highest, the phase of the fourth scan signal Vg1-2 is the next, and the phase of the first scan signal Vg2-1 is the fourth The phase of the second scan signal Vg2-2 is lower than the phase of the scan signal Vg1-2 and the phase of the second scan signal Vg2-2 is behind the phase of the first scan signal Vg2-1. Here, the first to fourth scan signals Vg1-1, Vg1-2, Vg2-1, and Vg2-2 have the same pulse width and may overlap each other.

In the case of FIG. 6, a scan signal can be generated without changing the design of a general gate driver. However, both ends of the liquid crystal capacitor are in a floating state until the first scan signal (Vg2-1) corresponding to the precharge period (P1) is applied in the frame, so that the voltage charged in the liquid crystal capacitor in the previous frame Is not maintained constant due to the influence of the fourth scan signal (Vg1-2) preceding the signal (Vg2-1), and is increased by the amount of hatched as shown in FIG. 8A.

The scan signal of FIG. 7 is proposed to overcome the drawbacks of FIG. 7, a third scan signal Vg1-1 having a phase earlier than the first scan signal Vg2-1 is applied to the third gate line, and the first scan signal Vg2-1 is applied to the fourth gate line. -1 or a fourth gate signal Vg1-2 whose phase is the same as that of the first scan signal Vg2-1.

7, the first and third scan signals Vg1-1 and Vg2-1 have the same first pulse width and the second and fourth scan signals Vg1-2 and Vg2-2 are the same 2 pulse width, and the first pulse width is selected to be wider than the second pulse width. The first scan signal Vg2-1 and the fourth scan signal Vg1-2 are overlapped with each other only for a predetermined period P3.

7, since the first scan signal Vg2-1 is activated earlier than the fourth scan signal Vg1-2 or at the same timing as the fourth scan signal Vg1-2, A phenomenon that the voltage charged in the liquid crystal capacitor in the previous frame shakes due to the influence of the fourth scan signal Vg1-2 can be suppressed.

9 shows an equivalent circuit of a pixel according to another embodiment of the present invention. 10 is a schematic diagram for explaining the capacity increase of the storage capacitors shown in FIG.

9 shows a connection structure of pixels for making a boosting magnification in a pixel larger than twice without adding a gate line. By using three storage capacitors formed by four conductive films, a pixel driving voltage is set to 3 Boost your ship.

9, the sixth TFT M6 and the third storage capacitor Cst3 are further added as compared with the pixel configuration of FIG. The source electrode of the fifth TFT M5 is changed to be connected to the fourth node N4 connecting the sixth TFT M6 and the third storage capacitor Cst3.

The third storage capacitor Cst3 is connected between the second node N2 and the fourth node N4. The third storage capacitor Cst3 includes a third conductive film L3, a newly added fourth conductive film L4 and a dielectric film between the third conductive film L3 and the third conductive film L4 as shown in FIG.

The sixth TFT M5 is switched according to the first scan signal Vg2-1 to apply the first data voltage Vd + on the first data line 151 to the fourth node N4. The gate electrode of the sixth TFT M6 is connected to the first gate line 162-1 to which the first scan signal Vg2-1 is supplied and the drain electrode thereof is connected to the first data line 151, And the electrode is connected to the fourth node N4.

The fifth TFT M5 is switched according to the second scan signal Vg2-2 to apply the second data voltage Vd- on the second data line 152 to the fourth node N4. The gate electrode of the fifth TFT M5 is connected to the second gate line 162-2 to which the second scan signal Vg2-2 is supplied and the drain electrode thereof is connected to the second data line 152, And the electrode is connected to the fourth node N4.

In the pixel of Fig. 9, not only the potential VN3 of the third node N3 but also the potential VN4 of the fourth node N4 also changes in the boosting period P2.

In the boosting period P2, the potential VN3 of the third node N3 is changed from the second data voltage Vd- to the first data voltage Vd +, and the variation (Vd-) - (Vd + ) Is reflected to the potential VN1 of the first node N1 by the coupling effect of the first storage capacitor Cst1. Therefore, in the boosting period P2, the potential VN1 of the first node N1 corresponds to the potential change (Vd -) - (Vd +) of the third node N3, Of the pixel driving voltage Vdd.

In the boosting period P2, the potential VN4 of the fourth node N4 is changed from the first data voltage Vd + to the second data voltage Vd-, and the change (Vd +) - ( Vd-) is reflected to the potential VN2 of the second node N2 by the coupling effect of the third storage capacitor Cst3. Therefore, in the boosting period P2, the potential VN2 of the second node N2 corresponds to the potential change (Vd +) - (Vd-) of the fourth node N4, Of the pixel driving voltage Vdd.

Accordingly, the liquid crystal capacitor Clc is supplied with the pixel drive voltage Vdd of the second range, which is the second range, and the boosting voltages 2Vdd of the second boosting operation, 3Vdd) is finally charged. The pixel implements the gradation according to the pixel driving voltage in the second range.

The scan signals of FIGS. 6 and 7 can be applied to the pixel of FIG. 9 as it is, and the operation and effect of the scan signal are the same as those described in FIGS. 8A and 8B.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: Source driver 13: Gate driver
15: Data lines 16: Gate lines

Claims

There is provided a liquid crystal display device for high voltage driving having a liquid crystal display panel in which a plurality of horizontal pixel lines in which pixels are arranged and a plurality of data lines and two gate lines are allocated to each horizontal pixel line,
(I is a positive integer equal to or greater than two) horizontal pixel lines to which a first gate line to which a first scan signal is applied and a second gate line to which a second scan signal that is out of phase with the first scan signal is applied One of the arranged pixels is a pixel-
A liquid crystal capacitor connected between a first node of the first pixel electrode and a second node of the second pixel electrode;
A first storage capacitor connected between the first node and the third node;
A second storage capacitor connected between the second node and the third node;
A first TFT switched according to the first scan signal to apply a first data voltage on a first one of the data lines to the first node;
A second TFT which is switched in accordance with the first scan signal to apply a second data voltage on a second one of the data lines to the second node;
A third TFT switched according to the first scan signal to apply the second data voltage to the third node;
A fourth TFT switched according to the second scan signal to apply the first data voltage to the third node; And
And a fifth TFT which is switched according to the second scan signal and applies the second data voltage to the second node.

The method according to claim 1,
One of the pixels arranged in the i < th > horizontal pixel line,
A first auxiliary capacitor for stabilizing the potential of the first node; And
Further comprising: a second auxiliary capacitor for stabilizing the potential of the second node;
One side of the first auxiliary capacitor is connected to the first node, and the other side of the first auxiliary capacitor is connected to a scan signal whose phase is out of the third gate line and the fourth gate line assigned to the (i-1) Connected to the fourth gate line to be applied;
Wherein one side of the second auxiliary capacitor is connected to the second node and the other side of the second auxiliary capacitor is connected to the fourth gate line.

3. The method of claim 2,
A third scan signal having a phase earlier than the first scan signal is applied to the third gate line, a fourth gate signal having a phase lower than that of the third scan signal, A signal is applied;
Wherein the first to fourth scan signals have the same pulse width and are not overlapped with each other.

3. The method of claim 2,
A third scan signal having a phase earlier than that of the first scan signal is applied to the third gate line, and a third scan signal having a phase opposite to that of the first scan signal, 4 gate signal is applied;
Wherein the first and third scan signals have the same first pulse width and the second and fourth scan signals have the same second pulse width;
Wherein the first pulse width is larger than the second pulse width, and the first scan signal and the fourth scan signal overlap each other.

There is provided a liquid crystal display device for high voltage driving having a liquid crystal display panel in which a plurality of horizontal pixel lines in which pixels are arranged and a plurality of data lines and two gate lines are allocated to each horizontal pixel line,
(I is a positive integer equal to or greater than two) horizontal pixel lines to which a first gate line to which a first scan signal is applied and a second gate line to which a second scan signal that is out of phase with the first scan signal is applied One of the arranged pixels is a pixel-
A liquid crystal capacitor connected between a first node of the first pixel electrode and a second node of the second pixel electrode;
A first storage capacitor connected between the first node and the third node;
A second storage capacitor connected between the second node and the third node;
A third storage capacitor connected between the second node and the fourth node;
A first TFT switched according to the first scan signal to apply a first data voltage on a first one of the data lines to the first node;
A second TFT which is switched in accordance with the first scan signal to apply a second data voltage on a second one of the data lines to the second node;
A third TFT switched according to the first scan signal to apply the second data voltage to the third node;
A fourth TFT switched according to the second scan signal to apply the first data voltage to the third node;
A fifth TFT which is switched according to the second scan signal to apply the second data voltage to the fourth node; And
And a sixth TFT which is switched according to the first scan signal and applies the first data voltage to the fourth node.

6. The method of claim 5,
One of the pixels arranged in the i < th > horizontal pixel line,
A first auxiliary capacitor for stabilizing the potential of the first node; And
Further comprising: a second auxiliary capacitor for stabilizing the potential of the second node;
One side of the first auxiliary capacitor is connected to the first node, and the other side of the first auxiliary capacitor is connected to a scan signal whose phase is out of the third gate line and the fourth gate line assigned to the (i-1) Connected to the fourth gate line to be applied;
Wherein one side of the second auxiliary capacitor is connected to the second node and the other side of the second auxiliary capacitor is connected to the fourth gate line.

The method according to claim 6,
A third scan signal having a phase earlier than the first scan signal is applied to the third gate line, a fourth gate signal having a phase lower than that of the third scan signal, A signal is applied;
Wherein the first to fourth scan signals have the same pulse width and are not overlapped with each other.

The method according to claim 6,
A third scan signal having a phase earlier than that of the first scan signal is applied to the third gate line, and a third scan signal having a phase opposite to that of the first scan signal, 4 gate signal is applied;
Wherein the first and third scan signals have the same first pulse width and the second and fourth scan signals have the same second pulse width;
Wherein the first pulse width is larger than the second pulse width, and the first scan signal and the fourth scan signal overlap each other.