KR20140112674A - Fabricating method of stacked semiconductor package - Google Patents

Abstract

The present technology includes a method for manufacturing a laminated semiconductor package. The method included in the technology includes a step of forming multiple semiconductor chips including a bonding pad and a through electrode electrically connected to the bonding pad in a chip area of a wafer including a front side divided into the chip area and an outer area surrounding the chip area and the rear side facing the front side, a step of forming a bump on the bonding pad, a step of forming an attachment member covering the front side and exposing an upper part of the bump, a step of polishing the central part of the rear side corresponding to the chip area to expose the through electrode and make a ring type reinforcing part left at the border of the rear side, a step of protruding the through electrode by etching the rear side, a step of forming the insulating film covering the rear side and the upper part of the through electrode, a step of individualizing the semiconductor chips by cutting the wafer, and a step of laminating the individualized semiconductor chips so that the bump of the upper semiconductor chip can be directly attached to the through electrode of the lower semiconductor chip.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a stacked semiconductor package,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package technology, and more particularly, to a method of manufacturing a semiconductor package.

BACKGROUND ART [0002] Package technology for integrated circuits in the semiconductor industry has been continuously developed in order to satisfy demands for miniaturization and reliability of mounting. Recently, with the miniaturization of electric / electronic products and the demand for high performance, various technologies for lamination have been developed have.

In the semiconductor industry, "lamination" means stacking two or more semiconductor chips or semiconductor packages vertically. According to this stacking technique, in the case of a memory device, can do. Further, the laminated semiconductor package has an advantage in terms of efficiency of use of mounting density and mounting area as well as memory capacity increase. As a result, research and development on laminated semiconductor packages have been accelerated.

As one example of the laminated semiconductor package, a laminated semiconductor package in which a through electrode is formed in a semiconductor chip to make a physical and electrical connection between the upper and lower semiconductor chips is introduced.

A front bump is formed on the front surface of the wafer so as to be connected to the penetrating electrode. The front bump is formed on the front surface of the semiconductor chip, . Then, in order to prevent warping and cracking of the thinly processed wafer through the subsequent back grinding process, the back surface of the wafer is back-grounded with the support substrate attached to the front surface of the front bump formed wafer To expose the penetrating electrode, and then form a back bump on the penetrating electrode on the rear surface of the wafer. Thereafter, the support substrate is separated, the semiconductor chips are individualized by sowing the wafers, and the individual semiconductor chips are stacked so that the front bumps of the upper semiconductor chip are bonded onto the rear bumps of the lower semiconductor chip under the interposition of the solder bumps, Thereby forming a package.

The stacked semiconductor package using the penetrating electrode has an advantage that a high operating speed and miniaturization can be achieved because the electrical connection is made through the penetrating electrode.

However, the process of attaching the support substrate, the process of separating the support substrate, and the process of bonding the upper and lower semiconductor chips through the solder bumps are expensive and expensive processes. . In addition, when the solder bump is not in the position, the electrical connection between the upper and lower semiconductor chips is broken, and a large resistance value is obtained as compared with the metal used as the material of the penetrating electrode, the front bump and the rear bump There is a problem that the electrical reliability and characteristics are deteriorated because the signal transmission speed is slowed due to the solder bump.

Embodiments of the present invention provide a method of manufacturing a laminated semiconductor package that can lower manufacturing costs and improve electrical reliability and characteristics.

A method of manufacturing a semiconductor package according to an embodiment of the present invention includes a step of forming a bonding pad on a chip area of a wafer having a chip area and a front surface partitioned by an outer circumferential area surrounding the chip area, Forming a plurality of semiconductor chips each having a through electrode electrically connected to the pad; forming a bump on the bonding pad; forming an adhesive member covering the front surface and exposing an upper end of the bump; Polishing the central portion of the rear surface corresponding to the chip region such that the penetrating electrode is exposed and the annular reinforcing portion remains at the rear edge; etching the rear surface to protrude the penetrating electrode; Forming an insulating film that exposes an upper end portion of the penetrating electrode; And the step of laminating the individualized semiconductor chips so that the bumps of the upper semiconductor chip are directly bonded onto the penetrating electrodes of the lower semiconductor chip.

The step of forming the adhesive member may include applying an adhesive on the front surface including the bump, curing the adhesive, and polishing the adhesive to expose the bump.

The step of laminating the protective tape on the adhesive member including the bump may be further included before the step of polishing the center portion of the rear surface after the step of forming the adhesive member.

The step of attaching the dicing tape mounted on the wafer ring on the insulating film and the step of removing the protective tape may be further included before the step of forming the semiconductor chips after the step of forming the insulating film.

The step of etching the rear surface to protrude the penetrating electrode may be performed using a chemical mechanical polishing process or a dry etching process.

The forming of the insulating layer may include forming an insulating layer on the rear surface including the projected through electrode, and polishing the insulating layer to expose the penetrating electrode.

The adhesion member may include a polymer, and the insulating film may include at least one selected from the group consisting of a nitride film and an oxide film.

The method may further include removing oxide existing on the surface of the bump and the penetrating electrode before the step of stacking the semiconductor chips, and removing the oxide may be performed using a surface activation treatment process.

The step of laminating the semiconductor chips may further include an annealing step for strengthening bonding between the bumps and the penetrating electrodes of the stacked semiconductor chips and for strengthening the adhesive strength of the adhesive members.

According to the present invention, a support substrate attaching step, a support substrate separating step, and a solder bump, in which the strength of a thinly processed wafer is maintained by the annular reinforcing part and the penetrating electrodes and bumps of the upper and lower semiconductor chips are directly bonded, Since the mediated chip bonding process is eliminated, the cost of fabricating the semiconductor package is reduced. In addition, since the solder bumps are not used, electrical characteristics and reliability degradation caused by the solder bumps are fundamentally prevented, which improves the electrical characteristics and reliability of the semiconductor package.

1 is a perspective view showing a wafer on which a semiconductor chip is formed.
2 is a cross-sectional view taken along the line I-I 'of Fig.
3 is a cross-sectional view showing the state after the bump forming process.
4 is a sectional view showing a state after the adhesive member forming step.
5 is a perspective view showing a state after the protective tape attaching step.
6 is a cross-sectional view taken along line II-II 'of FIG.
7 is a perspective view of the wafer shown in FIG. 5 in an inverted state.
8 is a perspective view showing a wafer rear surface polishing process.
9 is a cross-sectional view showing the state after the wafer rear surface polishing process.
10 is a cross-sectional view showing the state after the rear etching process.
11 is a cross-sectional view showing a state after the insulating film forming step.
12 is a sectional view showing the state after the protective tape removing step.
13 is a cross-sectional view showing the state after the wafer cutting process.
14 is a cross-sectional view showing the state after the chip stacking step.
15 is a perspective view showing an electronic device having a laminated semiconductor package according to an embodiment of the present invention.
16 is a block diagram showing an example of an electronic system including a laminated semiconductor package according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIGS. 1 and 2, a plurality of semiconductor chips 100 are formed on a front surface 11 of a wafer 10.

The wafer 10 has a back surface 12 facing the front surface 11 and the front surface 11 and the front surface 11 of the wafer 10 has a chip region CR and a chip region CR ) Is divided into an outer peripheral region (PR). In the chip region CR, a street 10A is formed in a lattice shape, and the semiconductor chip 100 is formed in each region defined by the street 10A.

Each of the semiconductor chips 100 includes a circuit portion (not shown), a bonding pad 110, and a penetrating electrode 120. The circuit unit may include a data storage unit for storing data and a data processing unit for processing data, and may be composed of semiconductor devices such as transistors, capacitors, and fuses necessary for chip operation. The bonding pad 110 is formed on the front surface 11 as an electrical contact of a circuit portion for electrical connection with the outside.

The penetrating electrode 120 is formed by etching a semiconductor chip 100 from the front surface 11 by, for example, a photolithography process to form a blind via hole, filling a blind via hole with a metal material, for example, copper And is electrically connected to the bonding pad 110. In the present embodiment, the penetrating electrode 120 penetrates the bonding pad 110 and is directly connected to the bonding pad 110. [

As is well known, 3D integrated circuit (IC) process technology using through electrodes is classified into Via first, Via middle, and Via last depending on when the through electrode is formed . Via First conducts a front-end-of-line (FEOL) process to form a semiconductor element and a contact plug after forming the penetrating electrode. After the FEAM process, the through-hole electrode is formed and then the back-end-of-line (BEOL) process is performed. The viaarest forms a through electrode on the wafer where the FEOL process and the BEOL process are completed.

In this embodiment, a case has been shown and described in which a through-hole is formed in a via last, that is, a wafer on which the FEOL process and the BEOL process are completed. However, the present invention is not limited to such an embodiment, and a via-first or non-intermediate scheme is also usable. In this case, since the FEOL / BEOL process or the BEOL process is performed after the penetrating electrode is formed, the penetrating electrode is not exposed to the front surface 11 of the wafer 10 and is not directly connected to the bonding pad 110, And is electrically connected to the bonding pads.

Subsequently, the bump 130 is formed on the bonding pad 110 as shown in FIG.

The bump 130 is formed by forming a bump metal layer on the front surface 11 of the wafer 10 using any one of an electrolytic plating process, an electroless plating process, and a sputtering process, May be formed by patterning.

4, an adhesive is applied on the front surface 11 of the wafer 10 including the bump 130 by a spin coating method, and the adhesive is cured by a curing process, And then the adhesive is polished by a chemical mechanical polishing (CMP) process so as to expose the bump 130 to cover the front face 11 of the wafer 10, The adhesive member 20 is exposed. As the material of the adhesive member 20, a polymer may be used.

Then, the protective tape 30 is laminated on the adhesive member 20 including the bumps 130 as shown in Figs. 5 and 6. 7 is a perspective view of the wafer shown in FIG. 5 in an inverted state.

Then, a back surface process for polishing the back surface 12 of the wafer 10 is performed. The back-grinding process is carried out, for example, by using the grinding apparatus shown in Fig.

The polishing apparatus includes a rotatable chuck table 210 and a polishing unit 220 for polishing the wafer 10. The polishing unit 220 includes a rotatable and ascendable spindle 221 and a polishing wheel 222 having a plurality of polishing pads 223 mounted on the bottom surface thereof.

The side of the protective tape 30 is sucked and held by the chuck table 210 and the back surface 12 of the wafer 10 is set against the polishing pad 223. The polishing pad 223 is rotated in the direction indicated by the arrow B while the chuck table 210 is rotated in the direction indicated by the arrow A and the polishing transfer mechanism (not shown) Is brought into contact with the rear face 12 of the wafer 10 and then the polishing wheel 222 is transferred to polish the center portion of the rear face 12 corresponding to the chip region CR. The back polishing process is performed until the penetrating electrode 120 is exposed.

9, the central portion of the rear face 12 corresponding to the chip region CR is polished to form the circular concave portion 40 and the rear face 12 corresponding to the outer peripheral region PR The edge remains and the annular reinforcing portion 50 is formed.

10, the rear surface 12 of the wafer 10 is etched by a CMP process or a dry etch process to protrude the penetrating electrode 120. Next, as shown in FIG.

11, an insulating layer is formed on the rear surface 12 of the wafer 10 including the protruding penetrating electrode 120 by, for example, a CVD (chemical vapor deposition) process, and the penetrating electrode 120 The insulating layer 60 is formed so as to cover the rear surface 12 of the wafer 10 and expose the upper end of the penetrating electrode 120. The insulating layer 60 may include at least one selected from the group consisting of an oxide layer and a nitride layer, and a CMP process may be used for polishing the insulating layer.

A dicing tape 72 mounted on a wafer ring (not shown) is attached to the rear surface 12 side of the wafer 10 on which the insulating film 70 is formed, The protective tape 30 attached to the front surface 11 side is removed.

Thereafter, as shown in Fig. 13, the wafer 10 is cut along the street 10A.

14, the upper semiconductor chip 100 is formed on the penetrating electrode 120 of the lower semiconductor chip 100. Then, as shown in FIG. 14, the upper semiconductor chip 100 is removed from the dicing tape 72, The semiconductor chips 100 are stacked on the structure 300 such that the bumps 130 of the semiconductor chips 100 are directly bonded.

The structure 300 may be a wafer level package. Although a case where a wafer level package is used as the structure 300 has been shown and described in this embodiment, any one of the printed circuit board and the interposer may be used as the structure 300.

A high-speed ion beam such as an Ar plasma is applied to the penetrating electrode 120 and the bump 130 in a very high vacuum before stacking the semiconductor chips 100 in order to increase the bonding strength between the penetrating electrode 120 and the bumps 130. [ A surface activated process for removing the oxide by colliding with the surface may be further performed.

Although not shown, an annealing process is performed for strengthening bonding between the penetrating electrode 120 of the stacked semiconductor chips 100 and the bump 130, and for enhancing the adhesion of the adhesive member 20.

According to the above-described embodiment, the support substrate attaching step, the support substrate separating step, and the solder attaching step, in which the strength of the thinly processed wafer is maintained by the annular reinforcing part and the penetrating electrodes and bumps of the upper and lower semiconductor chips are directly bonded, The bump-mediated chip bonding process is eliminated, thereby reducing the cost of fabricating the semiconductor package. In addition, since the solder bumps are not used, electrical characteristics and reliability degradation caused by the solder bumps are fundamentally prevented, which improves the electrical characteristics and reliability of the semiconductor package.

The laminated semiconductor package according to the embodiment described above can be applied to various electronic devices.

15 is a perspective view showing an electronic device having a laminated semiconductor package according to an embodiment of the present invention.

Referring to FIG. 15, a laminated semiconductor package according to embodiments of the present invention can be applied to an electronic device 1000 such as a cellular phone. The laminated semiconductor package of the present embodiments can be manufactured by a simple process at a low cost and is advantageous for improving cost competitiveness and electrical reliability of the electronic device 1000 because it does not use solder bumps which cause deterioration of electrical reliability. The electronic device is not limited to the mobile phone shown in Fig. 15, but may be a portable electronic device, a laptop computer, a portable computer, a portable multimedia player (PMP), an MP3 player, a camcorder, a web tablet ), A wireless telephone, a navigation system, a personal digital assistant (PDA), and the like.

16 is a block diagram showing an example of an electronic system including a laminated semiconductor package according to embodiments of the present invention.

16, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a storage device 1330. The controller 1310, the input / output device 1320, and the storage device 1330 may be coupled through a bus 1350. [ The bus 1350 may be a path through which data flows. For example, the controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions. The controller 1310 and the storage device 1330 may include a laminated semiconductor package according to the present invention. The input / output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 1330 is a device for storing data. The storage device 1330 may store data and / or instructions that may be executed by the controller 1310. The storage device 1330 may include a volatile storage element and / or a non-volatile storage element. Alternatively, the storage device 1330 may be formed of a flash memory. For example, a flash memory to which the technique of the present invention is applied can be mounted on an information processing system such as a mobile device or a desktop computer. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 1300 can stably store a large amount of data in the flash memory system. The electronic system 1300 may further include an interface 1340 for transferring data to or receiving data from the communication network. The interface 1340 may be in wired or wireless form. For example, the interface 1340 may include an antenna or a wired or wireless transceiver. Although it is not shown, the electronic system 1300 may be provided with an application chipset, a camera image processor (CIP), and an input / output device. It is obvious to one.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood that the invention can be variously modified and changed without departing from the technical scope thereof.

10: wafer
100: semiconductor chip
120: penetrating electrode
130: Bump
20:
50: annular reinforcing portion
60: Insulating film

Claims (11)

A plurality of semiconductor chips each having a bonding pad and a penetrating electrode electrically connected to the bonding pad in the chip region of the wafer having a front surface partitioned by a chip region and an outer peripheral region surrounding the chip region, ;
Forming a bump on the bonding pad;
Forming an adhesive member covering the front surface and exposing an upper end of the bump;
Polishing the central portion of the rear surface corresponding to the chip region such that the penetrating electrode is exposed and the annular reinforcing portion remains at the edge of the rear surface;
Etching the rear surface to protrude the penetrating electrode;
Forming an insulating film covering the rear surface and exposing an upper end of the penetrating electrode;
Cutting the wafer to individualize the semiconductor chips; and
Stacking the individual semiconductor chips so that the bumps of the upper semiconductor chip are directly bonded onto the penetrating electrodes of the lower semiconductor chip;
And a second semiconductor package. The method of claim 1, wherein forming the adhesive member comprises:
Applying an adhesive on the front surface including the bumps;
Curing the adhesive; and
And polishing the adhesive to expose the bumps. ≪ RTI ID = 0.0 > 21. < / RTI > The method according to claim 1, further comprising, before the step of polishing the center of the rear surface after the step of forming the adhesive member,
Further comprising laminating a protective tape on the adhesive member including the bumps. The method of manufacturing a semiconductor device according to claim 3, wherein, after the step of forming the insulating film,
Attaching a dicing tape mounted on the wafer ring on the insulating film;
And removing the protective tape from the substrate. ≪ RTI ID = 0.0 > 11. < / RTI > The method of claim 1, wherein etching the rear surface to protrude the penetrating electrode is performed using a chemical mechanical polishing process or a dry etching process. The method of claim 1, wherein forming the insulating layer comprises:
Forming an insulating layer on the rear surface including the protruding penetrating electrode; And
And polishing the insulating layer so that the penetrating electrode is exposed. The method of manufacturing a laminated semiconductor package according to claim 1, wherein the adhesive member comprises a polymer. The method according to claim 1, wherein the insulating film includes at least one selected from the group consisting of a nitride film and an oxide film. 2. The method of claim 1, further comprising removing oxides present on surfaces of the bumps and the penetrating electrodes prior to laminating the semiconductor chips. The method of manufacturing a semiconductor device according to claim 9, wherein the step of removing the oxide is performed using a surface activation treatment process The method according to claim 1, further comprising: after the step of laminating the semiconductor chips, performing an annealing process for strengthening bonding between the bumps and the penetrating electrodes of the stacked semiconductor chips and for strengthening the adhesive force of the adhesive member Wherein said step (c) comprises the steps of:

Images