KR20130123724A - Semiconductor chip stacked structure and method for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor package and, more specifically, to a semiconductor chip stacked structure to facilitate handling of a chip module and a manufacturing method thereof. The semiconductor chip stacked structure according to the present invention includes a storage member having multiple trenches and two or more semiconductor chips stacked in each trench.

Description

Semiconductor chip stack structure and manufacturing method therefor {SEMICONDUCTOR CHIP STACKED STRUCTURE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor chip stack structure and a method of manufacturing the same, which facilitate handling of a chip module.

Electronic devices are becoming smaller and larger in accordance with the development of the semiconductor industry and the needs of users. As one of the technologies mainly applied thereto, a multilayer semiconductor package in which a plurality of semiconductor chips are embedded in one package is known.

However, the conventional laminated semiconductor package has a disadvantage in that the size of the package is increased because an additional area is required for the wire bonding, and in addition, a gap is required for wire bonding to the bonding pads of each chip. There is a disadvantage that the overall height of. Accordingly, a stacked semiconductor package structure using through silicon vias (hereinafter, referred to as 'through electrodes') has been proposed.

Since the stacked semiconductor package using the through-electrode does not need an additional area for electrical connection to the substrate, and also does not need a gap for wire bonding between the semiconductor chips, the overall size and height are reduced compared to the conventional stacked semiconductor package. Can be.

On the other hand, more and more customers are demanding chip modules in which only thin-film semiconductor chips are stacked without a substrate. However, stacking thin semiconductor chips without a substrate is very complicated and difficult. In addition, when handling a chip module in which thin film semiconductor chips are stacked without the substrate, chip cracks may occur or defects in which the semiconductor chips may be detached from each other may occur.

The present invention provides a semiconductor chip stack structure and a method of fabricating the semiconductor chip stack easily without a substrate.

In addition, the present invention provides a semiconductor chip stack structure and a method of manufacturing the chip chip or a semiconductor chip stack structure that can easily handle a chip module stacked semiconductor chips without detachment between each other.

A semiconductor chip stack structure according to an embodiment of the present invention includes a receiving member having a plurality of trenches; And at least two semiconductor chips stacked in each of the trenches.

Each of the stacked semiconductor chips includes a through electrode, and the through electrodes of the stacked semiconductor chips are electrically connected to each other.

The trenches may be arranged in a matrix.

The trench has a size equal to or larger than the size of the semiconductor chip and a depth corresponding to the number of stacked semiconductor chips.

In addition, the semiconductor chip stack structure according to an embodiment of the present invention, the first adhesive member interposed between the lowermost semiconductor chip and the trench bottom surface of the stacked semiconductor chips; And a second adhesive member interposed between the stacked semiconductor chips and different in adhesive strength from the first adhesive member. And further comprising:

The first adhesive member is characterized in that the adhesive force is lost in the temperature range of 200 ~ 300 ℃.

The first adhesive member is characterized in that the adhesive strength is lost by chemical treatment using one or more of acetone, IPA, NMP, PGMEA / PGME and DMSO.

In the method of manufacturing a semiconductor chip stack structure according to an embodiment of the present invention, providing a plurality of wafers having semiconductor chips partitioned by a receiving member and scribe brine, forming a groove in the scribe brine of the plurality of wafers Forming a plurality of trenches in the accommodating member corresponding to the semiconductor chips of the plurality of wafers; and forming the plurality of trenches on the accommodating member such that each semiconductor chip of the wafer is disposed on a bottom surface of each trench of the accommodating member. Attaching one of the wafers of the wafer, backgrinding the wafer until the housing is exposed, thinning a semiconductor chip disposed in the trench, and other of the plurality of wafers on the housing Attaching one wafer to thinning the semiconductor chip disposed in the trench And a step of performing the series repeats.

The groove is characterized in that the width and depth of the groove is formed larger than the protrusion of the receiving member between the trench.

The plurality of trenches may be formed to have a size equal to or larger than the size of the semiconductor chip and a depth corresponding to the number of stacked semiconductor chips.

Furthermore, in the method of manufacturing a semiconductor chip stack structure according to an embodiment of the present invention, after the forming of the plurality of trenches and before attaching the wafer to the receiving member, an adhesive member is formed on the receiving member on which the trench is formed. It characterized in that it further comprises the step of depositing.

The adhesive member may include a first adhesive member interposed between the lowermost semiconductor chip and the trench bottom surface of the stacked semiconductor chips and the stacked semiconductor chips, and a second adhesive member having a different adhesive force from that of the first adhesive member. Characterized in that it comprises a.

According to the present invention, by providing an accommodating member having a trench in which thin film semiconductor chips are to be stacked, and stacking the thin film semiconductor chips in the trench, the semiconductor chips of the thin film can be easily stacked without a substrate.

In addition, the present invention may easily handle a chip module in which thin film semiconductor chips are stacked without detaching chip cracks or semiconductor chips from each other by using the trench-containing storage member as a tray.

1 is a cross-sectional view illustrating a semiconductor chip stack structure in accordance with an embodiment of the present invention.
2 to 7 are cross-sectional views of processes for describing a method of manufacturing a semiconductor chip stack according to an embodiment of the present invention.
8 is a perspective view illustrating an electronic device having a semiconductor package according to the present invention.
9 is a system block diagram of an electronic device to which the semiconductor package according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is a cross-sectional view illustrating a semiconductor chip stack structure in accordance with an embodiment of the present invention.

As shown, the semiconductor chip stack structure 100 includes an accommodating member 10, a chip module 20, and an adhesive member 30.

For example, the storage member 10 may be formed of glass or other silicon (Si) and a material having an etch selectivity close to infinity. The receiving member 10 has a plurality of trenches 12 arranged in a matrix form on an upper surface thereof. Preferably, each of the trenches 12 is disposed at a position corresponding to each of the semiconductor chips at the wafer level.

In the present embodiment, each of the trenches 12 is formed to have a size equal to or larger than the size of the semiconductor chip to be stored, and the depth is determined according to the number of stacked semiconductor chips. For example, when two semiconductor chips 20A and 20B are stacked as in the present exemplary embodiment, the depth of the trench 12 is equal to the thickness of the two semiconductor chips 20A and 20B and the thickness of the adhesive member 30. Let it be depth corresponding to the combined thickness.

The chip module 20 is formed by stacking two semiconductor chips 20A and 20B, that is, a first semiconductor chip 20A and a second semiconductor chip 20B, in each trench 12. Here, the number of semiconductor chips stacked in each trench 12 may be not only two, but more than two, like the first semiconductor chip 20A and the second semiconductor chip 20B.

Each of the first semiconductor chip 20A and the second semiconductor chip 20B is a thin film, and although not shown, includes a circuit portion and a through electrode formed therein. The circuit unit includes a circuit that operates by receiving external power and a signal, for example, a data storage unit for storing data, a data processing unit for processing data, and the like. The through electrode is formed to penetrate the upper and lower surfaces of the first semiconductor chip 20A and the second semiconductor chip 20B, and is connected to the circuit unit.

The through electrodes of the first semiconductor chip 20A and the through electrodes of the second semiconductor chip 20B stacked on the trenches 12 are electrically connected to each other.

The adhesive member 30 may include a first adhesive member 30A interposed between the first semiconductor chip 20A, which is a lowermost semiconductor chip in the chip module 20, and a bottom surface of the trench 12, and the first semiconductor chip. And a second adhesive member 30B interposed between the 20A and the second semiconductor chip 20B.

In the present embodiment, the first adhesive member 30A and the second adhesive member 30B have different adhesive strengths. For example, a thermoplastic material may be used as the first adhesive member 30A, and a thermosetting material may be used as the second adhesive member 30B, and the first adhesive member 30A may be in a temperature range of 200 to 300 ° C. ), The adhesive force is lost, but the second adhesive member 30B does not lose the adhesive force. Alternatively, with respect to chemicals such as acetone, IPA, PGMEA, etc., the first adhesive member 30A loses its adhesive force, but the second adhesive member 30B does not lose its adhesive force. In addition, the adhesive force of the first adhesive member 30A is also lost by ultraviolet rays, lasers, heat treatment, solvents, and the like.

Therefore, the chip module 20 accommodated by the first adhesive member 30A in each trench 12 is subjected to a chemical treatment such as acetone, IPA, PGMEA, or the like by applying a temperature of 200 to 300 ° C. Through the adhesive force of the first adhesive member (30A) is lost can be detached from the receiving member (10).

As described above, the semiconductor chip stack structure according to the embodiment of the present invention can easily manufacture a chip module in which only semiconductor chips are stacked without using a substrate by using an accommodation member provided with a trench. By using the trench-formed storage member as a tray for providing only the chip module to the customer, it is possible to prevent cracking of the semiconductor chip or detachment between the semiconductor chips, which may be caused in the process of handling the chip module manufactured without the substrate. As a result, it is possible to reliably provide a chip module configured by stacking only chips having through electrodes to a customer.

2 to 7 are cross-sectional views of processes for describing a method of manufacturing a semiconductor chip stack according to an embodiment of the present invention.

Referring to FIG. 2, the accommodating member 10 and a known semiconductor manufacturing process are completed, and a first wafer 51 having a through electrode (not shown) is formed on each first semiconductor chip at the wafer level. For example, glass or other silicon and a material close to infinity of an etch selectivity may be used as the housing member 10, and the housing member 10 may have a size equal to or larger than that of the first wafer 51. The first wafer 51 is divided by a scribe lane S / L and includes a plurality of semiconductor chips having the same circuit portion.

Here, the circuit unit includes a circuit that operates by receiving an external power and signal, for example, a data storage unit for storing data, a data processing unit for processing data, and the like. The through electrode is formed to penetrate the upper and lower surfaces of each first semiconductor chip, and is connected to the circuit unit.

Scribine S / L of the first wafer 51 is partially sawed to form a first groove H1. Subsequently, portions of the receiving member 10 are selectively etched to form a plurality of trenches 12.

In the process of forming the first groove H1 in the scribe brine S / L of the first wafer 51, the width W and the depth D of the first groove H1 are defined in the housing member. It is preferred to be larger than the projections 14 between the trenches 12 in 10.

In the process of forming the trench 12, the trenches 12 are received corresponding to each of the first semiconductor chips so that each of the first semiconductor chips of the first wafer 51 can be seated on the bottom surface thereof. Part of the member 10 is selectively etched to form it. In addition, each of the trenches 12 is formed to have a size equal to or larger than that of the first semiconductor chip, and the depth D2 is determined according to the number of stacked semiconductor chips.

Meanwhile, the partial sawing of the first wafer 51 and the trench etching of the accommodating member 10 may be reversed.

Referring to FIG. 3, after applying the first adhesive member 30A on the receiving member 10 in which the trench 12 is formed in the matrix form, the first wafer 51 on the receiving member 10. Is attached as a face-down type. In this case, the protrusions 14 of the accommodating member 10 are inserted into the respective first grooves H of the first wafer 51, so that each of the first semiconductor chips of the first wafer 51 may be It is arranged on the bottom surface of the corresponding trench 12 of the receiving member 10.

Here, the first adhesive member 30A, a thermoplastic material may be used as an example, the first adhesive member 30A is lost in the adhesive force in the temperature range of 200 ~ 300 ℃ or acetone, IPA, PGMEA The adhesive force is lost in response to chemicals such as and the like. In addition, the adhesive force of the first adhesive member 30A is also lost by ultraviolet rays, lasers, heat treatment, solvents, and the like.

Referring to FIG. 4, the first wafer 51 is back ground until the protrusion 14 of the accommodating member 10 is exposed. At this time, the portion of the first adhesive member 30A applied on the protrusion 14 of the housing member 10 is removed together, and thus, in the trench 12 of the housing member 10 as a result of the backgrinding. Only the first semiconductor chip 20A remains.

Referring to FIG. 5, a part of the thickness of the first semiconductor chip 20A disposed in the trench 12 is dry-etched, and through this, the first semiconductor chip 20A attached to each trench 12 is thinned. . Here, the dry etching is performed until the first semiconductor chip 20A having a desired thickness is obtained.

Referring to FIG. 6, similar to the first wafer 51 including the plurality of first semiconductor chips 20A, a known semiconductor manufacturing process is completed and a through electrode is formed on each second semiconductor chip at the wafer level. 2 wafer 53 is prepared. Then, the second wafer 53 is formed in the scribe brine S / L of the second wafer H2 in the same manner as the first wafer 51. Here, in the step of forming the second groove H2 in the scribe brine S / L of the second wafer 53, the second groove H2 is the scribe brine of the first wafer 51. Compared with the first groove H1 formed in S / L, the width of the first semiconductor chip 20A having the same width but depth is preferably shallower.

Subsequently, after the second adhesive member 30B is applied to the entire surface including the first semiconductor chip 20A attached to each of the trenches 12, the respective trenches 12 may be subjected to a general selective etching process such as using a photosensitive film. The second adhesive member 30B on the through electrode of the first semiconductor chip 20A attached therein is selectively etched and removed.

Thereafter, the second wafer 53 is attached to the accommodating member 10 in the face-down type in the same manner as the first wafer 51. In this case, each second semiconductor chip 20B of the second wafer 53 is attached to the first semiconductor chip 20A, respectively. The second groove H2 formed in the scribe brine S / L of the second wafer 53 is formed in the scribe brine S / L of the first wafer 51 and the first groove H1 formed therein. Since the widths are the same, when each second semiconductor chip of the second wafer 53 is attached onto the first semiconductor chip 20A, the second adhesive member 30B applied to the sidewall of the trench 12, respectively. Is moved to the second adhesive member 30B coated on the first semiconductor chip 20A together with the second semiconductor chip, and the first adhesive member (3) is not formed on the sidewall of the trench 12 without the second adhesive member 30B. Only 30A) remains. In addition, the through electrodes of the second semiconductor chips of the second wafer 53 are electrically connected to the through electrodes of the first semiconductor chip 20A exposed by the selective etching process of the second adhesive member 30B. .

In the present exemplary embodiment, a material having a different adhesive force from that of the first adhesive member 30A may be used for the second adhesive member 30B. For example, a thermosetting material may be used for the second adhesive member 30B, and such a material does not lose its adhesive strength even in a temperature range of 200 to 300 ° C., and also for chemicals such as acetone, IPA, and PGMEA. The adhesion is not lost.

Referring to FIG. 7, the second wafer 53 is back ground until the protrusion 14 of the accommodating member 10 is exposed. At this time, the portion of the second adhesive member 30B applied on the protrusion 14 of the accommodating member 10 is removed together, so that the trench above each of the first semiconductor chips 20A is formed as a result of the backgrinding. The second semiconductor chip 20B remains only in the region 12.

Then, although not shown in detail, by dry etching a part of the thickness of the second semiconductor chip (20B), thereby thinning each of the second semiconductor chip (20B) remaining on the first semiconductor chip (20A), Accordingly, the semiconductor chip stack according to the embodiment of the present invention, in which the chip module 20 configured by stacking the first and second semiconductor chips 20A and 20B is stacked in each trench 12 of the housing member 10. Complete the manufacture of the structure 100.

Here, the dry etching process is performed under the condition that the housing member 10 is not lost, similarly to the etching conditions of the first semiconductor chip 20A.

In the present embodiment, as described above, the two wafers are attached, back-grinded, and thinned, but the two trenches 12 are repeatedly formed by the method described above. A plurality of semiconductor chips can be stacked in the thermosetting material.

Meanwhile, since the first adhesive member 30A may have a material having a different adhesive force from that of the second adhesive member 30B, for example, the first adhesive member 30A may use a thermoplastic material. In addition, since these materials lose their adhesion in the temperature range of 200 to 300 ° C., and also lose their adhesion in response to chemicals such as acetone, IPA, PGMEA, etc., the first, The second semiconductor chips 20A and 20B lose the adhesive force of the first adhesive member 30A by applying a temperature of 200 to 300 ° C. or through a chemical treatment such as acetone, IPA, PGMEA, or the like. It can be detached from (10).

In the method for manufacturing a semiconductor chip stack structure according to the embodiment of the present invention described above, by using an accommodating member provided with a trench, a chip module in which only semiconductor chips are stacked can be reliably manufactured without using a substrate. By using the trench-formed storage member as a tray for providing only the chip module to the customer, it is possible to prevent cracking of the semiconductor chip or detachment between the semiconductor chips, which may be caused in the process of handling the chip module manufactured without the substrate. As a result, it is possible to reliably provide a chip module configured by stacking only chips having through electrodes to a customer.

The semiconductor package described above may be applied to various package modules.

8 is a perspective view illustrating an electronic device having a semiconductor package according to an embodiment of the present disclosure.

As illustrated, the multilayer semiconductor package according to an embodiment of the present invention may be applied to an electronic device 1000 such as a mobile phone. Since the semiconductor package according to the present exemplary embodiment is excellent in terms of size reduction and electrical characteristics, it is advantageous to reduce the thickness of the electronic device 1000 that simultaneously implements various functions. The electronic device is not limited to the mobile phone shown in Fig. 8, but may be a portable electronic device, a laptop computer, a portable computer, a portable multimedia player (PMP), an MP3 player, a camcorder, a web tablet ), A wireless telephone, a navigation system, a personal digital assistant (PDA), and the like.

9 is a block diagram illustrating an example of an electronic device including a semiconductor package according to the present invention.

As shown, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a memory device 1330. The controller 1310, the input / output device 1320, and the memory device 1330 may be coupled through a bus 1350. The bus 1350 may be a path through which data flows. For example, the controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing the same functions. The controller 1310 and the memory device 1330 may include a semiconductor package according to the present invention. The input / output device 1320 may include at least one selected from a keypad, a keyboard, and a display device. The storage device 1330 is a device for storing data. The storage device 1330 may store data and / or instructions that may be executed by the controller 1310. The storage device 1330 may include a volatile storage element and / or a non-volatile storage element. Alternatively, the storage device 1330 may be formed of a flash memory. For example, a flash memory to which the technique of the present invention is applied can be mounted on an information processing system such as a mobile device or a desktop computer. Such a flash memory may consist of a semiconductor disk device (SSD). In this case, the electronic system 1300 can stably store a large amount of data in the flash memory system. The electronic system 1300 may further include an interface 1340 for transferring data to or receiving data from the communication network. The interface 1340 may be in a wired or wireless form. For example, the interface 1340 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1300 may be further provided with an application chip set, a camera image processor (CIS), and an input / output device. Self-explanatory to those who have learned.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawing.

10: housing member 12: trench
20: chip module 30: adhesive member

Claims (14)

A housing member having a plurality of trenches; And
At least two semiconductor chips stacked in each of the trenches;
Semiconductor chip stack structure including. The method of claim 1,
Each of the stacked semiconductor chips includes a through electrode, and the through electrodes of the stacked semiconductor chips are electrically connected to each other. The method of claim 1,
The trench is a semiconductor chip stack, characterized in that arranged in the form of a matrix. The method of claim 1,
The trench has a semiconductor chip stack structure having a size equal to or larger than the size of the semiconductor chip and a depth corresponding to the number of stacked semiconductor chips. The method of claim 1,
A first adhesive member interposed between a lowermost semiconductor chip and the trench bottom surface of the stacked semiconductor chips; And
A second adhesive member interposed between the stacked semiconductor chips and different in adhesive strength from the first adhesive member; The semiconductor chip stack structure further comprising. The method of claim 5, wherein
The first adhesive member has a semiconductor chip stack structure, characterized in that the adhesive force is lost in the temperature range of 200 ~ 300 ℃. The method of claim 5, wherein
The first adhesive member is characterized in that the adhesive strength is lost by the chemical treatment using one or more of acetone, IPA, NMP, PGMEA / PGME and DMSO. Providing a plurality of wafers having semiconductor chips partitioned by a housing member and a scribe line;
Forming grooves in the scribe brains of the plurality of wafers;
Forming a plurality of trenches in the housing member corresponding to the semiconductor chips of the plurality of wafers;
Attaching one wafer of the plurality of wafers onto the housing member such that each semiconductor chip of the wafer is disposed on a bottom surface of each trench of the housing member;
Backgrinding the wafer until the housing is exposed;
Thinning the semiconductor chip disposed in the trench; And
Repeatedly attaching one of the plurality of wafers to the receiving member to thinning the semiconductor chip disposed in the trench;
Method of manufacturing a semiconductor chip laminated structure comprising a. The method of claim 8,
And the groove is formed to have a width and a depth greater than a protrusion of the accommodation member between the trenches. The method of claim 8,
And forming a plurality of trenches having a size equal to or larger than the size of the semiconductor chip and a depth corresponding to the number of stacked semiconductor chips. The method of claim 8,
Fabricating a semiconductor chip stack structure after the forming of the plurality of trenches, before depositing the wafer on the receiving member, depositing an adhesive member on the receiving member on which the trench is formed. Way. The method of claim 11,
The adhesive member may include a first adhesive member interposed between the lowermost semiconductor chip and the trench bottom surface of the stacked semiconductor chips and the stacked semiconductor chips, and a second adhesive member having a different adhesive force from that of the first adhesive member. Method of manufacturing a semiconductor chip laminate structure comprising a. 13. The method of claim 12,
The first adhesive member is a method for manufacturing a semiconductor chip stack structure, characterized in that the adhesive force is lost in the temperature range of 200 ~ 300 ℃. 13. The method of claim 12,
The first adhesive member has a characteristic that the adhesive force is lost by a chemical treatment using one or more of acetone, IPA, NMP, PGMEA / PGME and DMSO has a characteristic that the adhesive force is lost.

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