KR20140110230A - Solar cell and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a solar cell and a manufacturing method thereof. The solar cell according to the embodiment of the present invention includes a substrate which includes a first surface with a first uneven part and a second surface with a second uneven part which is different from the first uneven part, an impurity layer which is formed on the substrate, and an electrode which is connected to the impurity layer.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell with improved structure and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

The solar cell may be formed by forming a conductive region and an electrode electrically connected to the conductive region on the semiconductor substrate so as to cause photoelectric conversion. In order to improve the efficiency of a solar cell, a technique of forming irregularities by texturing the surface of a semiconductor substrate has been proposed.

As described above, the surface of the semiconductor substrate can be reduced in surface reflectivity by forming irregularities by texturing. However, when the same texture is formed on the rear surface and the same irregularities are formed, a large number of defects may occur and the passivation characteristics of the rear surface may be deteriorated. As a result, the surface reflectivity of the front surface is lowered by unevenness, and the passivation property of the rear surface is lowered, so that the efficiency can not be greatly improved.

The present invention aims at providing a solar cell having excellent efficiency and high productivity and a manufacturing method thereof.

A solar cell according to an embodiment of the present invention includes: a substrate having a first surface having first irregularities and a second surface having second irregularities different from the first irregularities; An impurity layer formed on the substrate; And an electrode connected to the impurity layer.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: preparing a substrate; A first texturing step of forming first irregularities on a first surface and a second surface of the substrate; A second texturing step of forming second irregularities on the second surface of the substrate different from the first irregularities; Forming an impurity layer on the substrate; And forming an electrode electrically connected to the impurity layer.

According to the solar cell of the present embodiment, first irregularities are formed on both surfaces of the semiconductor substrate by an easy and simple process by first texturing using wet etching, and then, Only the end portions of the irregularities are etched to form the second irregularities. Thus, by the simple process, the first concavo-convex portion having a sharp end and the high aspect ratio can be formed on the front surface of the semiconductor substrate, and the second concavo-convex portion having the rounded end portion and the low aspect ratio can be formed on the rear surface. The first irregularities and the second irregularities having such different shapes can improve the optical properties and the passivation properties, respectively, and consequently improve the efficiency of the solar cell.

That is, according to the present invention, a solar cell having excellent efficiency can be produced with high productivity.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
FIG. 2 is a perspective view illustrating first and second irregularities of a solar cell according to an embodiment of the present invention. FIG.
3 is a plan view of the solar cell shown in Fig.
4 is a flowchart of a method of manufacturing a solar cell according to an embodiment of the present invention.
5A to 5F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
6 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
7 is a front view of the semiconductor substrate after the second texturing is completed in the experimental example of the present invention.
8 is a rear view of the semiconductor substrate after the second texturing is completed in the experimental example of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention, and FIG. 2 is a perspective view illustrating first and second irregularities of a solar cell according to an embodiment of the present invention. And FIG. 3 is a plan view of the solar cell shown in FIG.

1, a solar cell 100 according to the present embodiment includes a substrate (e.g., a semiconductor substrate) (hereinafter, referred to as a "semiconductor substrate") 110, an impurity layer 20 30 and electrodes 24, 34 electrically connected to the impurity layers 20, 30. The impurity layers 20 and 30 may include an emitter layer 20 and a back front layer 30 and the electrodes 24 and 34 may include a first electrode 24 electrically connected to the emitter layer 20, And a second electrode 34 electrically connected to the rear front layer 30. In addition, the solar cell 100 may further include an antireflection film 22, a passivation film 32, and the like. This will be explained in more detail.

The semiconductor substrate 110 includes a region in which the impurity layers 20 and 30 are formed and a base region 10 in which the impurity layers 20 and 30 are not formed. The base region 10 may comprise, for example, silicon containing a second conductivity type impurity. As the silicon, single crystal silicon or polycrystalline silicon may be used, and the second conductivity type impurity may be n-type, for example. That is, the base region 10 may be formed of single crystal or polycrystalline silicon doped with Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb)

When the base region 10 having the n-type impurity is used as described above, the emitter layer 20 having p-type impurities is formed on the first surface (hereinafter referred to as "front surface") of the semiconductor substrate 110, (20) and the basesurface (10) form a pn junction. When the pn junction is irradiated with light, electrons generated by the photoelectric effect move toward the second surface (hereinafter referred to as "back surface") of the semiconductor substrate 110 and are collected by the second electrode 34, 110 and collected by the first electrode 24. Thereby, electric energy is generated. In this case, a hole having a slower moving speed than the electron moves to the front surface of the semiconductor substrate 110, not the rear surface, so that the conversion efficiency can be improved.

However, the present invention is not limited thereto, and it goes without saying that the base region 10 and the rear front layer 30 may have a p-type and the emitter layer 20 may have an n-type.

In this embodiment, the front surface and the rear surface of the semiconductor substrate 110 have concave and convex portions 112 and 114 formed by texturing. In this embodiment, the front surface and the rear surface of the semiconductor substrate 110 satisfy the respective required characteristics The first irregularities 112 on the front surface and the second irregularities 114 on the rear surface have different shapes. This will be described in more detail with reference to FIG.

2 (a) is a perspective view showing the first unevenness 112, and FIG. 2 (b) is a perspective view showing the second unevenness 114. FIG. 2 (b), for the sake of clarity, the end of the second concavity and convexity 114 is positioned at the upper side, as opposed to the first embodiment. 2 (a), the end of the first concavity and convexity 112 is located at the upper portion, as in FIG.

2, the first irregularities 112 formed on the front surface of the semiconductor substrate 110 are formed to have sharp ends, and the second irregularities 114 formed on the rear surface of the semiconductor substrate 110 are formed in a manner Is rounded.

More specifically, the first irregularities 112 are irregularities in which specific surfaces of the semiconductor substrate 110 are etched so as to have the directionality of the material constituting the semiconductor substrate 110 (i.e., anisotropically). For example, when the material constituting the semiconductor substrate 110 is silicon, the (111) surface of silicon constitutes the four side surfaces of the first concavity and convexity 112, and the first concavity and convexity 112 forms the pyramid shape I have. The end portion of the first concavity and convexity 112 is formed as a point where four (111) planes gather.

For example, the average height H1 of the first irregularities 112 may be 10 to 15 占 퐉. If the average height H1 of the first irregularities 112 exceeds 15 mu m, defects may increase at the front surface of the semiconductor substrate 110. If the average height H1 is less than 10 mu m, the reflectance of the semiconductor substrate 110 may be increased. The cross section of the first concavity and convexity 112 has an isosceles triangle and the angle A1 of the end portion of the first concavity and convexity 112 in the isosceles triangle may be approximately 65 to 85 degrees (for example, approximately 72 degrees). The angle A1 of the cross-sectional shape and the end portion is due to the characteristics of the material constituting the semiconductor substrate 110. [

However, the present invention is not limited thereto. Therefore, the average height H1 of the first concave and convex portions 112 and the angle A1 of the end portions may be variously changed according to the size of the solar cell 100, the material of the semiconductor substrate 110, and the like.

The second irregularities 114 are irregularities formed so as to have rounded ends formed by isotropically etching the ends of the pointed first irregularities 112. That is, the second concave and convex portions 114 are formed such that four (111) planes are formed on sides and an end portion thereof is rounded. For example, the second concavities and convexities 114 may have a rounded pyramid shape. Accordingly, the second irregularities 114 have a lower height than the first irregularities 112, and the surface area becomes smaller.

For example, the average height H2 of the second irregularities 114 may be less than the average height H1 of the first irregularities 112 as 5 to 12 占 퐉. If the average height H2 of the second concave and convexes 114 exceeds 12 占 퐉, the ends of the first concavities and convexities 112 are not sufficiently removed and the defects can not be sufficiently reduced. If the average height H2 is less than 5 占 퐉, . At this time, the ratio (H2 / H1) of the average height H2 of the second concave and convexities 114 to the average height H1 of the first concavities and convexities 112 may be 0.6 to 0.9.

The radius of curvature R at the end of the second concavity and convexity 114 may be, for example, about 1.25 to 3 탆. The radius of curvature R at the end of the second concavity and convexity 112 is limited to such an extent as to reduce defects in the second concavity and convexity 114 and to prevent damage to the semiconductor substrate 110. [

However, the present invention is not limited thereto. Therefore, the average height H2 of the second concave and convexities 114, the height ratio H2 / H1 and the radius of curvature R at the end of the second concavo-convex 114 are determined according to the standard of the solar cell 100, 1 and the shape of the second concavities and convexities 112, 114, and the like.

In this embodiment, the side surface of the second concavity and convexity 114 is formed of four inclined planes (i.e., (111) planes) and the end is rounded. However, the present invention is not limited to this, and the second concavities and convexities 114 may be rounded as a whole.

As described above, in the present embodiment, the first irregularities 112 located on the front surface, which is the light receiving surface, have a relatively high aspect ratio, thereby sufficiently reducing the reflectivity. Accordingly, the amount of light reaching the pn junction of the solar cell 100 can be increased. As a result, the threshold current Isc of the solar cell 100 can be increased. In addition, the second concavities and convexities 112 located on the rear surface may be rounded to remove a portion having a large number of defects, and the surface area may be reduced. Accordingly, it is possible to increase the open-circuit voltage (Voc) of the solar cell 100 by improving the passivation property on the rear surface of the semiconductor substrate 110. [

As described above, the first irregularities 112 and the second irregularities 114 have different shapes, so that the first irregularities 112 have a shape capable of improving optical characteristics, and the second irregularities 114 have a rear passivation characteristic Can be improved. As a result, both the optical characteristics and the back passivation characteristics are improved, so that the open-circuit voltage and the short-circuit current can be increased together. As a result, the efficiency of the solar cell 100 can be greatly improved.

The process of manufacturing the first irregularities 112 and the second irregularities 114 will be described later in detail with reference to FIG. 4 and FIGS. 5A through 5F.

An emitter layer 20 having a first conductivity type impurity may be formed on the front surface of the semiconductor substrate 110. In the present embodiment, the emitter layer 20 is a first conductivity type impurity, and a p-type impurity such as boron (B), aluminum (Al), gallium (Ga), or indium (In) as a Group III element can be used.

In this embodiment, the emitter layer 20 includes a first portion 20a having a high impurity concentration and a relatively low resistance, a first portion 20b having a lower impurity concentration than the first portion 20a and having a relatively high resistance And may have a second portion 20b. The first portion 20a is formed to be in contact with a part or all (i.e., at least a part of) the first electrode 24.

 As described above, in the present embodiment, a second portion 20b having a relatively high resistance is formed at a portion corresponding to a portion between the first electrodes 24 to which light is incident, thereby implementing a shallow emitter. Thus, the current density of the solar cell 100 can be improved. In addition, it is possible to reduce the contact resistance with the first electrode 24 by forming the first portion 20a having a relatively low resistance at the portion adjacent to the first electrode 24. [ That is, the emitter layer 20 of this embodiment can maximize the efficiency of the solar cell 100 by the selective emitter structure.

However, the present invention is not limited thereto, and the emitter layer 20 may have a homogeneous emitter structure having a uniform doping concentration. In this embodiment, the emitter layer 20 is formed only on the front surface of the semiconductor substrate 110, but the present invention is not limited thereto. That is, the emitter layer 20 may extend to the backside, and the solar cell 100 may have a rear electrode structure.

The anti-reflection film 22 and the first electrode 24 are formed on the semiconductor substrate 110, more precisely on the emitter layer 20 formed on the semiconductor substrate 110.

The antireflection film 22 may be formed substantially entirely on the entire surface of the semiconductor substrate 110 except for the portion where the first electrode 24 is formed. The antireflection film 22 reduces the reflectance of light incident on the front surface of the semiconductor substrate 110 and immobilizes defects present in the surface or bulk of the emitter layer 20. [

The amount of light reaching the pn junction formed at the interface between the base portion 10 and the emitter layer 20 can be increased by lowering the reflectance of the light incident through the front surface of the semiconductor substrate 110. Accordingly, the short circuit current of the solar cell 100 can be increased. The defect in the emitter layer 20 may be passivated to remove recombination sites of the minority carriers, thereby increasing the open-circuit voltage of the solar cell 100. The efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 with the anti-reflection film 22.

The anti-radiation film 22 may be formed of various materials. For example, the antireflection film 22 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , Layer structure having a combination of at least two layers. However, the present invention is not limited thereto, and it goes without saying that the anti-reflection film 22 may include various materials. Further, a front passivation film (not shown) may be further provided between the semiconductor substrate 110 and the antireflection film 22 for passivation. Are also within the scope of the present invention.

The first electrode 24 is electrically connected to the emitter layer 20 through an opening formed in the antireflection film 22 (i.e., through the antireflection film 22). The first electrode 24 may be formed to have various shapes, which will be described with reference to FIG.

A rear front layer 30 including a second conductive impurity at a higher doping concentration than the semiconductor substrate 110 is formed on the rear side of the semiconductor substrate 110. In the present embodiment, the rear front layer 30 may be an n-type impurity such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) which are Group 5 elements as the second conductive impurities.

In this embodiment, the rear front layer 30 has a first portion 30a having a high impurity concentration and a relatively low resistance and a second portion 30b having a relatively high impurity concentration and having a lower impurity concentration than the first portion 30a And may have a second portion 30b. The first portion 30a is formed to be in contact with a part or all (i.e., at least a part of) the first electrode 34. [

As described above, in this embodiment, the second portion 30b having a relatively high resistance is formed at the portion corresponding to the space between the second electrodes 34, so that recombination of holes and electrons can be prevented. Thus, the current density of the solar cell 100 can be improved. In addition, it is possible to reduce the contact resistance with the second electrode 34 by forming a first portion 30a having a relatively low resistance at a portion adjacent to the second electrode 34. [ That is, the rear front layer 30 of the present embodiment can maximize the efficiency of the solar cell 100 by the selective rear field structure.

However, the present invention is not limited thereto, and the rear front layer 30 may have a homogeneous back surface field structure having a uniform doping concentration. Alternatively, the backside front layer 30 may have a local back surface field structure formed locally only at a portion adjacent to the second electrode 34 at the rear surface of the semiconductor substrate 110. [

 In addition, a passivation film 32 and a second electrode 34 may be formed on the rear surface of the semiconductor substrate 110.

The passivation film 32 may be formed substantially on the entire rear surface of the semiconductor substrate 110 except for the portion where the second electrode 34 is formed. This passivation film 32 can pass the defects present on the back surface of the semiconductor substrate 110 to remove recombination sites of the minority carriers. Accordingly, the open-circuit voltage of the solar cell 100 can be increased.

The passivation film 32 may be made of a transparent insulating material so that light can be transmitted. Therefore, light can be incident on the rear surface of the semiconductor substrate 110 through the passivation film 32, thereby improving the efficiency of the solar cell 100. For example, the passivation film 32 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO _2, and CeO ₂ , Layer structure having a combination of at least two layers. However, the present invention is not limited thereto, and it goes without saying that the passivation film 32 may include various materials.

The second electrode 34 is electrically connected to the rear front layer 30 through an opening formed in the passivation film 32 (i.e., through the passivation film 32). The second electrode 34 may be formed to have various shapes. That is, the first electrode 24 and / or the second electrode 34 according to the present embodiment may have various planar shapes, and an example thereof will be described with reference to FIG. Although the first electrode 24 and the second electrode 34 may have different widths, pitches, and the like, their basic shapes may be similar. Accordingly, the first electrode 24 will be mainly described in FIG. 3, and the description of the second electrode 34 will be omitted. The following description can be applied to the first and second electrodes 24 and 34 in common.

Referring to FIG. 3, the first electrode 24 may include a plurality of finger electrodes 24a having a first pitch P1 and disposed in parallel with each other. In addition, the electrode 24 may include a bus bar electrode 24b formed in a direction crossing the finger electrodes 24a and connecting the finger electrodes 24a. Only one bus electrode 24b may be provided or a plurality of bus electrodes 24b may be provided with a second pitch P2 larger than the first pitch P1 as shown in FIG. At this time, the width W2 of the bus bar electrode 24b may be larger than the width W1 of the finger electrode 24a, but the present invention is not limited thereto and may have the same width. The shape of the first electrode 24 described above is merely an example, and the present invention is not limited thereto.

The finger electrode 24a and the bus bar electrode 24b both may be formed to penetrate through the antireflection film 22 (the passivation film 32 in the case of the second electrode 34, hereinafter the same) have. Alternatively, the finger electrode 24a may pass through the antireflection film 22 and the bus bar electrode 24b may be formed on the antireflection film 22.

As described above, in the solar cell 100 according to the present embodiment, the first irregularities 112 formed on the front surface of the semiconductor substrate 110 and the second irregularities 114 formed on the rear surface are formed in different shapes The optical characteristics on the front surface and the passivation characteristics on the rear surface can be improved at the same time.

The manufacturing process of the first irregularities 112 and the second irregularities 114 will be described below in more detail with reference to FIG. 4 and FIGS. 5A through 5F. For the sake of simplicity and clarity, the detailed description will be omitted for the parts already described and the details not described will be described below.

FIG. 4 is a flow chart of a method of manufacturing a solar cell according to an embodiment of the present invention, and FIGS. 5A to 5F are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

Referring to FIG. 4, a method of manufacturing a solar cell according to an embodiment of the present invention includes a step ST10 of preparing a substrate, a step ST20 of performing a first texturing, a step ST30 of performing a second texturing, A step ST40 of forming an antireflection film and a passivation film, and a step ST60 of forming an electrode.

First, as shown in FIG. 5A, a semiconductor substrate 110 having a second conductivity type impurity is prepared in a step ST10 of preparing a substrate.

Next, as shown in FIG. 5B, in the first texturing step ST20, first irregularities 112 having sharp ends are formed on the front and back surfaces of the semiconductor substrate 110 by the first texturing. For example, wet etching may be used to immerse the semiconductor substrate 110 in the etching solution with a first texturing. Such wet etching has advantages of short process time and simple process.

According to the wet etching, the semiconductor substrate 110 is etched in an anisotropic manner to remain on a specific surface ((111) surface when the semiconductor substrate 110 includes silicon). Accordingly, the first irregularities 112 may have a pyramid shape with four (111) faces forming side faces and having sharp ends.

As the wet solution, an alkali solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) may be used. However, the present invention is not limited thereto, and specific process conditions of the wet solution, the wet etching, the specific shape of the first concavity and convexity 112 and the like can be variously modified.

Next, as shown in FIG. 5C, in the second texturing step ST30, a second unevenness 114 is formed on the rear surface of the semiconductor substrate 110 by the second texturing. That is, the second concavities and convexities 114 are formed by changing the concavo-convex shape of the rear surface of the semiconductor substrate 110 by cross-sectional etching. At this time, dry etching is performed by the second texturing so that the isotropic etching is performed.

As an example, reactive ion etching (RIE) may be used for the second texturing. The reactive ion etching accelerates the ions in the plasma and uses the chemical reaction and the kinetic energy of the ions to etch them, so that fine irregularities can be uniformly formed. At this time, a single hexafluoride (SF ₆ ) gas may be used as the reactant gas to more effectively round the end portion of the first concavity and convexity 112. That is, when the hexafluoride gas is used singly, the material (for example, silicon) constituting the semiconductor substrate 110 has a radius of 2 to 3 angstroms, (For example, 5 to 6 ANGSTROM for silicon). Accordingly, the pointed ends of the first irregularities 112 can be etched and rounded by the isotropic etching characteristics. As a result, the second unevenness 114 is formed.

The process conditions of the reactive ion etching can be variously modified. For example, reactive ion etching can be performed by injecting sulfur hexafluoride gas at a rate of 2000 to 6000 sccm into a chamber having a power of 1000 to 2000 W and a pressure of 200 to 500 mTorr and holding the chamber for 2 to 10 minutes. Such power, pressure, gas injection rate, process time, etc. are shown in a range suitable for rounding the sharp end of the first concavity and convexity 112. However, the present invention is not limited thereto. Therefore, the power, the pressure, the gas injection rate, the process time, and the like are calculated in consideration of the type of the semiconductor substrate 110, the size of the first concavities and convexities 112, the size of the chamber, the radius of curvature at the end of the second concavo- Can be variously modified.

Next, as shown in FIG. 5D, an impurity layer (emitter layer) 20 and a rear front layer 30 are formed in a step (ST40) of forming an impurity layer. A portion where the emitter layer 20 and the rear front layer 30 are not formed constitutes the base portion 10.

Here, the emitter layer 20 may be formed by doping the first conductive impurity on the entire surface of the semiconductor substrate 110 by various methods such as ion implantation and thermal diffusion. Similarly, the rear front layer 30 may be formed by doping the second conductive impurity on the rear surface of the semiconductor substrate 110 by various methods such as ion implantation, thermal diffusion, or the like. Although both the emitter layer 20 and the rear front layer 30 are formed in the step of forming the impurity layer in the figure, only the emitter layer 20 may be formed and the rear front layer 30 may be formed later Do.

The emitter layer 20 and the rear whole layer 30 having a selective structure as in this embodiment can be formed by various methods such as using a comb mask or performing a plurality of doping. The present invention is not limited to the method of forming the emitter layer 20 and the back front layer 30.

5E, the antireflection film 22 and the passivation film 32 are formed on the front surface and the rear surface of the semiconductor substrate 110, respectively, in the step of forming the antireflection film and the passivation film (ST50). The antireflection film 22 and the passivation film 32 may be formed by various methods such as a vacuum evaporation method, a chemical vapor deposition method, a spin coating method, a screen printing method or a spray coating method.

5F, in the step of forming the electrode (ST60), the first electrode 24 which is in contact with the emitter layer 20 is formed on the entire surface of the semiconductor substrate 110, and the semiconductor substrate 110 The second electrode 34 contacting the rear front layer 30 is formed.

The first electrode 24 may be formed in various ways such as a plating method, a deposition method, or the like, in the opening portion of the antireflection film 22. Then, an opening is formed in the passivation film 32, and the second electrode 34 can be formed in this opening by various methods such as a plating method and a vapor deposition method.

Alternatively, the first and second electrode formation paste may be applied on the antireflection film 22 and the passivation film 32 by screen printing or the like, and then fire through or laser firing contact may be performed It is possible to form the first and second electrodes 24 and 34 having the above-described shape. In this case, it is not necessary to carry out the step of forming the opening separately.

The emitter layer 20 and the rear front layer 30 are formed and then the antireflection film 22 and the passivation film 32 are formed in the above embodiment and then the first and second electrodes 24, and 34 are formed. However, the present invention is not limited thereto. Therefore, the order of forming the emitter layer 20, the backside front layer 30, the antireflection film 22, the passivation film 32, the first electrode 24, and the second electrode 34 can be variously modified .

According to the method of manufacturing the solar cell 100 according to the present embodiment, first irregularities 112 are formed on both surfaces of the semiconductor substrate 110 by a simple and simple process by first texturing using wet etching, The second concave and convex portions 114 are formed by etching only the end portions of the first concave and convex portions 112 formed on the rear surface of the semiconductor substrate 110 by texturing. Thus, by a simple process, first irregularities 112 having sharp edges and high aspect ratios are formed on the entire surface of the semiconductor substrate 110, and second irregularities 114 having rounded edges and low aspect ratios are formed on the rear surface . The first irregularities 112 and the second irregularities 114 having different shapes improve the optical characteristics and the passivation characteristics, respectively, and as a result, the efficiency of the solar cell 100 can be improved.

That is, according to the present invention, a solar cell 100 having high productivity and excellent efficiency can be manufactured.

6, a solar cell according to another embodiment of the present invention and a method of manufacturing the same will be described in detail. Hereinafter, detailed description will be omitted for the same or extremely similar parts as those of the above-described embodiments, and only different parts will be described in detail.

6 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Referring to FIG. 6, a third unevenness 116 smaller than the first unevenness 112 is formed on the side (inclined surface) of the first unevenness 112 in this embodiment. The third concavo-convex 116 is formed between the first texturing step (ST20 in FIG. 5B) and the second texturing step (ST30 in FIG. 5C) . ≪ / RTI >

At this time, the reactive ion etching in the second texturing step ST30 and the reactive ion etching in the step of forming the third irregularities 116 may have different process conditions. More specifically, in the second texturing step ST30, isotropic etching is performed using a single hexafluorophore as the reactant gas, while in the step of forming the third concavity and convexity 116, hexafluoropropane gas, Anisotropic etching is induced using a mixed gas of chlorine gas and oxygen gas.

Since the reactive ion etching generally forms uniform and fine irregularities, the third irregularities 116 may have an average height of 1 탆 or less (for example, 300 nm to 1 탆, more specifically 300 to 600 nm). And may have a sharp end similar to the first irregularities 112 by anisotropic etching.

The surface irregularities 116 smaller than the first irregularities 112 may be formed on the first irregularities 112 formed on the front surface of the semiconductor substrate 110 as the light receiving surface to reduce the surface reflectivity have. Hereinafter, the optical characteristics can be further improved, and as a result, the efficiency of the solar cell can be further improved.

Hereinafter, the present invention will be described in more detail with reference to examples of the present invention. However, the following experimental examples are merely illustrative of the present invention and the present invention is not limited to the following experimental examples.

Experimental Example

an n-type semiconductor substrate was prepared. The first texturing is performed by immersing the semiconductor substrate in an alkali solution to form first irregularities on the front and rear surfaces of the semiconductor substrate. Thereafter, reactive ion etching using sulfur hexafluoride gas on the rear surface of the semiconductor substrate was performed for 5 minutes to form second irregularities on the rear surface of the semiconductor substrate.

Boron (B) was doped on the entire surface of the semiconductor substrate to form an emitter layer. Then, phosphorus (P) is doped to the rear surface of the semiconductor substrate to form a rear whole layer. An antireflection film including a silicon nitride film was formed on the entire surface of the semiconductor substrate, and a passivation film including a silicon oxide film and a silicon nitride film was formed on the rear surface of the semiconductor substrate. A first electrode electrically connected to the emitter layer and a second electrode electrically connected to the rear surface layer were formed.

FIG. 7 shows a front view of the semiconductor substrate after the second texturing is completed, and FIG. 8 shows a rear view of the semiconductor substrate after the second texturing is completed. Referring to FIG. 7, a pyramid-shaped first irregularity having a sharp end is formed on the front surface of the semiconductor substrate, whereas a second irregularity having rounded ends is formed on the rear surface of the semiconductor substrate.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
110: semiconductor substrate
112: 1st unevenness
114: second unevenness
116: Third unevenness
20: Emitter layer
30: rear front layer
24: first electrode
34: Second electrode

Claims (20)

A substrate having a first surface having first irregularities and a second surface having second irregularities different from the first irregularities;
An impurity layer formed on the substrate; And
The electrode connected to the impurity layer
≪ / RTI > The method according to claim 1,
The first irregularities are formed to have a sharp end,
And the second irregularities are rounded at the ends. 3. The method of claim 2,
Wherein the substrate comprises silicon,
The first irregularities may have a side surface made of the (111) faces of the silicon,
Wherein the second irregularities have side surfaces formed of (111) planes of the silicon, and the ends are rounded. 3. The method of claim 2,
Wherein the first irregularities have a pyramid shape,
And the second irregularities have a pyramid shape in which the end portions are rounded. 3. The method of claim 2,
And the average height of the second irregularities is smaller than the average height of the first irregularities. 6. The method of claim 5,
Wherein a ratio of an average height of the second irregularities to an average height of the first irregularities is 0.6 to 0.9. 3. The method of claim 2,
The average height of the first irregularities is 10 to 15 占 퐉,
And the average height of the second irregularities is 5 to 12 占 퐉. 8. The method of claim 7,
Wherein an angle of the end portion in the cross section of the first concavo-convex is 65 to 85 degrees,
And the radius of curvature of the end portion in the second unevenness is 1.25 to 3 占 퐉. 3. The method of claim 2,
And third irregularities smaller in size than the first irregularities are further formed on the first irregularities. 10. The method of claim 9,
And the average height of the third irregularities is 1 占 퐉 or less. Preparing a substrate;
A first texturing step of forming first irregularities on a first surface and a second surface of the substrate;
A second texturing step of forming second irregularities on the second surface of the substrate different from the first irregularities;
Forming an impurity layer on the substrate; And
Forming an electrode electrically connected to the impurity layer
Wherein the method comprises the steps of: 12. The method of claim 11,
In the first texturing step, the substrate is etched anisotropically to form the first irregularities having sharp ends,
Wherein the second texturing rounds the end of the first irregularities located on the second surface of the substrate to form the second irregularities. 13. The method according to claim 11 or 12,
Wherein the second texturing is performed by reactive ion etching. 14. The method of claim 13,
Wherein a single hexafluorosulfur gas is used as a reactive gas in the reactive ion etching of the second texturing step. 13. The method of claim 12,
Wherein the substrate comprises silicon,
The first irregularities may have a side surface made of the (111) faces of the silicon,
Wherein the second irregularities have a side surface made of (111) planes of the silicon and the end rounded. 13. The method of claim 12,
Wherein the first irregularities have a pyramid shape,
And the second irregularities have a pyramid shape in which the ends are rounded. 12. The method of claim 11,
Performing a separate reactive ion etching on the first surface of the substrate between the first texturing step and the second texturing step to form a third irregular surface having a smaller size than the first irregular surface on the first irregular surface, Thereby forming a solar cell. 18. The method of claim 17,
Wherein the separate reactive ion etching uses a mixed gas obtained by mixing a hexafluoropropane gas, chlorine gas, and oxygen gas as a reactive gas. 18. The method of claim 17,
And the third irregularities have sharp ends. 18. The method of claim 17,
And the average height of the third irregularities is 1 占 퐉 or less.

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