KR20150124292A - Solar cell and method for manufacturing the same - Google Patents

Abstract

A method for manufacturing a solar cell according to an embodiment of the present invention includes a semiconductor layer forming step of forming a first semiconductor layer on one side of a semiconductor substrate and a second semiconductor layer on the other side of the semiconductor substrate, a first etching step of removing the first semiconductor layer located on one side of the semiconductor substrate, a second etching step of forming an uneven part on one side of the semiconductor substrate, and a conductive region forming step of forming a first conductive region by doping one side of the semiconductor substrate with a first conductive dopant and forming a second conductive region by doping the second semiconductor layer with a second conductive dopant.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

The present invention relates to a solar cell and a method of manufacturing the same.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be designed so as to maximize the efficiency of the solar cell.

The present invention provides a solar cell capable of improving efficiency and a manufacturing method thereof.

A method of manufacturing a solar cell according to an embodiment of the present invention includes a semiconductor layer forming step of forming a first semiconductor layer on one surface of a semiconductor substrate and forming a second semiconductor layer on the other surface of the semiconductor substrate; A first etching step of removing the first semiconductor layer located on one surface of the semiconductor substrate; A second etching step of forming recesses and protrusions on one surface of the semiconductor substrate; And forming a second conductive type region by forming a first conductive type region by doping a first conductive type dopant on one surface of the semiconductor substrate and doping the second conductive type dopant with the second conductive type dopant, .

A solar cell according to an embodiment of the present invention includes a semiconductor substrate including a base region and a first conductive type region doped with a first conductive type dopant, the first conductive type region being located on one side of the base region; A tunneling layer formed on the other surface of the base region; A second conductive type region which is located on the tunneling layer and has a crystal structure different from that of the semiconductor substrate and is doped with a second conductive type dopant; And an electrode including a first electrode connected to the first conductive type region and a second electrode connected to the second conductive type region. And an irregular portion having a size smaller than the other surface of the semiconductor substrate is formed on one surface of the semiconductor substrate.

In this embodiment, the first conductive type region is formed of a doped region formed by doping a first conductive type dopant in a semiconductor substrate, and the second conductive type region is formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate. This minimizes the interference of light from the front surface of the semiconductor substrate and minimizes deterioration of recombination characteristics in the second conductive type region located on the rear surface of the semiconductor substrate. Thus, the characteristics of the solar cell can be greatly improved.

Meanwhile, in this embodiment, the first etching step for removing the semiconductor layer located on the front surface of the semiconductor substrate and the second etching step for forming the small-sized concave-convex part on the semiconductor substrate are performed in the same reactive ion etching apparatus by the in- Can be carried out under process conditions. Accordingly, a solar cell having a desired structure can be manufactured while simplifying the process. Alternatively, the first etching step may be performed by wet etching and the second etching step may be performed by reactive ion etching to produce a solar cell having a desired structure by a simple process.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
2 is a plan view of the solar cell shown in Fig.
3 is a cross-sectional view illustrating a solar cell according to another embodiment of the present invention.
4A to 4I are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
5A to 5H are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
6A to 6G are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention, and FIG. 2 is a plan view of the solar cell shown in FIG. In FIG. 2, the semiconductor substrate and the electrodes are mainly shown.

1, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 10 and a first conductivity type region (or emitter region) 20 having a first conductivity type A second conductive type region 30 formed on the semiconductor substrate 110 and having a crystal structure different from that of the semiconductor substrate 110 and having a second conductive type and a second conductive type region 30 connected to the first conductive type region 20, A first electrode 42 and a second electrode 44 connected to the second conductivity type region 30. The solar cell 100 may further include a tunneling layer (or a second tunneling layer) 54, passivation films 22 and 32, and an anti-reflection film 24. This will be explained in more detail.

The semiconductor substrate 110 may be formed of a crystalline semiconductor. In one example, the semiconductor substrate 110 may be composed of a single crystal or polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon). In particular, the semiconductor substrate 110 may be composed of a single crystal semiconductor (for example, a single crystal semiconductor wafer, more specifically, a single crystal silicon wafer). Thus, when the semiconductor substrate 110 is made of a single crystal semiconductor (for example, a single crystal silicon), the solar cell 100 constitutes a single crystal semiconductor solar cell (for example, a single crystal silicon solar cell). The solar cell 100 based on the semiconductor substrate 110 formed of a crystalline semiconductor having high crystallinity and having few defects can have excellent electrical characteristics.

The front surface and / or the rear surface of the semiconductor substrate 110 may be textured to have irregularities. In this embodiment, the front surface and / or the rear surface of the semiconductor substrate 110 may have irregularities 112 and 114 formed by texturing. When the irregularities 112 and 114 are formed on the front surface and / or the rear surface of the semiconductor substrate 110 by such texturing, the reflectivity of light incident through the front surface and / or the rear surface of the semiconductor substrate 110 can be reduced. Therefore, the amount of light reaching the pn junction (for example, the pn tunnel junction) formed by the base region 10 and the first conductive type region 20 can be increased, and the optical loss can be minimized.

More specifically, in this embodiment, the concavities and convexities 112 and 114 are formed on the rear surface (rear surface side) of the semiconductor substrate 110 and the first concavities and convexities 112 formed on the front surface (or front surface side surface) And the second concave and convex portions 114 may be formed on the second concave and convex portions. Thus, reflection of light incident on the front surface and the rear surface of the semiconductor substrate 110 can be prevented, and the optical loss in the solar cell 100 having the bi-facial structure similar to that of the present embodiment can be effectively . However, the present invention is not limited to this, and it is also possible that only one of the first irregularities 112 and the second irregularities 114 is formed.

The first irregularities 112 located on the front surface of the semiconductor substrate 110 may include first irregularities 112a and second irregularities 112b to minimize optical loss. The second concavo-convex portion 112b is formed on the first concavo-convex portion 112a, more specifically, on the outer surface constituting the first concavo-convex portion 112a and may have a smaller size than the first concavo-convex portion 112a have. The average size of the second concave-convex portion 112b may be smaller than the average size of the first concave-convex portion 112a and the second concave-convex portion 112b may be smaller than the average size of the first concave- At least one, e.g., a plurality of, locations. The first irregular portion 112a and the second irregular portion 112b may be formed by different methods.

The outer surface of the first concavo-convex part 112a may be composed of specific crystal faces. For example, the first irregular portion 112a may have a rough pyramid shape formed by four outer surfaces that are (111) surfaces.

(For example, an average value of the height of the first irregular portion 112a) of the first irregular portion 112a may be a micrometer level (for example, 1um to 1mm), for example, Lt; / RTI > It may be difficult to manufacture the first concave portion 112a having an average size of less than 10 um and the average size of the first concave portion 112a may be formed to be less than 30 um to improve the antireflection effect. The deviation of the size of the first concavo-convex portion 112a may have a relatively large first variation.

The first concavo-convex portion 112a may be formed by anisotropic etching by wet etching. When the first irregular portion 112a is formed by wet etching, the first irregular portion 112a can be formed within a short time by a simple process. The process of forming the first concavo-convex portion 112a by wet etching will be described later in more detail. The shape, average size, size deviation, etc. of the first concavity and convexity 112a may be variously modified. The first concavo-convex portion 112a is not limited to the shape, the average size and the size variation of the first concavo-convex portion 112a.

The second concavo-convex portion 112b may be formed on the outer surface (for example, the (111) surface) of the first concavo-convex portion 112a while having a minute size. The second concave-convex portion 112b may have a pointed end, but the present invention is not limited thereto and the second concave-convex portion 112b may have rounded ends.

The average size (for example, the average value of the height of the second concave-convex portion 112b) of the second concave-convex portion 112b may be on the order of nanometers (i.e., 1um or less, for example, 1nm to 1um) For example, it may have a size of about 100 nm to 500 nm. If the second concave-convex portion 112b having a smaller size than the first concave-convex portion 112a is formed in this way, the anti-reflection effect can be improved. The second concavo-convex portion 112b having an average size of less than 100 nm may be difficult to manufacture, and if the average size of the second concavo-convex portion 112b is set to 500 nm or less, the antireflection effect can be further improved. The size variation of the second concave and convex portion 112b may have a second variation smaller than the first variation. This is because the average size of the second concave-convex portion 112b is smaller, and the process of the second concave-convex portion 112b is based on isotropic etching. Thus, in this embodiment, the uniform and fine second concave-convex portion 112b is formed on the outer surface of the first concave-convex portion 112a.

The second concavo-convex portion 112b may be formed by isotropic etching by dry etching. For dry etching, for example, reactive ion etching (IRE) may be used. The second irregular portion 112b can be formed finely and uniformly by reactive ion etching. The shape, average size, size deviation, etc. of the second concavo-convex portion 112b may be variously modified. The present invention is not limited to the shape, the average size, and the size variation of the second concavo-convex portion 112b.

In this embodiment, the second concave and convex portions 114 formed on the rear surface of the semiconductor substrate 110 may include the first concave and convex portions 114a. The description of the first concavity and convexity 112a of the first concavity and convexity 112 may be applied to the first concavity and convexity 114a of the second concavity and convexity 114, and thus a detailed description thereof will be omitted. When the second concave and convex portions 114 of the semiconductor substrate 110 have different shapes from the first concave and convex portions 112 having the first and second concave and convex portions 112a and 112b with only the first concave and convex portions 114a, Reflection of the light from the front surface of the semiconductor substrate 110 having a large amount of light can be effectively prevented by the first irregularities 112 and the second irregularities 114 can have a simple structure, The process can be simplified.

However, the present invention is not limited thereto. The first irregularities 112 formed on the front surface of the semiconductor substrate 110 may not have the first irregularities 112a and / or the second irregularities 114 may not be formed. Various other variations are possible.

The semiconductor substrate 110 may include a base region 10 having a second conductivity type including a second conductivity type dopant at a relatively low doping concentration. For example, the base region 10 may be located farther from the front surface of the semiconductor substrate 110 than the first conductivity type region 20, or closer to the rear surface. That is, in this embodiment, the first conductivity type region 20 is located on the front side of the semiconductor substrate 110. However, the present invention is not limited thereto, and it goes without saying that the position of the base region 10 can be changed.

Here, the base region 10 may be formed of a crystalline semiconductor containing a second conductive dopant. In one example, the base region 10 may be composed of a single crystal or a polycrystalline semiconductor (for example, single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, the base region 10 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a single crystal silicon wafer) comprising a second conductive dopant.

The second conductivity type may be n-type or p-type. When the base region 10 has an n type, the base region 10 is formed of a single crystal or polycrystalline semiconductor doped with a Group 5 element (P), arsenic (As), bismuth (Bi), antimony (Sb) Lt; / RTI > When the base region 10 has a p-type, the base region 10 is formed of a single crystal or polycrystalline semiconductor doped with boron (B), aluminum (Al), gallium (Ga) Lt; / RTI >

However, the present invention is not limited thereto, and the base region 10 and the second conductive dopant may be composed of various materials.

As an example, the base region 10 may be n-type. Then, the first conductivity type region 20 forming the pn junction with the base region 10 has p-type conductivity. When the pn junction is irradiated with light, electrons generated by the photoelectric effect move toward the second surface (hereinafter referred to as "back surface") of the semiconductor substrate 110 and are collected by the second electrode 44, 110 and collected by the first electrode 42. [ Thereby, electric energy is generated. Then, holes having a slower moving speed than electrons may move to the front surface of the semiconductor substrate 110, rather than the rear surface thereof, thereby improving the conversion efficiency. However, the present invention is not limited thereto, and it is also possible that the base region 10 and the second conductivity type region 30 have a p-type and the first conductivity type region 20 has an n-type.

A first conductivity type region 20 having a first conductivity type opposite to the base region 10 may be formed on the front side of the semiconductor substrate 110. [ The first conductive type region 20 forms a pn junction with the base region 10 to form an emitter region for generating carriers by photoelectric conversion.

In this embodiment, the first conductivity type region 20 may be a doped region constituting a part of the semiconductor substrate 110. Accordingly, the first conductive type region 20 may be formed of a crystalline semiconductor including the first conductive type dopant. In one example, the first conductive type region 20 may be composed of a single crystal or a polycrystalline semiconductor (for example, single crystal or polycrystalline silicon) including the first conductive type dopant. In particular, the first conductivity type region 20 may be composed of a single crystal semiconductor (for example, a single crystal semiconductor wafer, more specifically, a single crystal silicon wafer) including a first conductive type dopant. When the first conductivity type region 20 is formed as a part of the semiconductor substrate 110, the junction characteristics with the base region 10 can be improved.

The first conductivity type may be p-type or n-type. When the first conductive type region 20 has a p-type, the first conductive type region 20 is doped with boron (B), aluminum (Al), gallium (Ga), indium Single crystal or polycrystalline semiconductor. When the first conductive type region 20 has an n type, the first conductive type region 20 is doped with a Group 5 element such as (P), arsenic (As), bismuth (Bi), antimony (Sb) Single crystal or polycrystalline semiconductor. However, the present invention is not limited thereto, and various materials may be used as the first conductivity type dopant.

In this embodiment, the first conductivity type region 20 is formed entirely on the front side of the semiconductor substrate 110. The first conductivity type region 20 is located on the front side of the semiconductor substrate 110 in which light is relatively much incident and can minimize the loss of light before reaching the pn junction, The conductive type region 20 can have a sufficient area.

In addition, the first conductive type region 20 may be formed as a doped region so that a semiconductor layer having a different crystal structure is not formed on the front side of the semiconductor substrate 110. When the semiconductor layer is positioned on the semiconductor substrate 110 due to low light transmittance, light loss may occur due to the semiconductor layer. In this embodiment, the first conductive type region 20 including the doped region is formed in the semiconductor substrate 110 to prevent the problem of the semiconductor layer being located on the entire surface of the semiconductor substrate 110.

The thickness T1 of the first conductivity type region 20 formed of the doped region may be greater than the thickness T2 of the second conductivity type region 30. The first conductive type region 20 composed of a doped region formed by diffusion can be easily formed into a thick thickness. In addition, the thickness of the first conductivity type region 20 is sufficiently ensured to prevent a short-circuiting problem or the like when joining with the first electrode 42 and to have a sufficient junction depth. As an example, the thickness T1 of the first conductivity type region 20 may be 700 nm to 1.5 um. If the thickness T1 of the first conductivity type region 20 is less than 700 nm, the junction depth may not be sufficient and the characteristics may deteriorate. If the thickness T1 of the first conductivity type region 20 exceeds 1.5 .mu.m, it may be difficult to form a shallow emitter by doping with a high doping concentration or a long process time, The characteristics may be degraded. However, the present invention is not limited thereto, and the thickness of the first conductivity type region 20 may have various values.

In the figure, the first conductivity type region 20 has a homogeneous structure having a uniform doping concentration as a whole. However, the present invention is not limited thereto. Thus, in another embodiment, as shown in FIG. 3, the first conductive type region 20 may have a selective structure.

Referring to FIG. 3, the first conductive region 20 having the selective structure includes a first portion 20a formed adjacent to the first electrode 42 to be in contact with the first electrode 42, And a second portion 20b formed at a portion other than the portion 20a. The first portion 20a may have a relatively high doping concentration and the second portion 20b may have a lower doping concentration than the first portion 20a and may have a relatively high resistance. If the thickness of the first portion 20a is small, the first electrode 42 may penetrate the first portion 20a and contact the base region 10 to cause a shunt. Therefore, the first portion 20a Can be thicker than the first portion 20a. That is, the junction depth of the first portion 20a may be greater than the junction depth of the second portion 20b.

Then, a second portion 20b having a relatively high resistance is formed at a corresponding portion between the first electrodes 42 on which light is incident, thereby implementing a shallow emitter. Thus, the current density of the solar cell 100 can be improved. In addition, it is possible to reduce the contact resistance with the first electrode 42 by forming a first portion 20a having a relatively low resistance at a portion adjacent to the first electrode 42. [ That is, if the first conductivity type region 20 has the selective structure, the efficiency of the solar cell 100 can be maximized. In addition, various structures may be applied to the structure of the first conductivity type region 20. [

Referring to FIG. 3, first and second concave and convex portions (reference numerals 112 and 114 in FIG. 1) may be formed on the front surface and the rear surface of the semiconductor substrate 110, respectively.

Referring again to FIG. 1, a tunneling layer 54 may be formed on the rear surface of the semiconductor substrate 110. The tunneling layer 54 acts as a kind of barrier for electrons and holes so that minority carriers are not passed and a majority carrier is accumulated at a portion adjacent to the tunneling layer 54 So that only a plurality of carriers having energy above a certain level can pass through the tunneling layer 54. At this time, a plurality of carriers having energy above a certain level can easily pass through the tunneling layer 54 by the tunneling effect. The tunneling layer 54 may also serve as a diffusion barrier to prevent the dopant of the conductive region 30 from diffusing into the semiconductor substrate 110. The tunneling layer 54 may include various materials through which a plurality of carriers can be tunneled. For example, the tunneling layer 54 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the tunneling layer 54 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. At this time, the tunneling layer 54 may be formed entirely on the rear surface of the semiconductor substrate 110. Accordingly, it can be easily formed without additional patterning.

The thickness of the tunneling layer 54 may be smaller than the thickness of the passivation film 32 to sufficiently realize the tunneling effect. In one example, the thickness of the tunneling layer 54 may be 10 nm or less, and may be 0.5 nm to 10 nm (more specifically, 0.5 nm to 5 nm, for example, 1 nm to 4 nm). If the thickness of the tunneling layer 54 exceeds 10 nm, the tunneling may not occur smoothly and the solar cell 100 may not operate. If the thickness of the tunneling layer 54 is less than 0.5 nm, May be difficult to form. In order to further improve the tunneling effect, the thickness of the tunneling layer 54 may be 0.5 nm to 5 nm (more specifically, 1 nm to 4 nm). However, the present invention is not limited thereto, and the thickness of the tunneling layer 54 may have various values.

The second conductive type region 30 forms a back surface field to prevent carriers from being lost by recombination on the surface of the semiconductor substrate 110 (more precisely, the back surface of the semiconductor substrate 110) Thereby constituting a rear electric field area.

At this time, the second conductivity type region 30 may include a semiconductor (for example, silicon) including the same second conductivity type dopant as the base region 10. In this embodiment, the second conductivity type region 30 is formed separately from the semiconductor substrate 110 on the semiconductor substrate 110 (more specifically on the tunneling layer 54) and the second conductivity type dopant is doped As shown in Fig. Accordingly, the second conductivity type region 30 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 110 so as to be easily formed on the semiconductor substrate 110. For example, the second conductivity type region 30 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the second conductive type dopant. The second conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the second conductivity type dopant may be a dopant that can exhibit the same conductivity type as that of the base region 10. That is, when the second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used.

In this embodiment, the second conductivity type region 30 is formed entirely on the tunneling layer 54 on the backside of the semiconductor substrate 110. Since the second conductive type region 30 is formed on the tunneling layer 54 to reduce the doping region formed in the semiconductor substrate 110, damage to the semiconductor substrate 110, which may occur during the formation of the doped region, It is possible to effectively prevent an increase in the surface recombination due to the heat treatment. Accordingly, the surface recombination can be effectively prevented, and the open-circuit voltage of the solar cell 100 can be greatly improved. In addition, since the second conductive type region 30 is entirely formed, a separate patterning step or the like is not required.

The thickness T2 of the second conductivity type region 30 made of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 110 is smaller than the thickness T1 of the first conductivity type region 20 . If the thickness of the second conductivity type region 30 made of the semiconductor layer is increased, the process time may become longer and the effect of hydrogen implantation for passivation of the second conductivity type region 30 may be deteriorated. As an example, the thickness T2 of the second conductivity type region 30 may be between 100 nm and 500 um. If the thickness T2 of the second conductivity type region 30 is less than 100 nm, the electrical characteristics may deteriorate and the resistance may be increased or may be damaged when the second electrode 44 is formed. When the thickness T2 of the second conductivity type region 30 exceeds 500 nm, when hydrogen is injected for passivation of the second conductivity type region 30 during or after the formation of the second conductivity type region 30 The passivation characteristics of the second conductivity type region 30 may be deteriorated because hydrogen is not sufficiently injected. However, the present invention is not limited thereto, and the thickness of the second conductivity type region 30 may have various values.

The passivation film 22 and the antireflection film 24 are sequentially formed on the front surface of the semiconductor substrate 110 and more precisely on the first conductive type region 20 formed on the semiconductor substrate 110 and the first electrode 42 Is formed in contact with the first conductivity type region 20 through the passivation film 22 and the antireflection film 24 (that is, through the opening portion 102).

The passivation film 22 and the antireflection film 24 may be formed substantially entirely on the entire surface of the semiconductor substrate 110 except for the opening portion 102 corresponding to the first electrode 42. [

The passivation film 22 is formed in contact with the first conductivity type region 20 to passivate defects present in the surface or bulk of the first conductivity type region 20. [ Accordingly, the open-circuit voltage (Voc) of the solar cell 100 can be increased by removing recombination sites of the minority carriers. The antireflection film 24 reduces the reflectance of light incident on the front surface of the semiconductor substrate 110. Accordingly, the amount of light reaching the pn junction formed by the base region 10 and the first conductivity type region 20 can be increased by lowering the reflectance of the light incident through the entire surface of the semiconductor substrate 110. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. In this way, the efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 by the passivation film 22 and the antireflection film 24.

The passivation film 22 may be formed of various materials. For example, the passivation film 22 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ And may have a multi-layered film structure in which two or more films are combined. For example, the passivation film 22 may include a silicon oxide film, a silicon nitride film, or the like having a fixed positive charge if the first conductivity type region 20 has an n-type, and the first conductivity type region 20 and an aluminum oxide film having a negative negative charge if it has a p-type.

The anti-radiation film 24 may be formed of various materials. For example, the antireflection film 24 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , Layer structure having a combination of at least two layers. In one example, the antireflective film 24 may comprise silicon nitride.

However, the present invention is not limited thereto, and it goes without saying that the passivation film 22 and the anti-reflection film 24 may include various materials. It is also possible that any one of the passivation film 22 and the antireflection film 24 functions as an anti-reflection role and passivation, so that the other is not provided. Alternatively, various films other than the passivation film 22 and the antireflection film 24 may be formed on the semiconductor substrate 110. Other variations are possible.

The first electrode 42 is electrically connected to the first conductivity type region (not shown) through the opening 102 formed in the passivation film 22 and the antireflection film 24 (that is, through the passivation film 22 and the antireflection film 24) 20, respectively. The first electrode 42 may be formed to have various shapes by various materials. The shape of the first electrode 42 will be described later with reference to Fig.

A passivation film 32 is formed on the rear surface of the semiconductor substrate 110 and more precisely on the second conductive type region 30 formed on the tunneling layer 54 formed on the semiconductor substrate 110, Is connected to the second conductivity type region 30 through the passivation film 32 (i.e., through the opening 104).

The passivation film 32 may be formed substantially on the entire rear surface of the semiconductor substrate 110 except for the opening 104 corresponding to the second electrode 44. [

The passivation film 32 is formed in contact with the second conductivity type region 30 to passivate defects present in the surface or bulk of the second conductivity type region 30. Accordingly, the open-circuit voltage (Voc) of the solar cell 100 can be increased by removing recombination sites of the minority carriers.

The passivation film 32 may be formed of various materials. For example, the passivation film 32 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO _2, and CeO ₂ , Layer structure having a combination of at least two layers. For example, the passivation film 32 may include a silicon oxide film having a fixed positive charge, a silicon nitride film or the like when the second conductivity type region 30 has an n-type, and the second conductivity type region 30 and an aluminum oxide film having a negative negative charge if it has a p-type.

However, the present invention is not limited thereto, and it goes without saying that the passivation film 32 may include various materials. Alternatively, various films other than the passivation film 32 may be formed on the rear surface of the second conductivity type region 30. Other variations are possible.

The second electrode 44 is electrically connected to the second conductivity type region 30 through the opening 104 formed in the passivation film 32. The second electrode 44 may be formed to have various shapes by various materials.

The planar shapes of the first and second electrodes 42 and 44 will be described in detail with reference to FIG.

Referring to FIG. 2, the first and second electrodes 42 and 44 may include a plurality of finger electrodes 42a and 44a spaced apart from each other with a predetermined pitch. Although the finger electrodes 42a and 44a are parallel to each other and parallel to the edge of the semiconductor substrate 110, the present invention is not limited thereto. The first and second electrodes 42 and 44 may include bus bar electrodes 42b and 44b formed in a direction crossing the finger electrodes 42a and 44a to connect the finger electrodes 42a and 44a. have. Only one bus bar electrode 42b or 44b may be provided or a plurality of bus bar electrodes 42b and 44b may be provided with a larger pitch than the pitch of the finger electrodes 42a and 44a as shown in FIG. At this time, the width of the bus bar electrodes 42b and 44b may be larger than the width of the finger electrodes 42a and 44a, but the present invention is not limited thereto. Therefore, the width of the bus bar electrodes 42b and 44b may be equal to or smaller than the width of the finger electrodes 42a and 44a.

The finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may all be formed to pass through the passivation film 22 and the antireflection film 24 as viewed in cross section. That is, the opening 102 has a first opening portion 102a formed corresponding to the finger electrode 42a of the first electrode 42 and a second opening portion 102b formed corresponding to the bus bar electrode 42b. . ≪ / RTI > The finger electrode 44a and the bus bar electrode 44b of the second electrode 44 may all be formed through the passivation film 32. [ That is, the opening 104 may include a first opening portion formed corresponding to the finger electrode 44a of the second electrode 44 and a second opening portion formed corresponding to the bus bar electrode 44b. However, the present invention is not limited thereto. As another example, the finger electrode 42a of the first electrode 42 is formed to pass through the passivation film 22 and the antireflection film 24, and the bus bar electrode 42b is formed through the passivation film 22 and the antireflection film 24 As shown in FIG. In this case, the opening portion 102 includes the first opening portion 102a corresponding to the finger electrode 42a, and the second opening portion 102b corresponding to the bus bar electrode 42b may not be formed. A finger electrode 44a of the second electrode 44 may be formed through the passivation film 32 and a bus bar electrode 44b may be formed on the passivation film 32. [ In this case, the opening 104 may include the first opening portion corresponding to the finger electrode 44a, and the second opening portion corresponding to the bus bar electrode 44b may not be formed.

In the drawing, the first electrode 42 and the second electrode 44 have the same planar shape. The width and the pitch of the finger electrode 42a and the bus bar electrode 42b of the first electrode 42 may be the same as the width and pitch of the finger electrode 44a and the bus bar electrode 42b of the second electrode 44, A width, a pitch, and the like of the first electrode 44b. In addition, the first electrode 42 and the second electrode 44 may have different planar shapes, and various other modifications are possible.

As described above, in this embodiment, since the first and second electrodes 42 and 44 of the solar cell 100 have a predetermined pattern, and the solar cell 100 can be incident on the front and rear surfaces of the semiconductor substrate 110 It has a bi-facial structure. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited thereto, and it is also possible that the second electrode 44 is formed entirely on the rear side of the semiconductor substrate 110.

In this embodiment, the first conductive region 20, which is located on the front surface of the semiconductor substrate 110 and constitutes the emitter region, is formed as a doped region. The first conductive type region 20 is located on the rear surface of the semiconductor substrate 110, The second conductive type region 30 is formed of a separate semiconductor layer. Accordingly, a separate semiconductor layer is not formed on the front surface of the semiconductor substrate 110, thereby preventing optical loss. In addition, on the rear surface side of the semiconductor substrate 110 where light incidence is relatively small, the second conductivity type region 30 ) May be formed as a separate semiconductor layer instead of the doped region to minimize the recombination due to the formation of the doped region, thereby improving the open-circuit voltage of the solar cell 100.

The solar cell 100 having such a structure can be manufactured by forming a semiconductor layer on both sides of a semiconductor substrate 110 and then removing a semiconductor layer located on the entire surface of the semiconductor substrate 110. At this time, uniform and fine second irregularities 112b are formed on the entire surface of the semiconductor substrate 110 in the process of removing the semiconductor layer located on the front surface of the semiconductor substrate 110, It is possible to minimize the reflection of light in the light source. Then, the solar cell 100 having excellent characteristics can be manufactured by a simple process.

A manufacturing method of the solar cell 100 having the above-described structure will be described in detail with reference to Figs. 4A to 4I.

4A to 4I are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

As shown in FIG. 4A, a semiconductor substrate 110 having first concave-convex portions 112a and 114a is prepared. For example, a first uneven portion 112a of a first uneven portion 112 is provided on a front surface of a semiconductor substrate 110, and a first uneven portion 114a of a second uneven portion 114 is formed on a rear surface of the semiconductor substrate 110 May be provided.

For example, in this embodiment, the first irregularities 112a and 114a may be formed by wet etching. As the etching solution used for the wet etching, an alkali solution (for example, a solution containing potassium hydroxide (KOH)) can be used. According to the wet etching, the first irregularities 112a and 114a can be formed on the surface of the semiconductor substrate 110 by a simple process in a short time. At this time, a dipping process in which the semiconductor substrate 110 is immersed in the etching solution to etch the semiconductor substrate 110 on both sides (the front side and the rear side) may be used. Since the first irregularities 112a and 114a formed on the front surface and the rear surface of the semiconductor substrate 110 can be formed together by one immersion process, the process can be simplified.

Since the first irregularities 112a and 114a are etched according to the crystal planes of the semiconductor substrate 110 according to the wet etching, the outer surfaces of the first irregularities 112a and 114a have a predetermined crystal plane (for example, (111) Plane). Thus, the first irregularities 112a and 114a can have a pyramid shape having four (111) planes, can have an average size on the micrometer level, and the size deviation can have a relatively large first variation have. However, the present invention is not limited thereto, and the first irregularities 112a and 114a may be formed by various methods to have various shapes, average sizes, and size variations.

In this embodiment, the first concavo-convex portions 112a and 114a are formed on both sides of the semiconductor substrate 110 to minimize the optical loss in the solar cell 110 having a double-side light receiving structure. However, the present invention is not limited thereto, and it is also possible that first uneven portions 112a and 114a are formed on one of the front surface and the rear surface of the semiconductor substrate 110. Alternatively, the first concavo-convex portions 112a and 114a may not be formed on the front surface and the rear surface of the semiconductor substrate 110.

Then, as shown in FIG. 4B, tunneling layers 52 and 54 are formed on the entire surface of the semiconductor substrate 110 as a whole. More specifically, a first tunneling layer 52 is formed on the front surface of the semiconductor substrate 110 and a second tunneling layer 54 is formed on the rear surface of the semiconductor substrate 110. Although the first tunneling layer 52 and the second tunneling layer 54 are illustrated as being separated from each other in the drawing, the tunneling layers 52 and 54 are formed not only on the front surface and the rear surface of the semiconductor substrate 110, Or may be formed entirely on the surface of the substrate 110. In this case, the first tunneling layer 52 and the second tunneling layer 54 may be connected to each other by the tunneling layers 52 and 54 formed on the side surfaces of the semiconductor substrate 110.

The tunneling layers 52 and 54 may be formed by, for example, thermal growth, evaporation (e.g., chemical vapor deposition (PECVD), atomic layer deposition (ALD)), or the like. However, the present invention is not limited thereto, and the tunneling layers 52 and 54 may be formed by various methods.

Subsequently, semiconductor layers 302 and 304 may be formed on the tunneling layers 52 and 54, as shown in FIG. 4C. More specifically, a first semiconductor layer 302 is formed on the first tunneling layer 52, 54 and a second semiconductor layer 304 is formed on the second tunneling layer 54. Although the first semiconductor layer 302 and the second semiconductor layer 304 are illustrated as being separated from each other in the drawing, the semiconductor layers 302 and 304 may be formed on the entire surface of the semiconductor substrate 110 on the tunneling layers 52 and 54, But may be formed entirely on the surface of the semiconductor substrate 110. [ In this case, the first semiconductor layer 302 and the second semiconductor layer 304 may be connected to each other by the semiconductor layers 302 and 304 located on the side of the semiconductor substrate 110.

The semiconductor layers 302 and 304 may be formed by, for example, a vapor deposition method (for example, chemical vapor deposition (PECVD)) or the like. The semiconductor layers 302 and 304 may be formed of an intrinsic semiconductor (an amorphous semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, such as a polycrystalline semiconductor, or the like) which does not include the first or second conductivity type dopant and has a crystal structure different from that of the semiconductor substrate 110 , Amorphous silicon, microcrystalline silicon, or polycrystalline silicon). At this time, hydrogen may be diffused into the semiconductor layers 302 and 304 at the time of or after the semiconductor layers 302 and 304 are formed to passivate the semiconductor layers 302 and 304. However, the present invention is not limited thereto. Therefore, the semiconductor layers 302 and 304 may be deposited in a state doped with the first or second conductive type dopant, and various other modifications are possible.

Next, as shown in FIG. 4D, a first etching step is performed to remove the first tunneling layer 52 and the first semiconductor layer 302 located on the front surface of the semiconductor substrate 110 by the cross-sectional etching. When the tunneling layers 52 and 54 and the semiconductor layers 302 and 304 are located on the side surfaces of the semiconductor substrate 110, the tunneling layers 52 and 54 and the semiconductor layers 302 and 304, 304 may be etched together in the first etching step. In the drawing, the first tunneling layer 52 is etched together with the first semiconductor layer 302 in the first etching step. However, the present invention is not limited thereto. In the first etching step, all or a part of the first tunneling layer 52 may remain without being etched.

The first etching step will be described in more detail when the second etching step performed in the step shown in FIG. 4E is described.

Next, as shown in FIG. 4E, a second etching step of forming a second uneven portion 112b on the entire surface of the semiconductor substrate 110 is performed.

In this embodiment, the first etching step and the second etching step may be performed by an in-situ process consisting of a continuous process in the same equipment. Accordingly, the first and second etching steps can be performed by using the etching method capable of forming the second concavo-convex part 112b in the second etching step while performing the cross-sectional etching in the first etching step according to the process conditions have.

For example, in this embodiment, the first etching step and the second etching step are performed by reactive ion etching (RIE), and the process conditions may be different from each other.

The reactive ion etching method is a dry etching method in which a plasma is generated after etching gas (for example, Cl ₂ , SF ₆ , NF ₃ , HBr, etc.) is supplied and etched. Reactive ion etching can be applied to cross-sectional etching. The material can be etched in a substantially isotropic manner without considering the crystal orientation of the crystal grains and the like. The first semiconductor layer 302 and / or the first tunneling layer 52 located on the front surface of the semiconductor substrate 110 may be entirely removed according to process conditions such as etching gas used, The second concavo-convex portion 112b may be formed.

In this embodiment, the process conditions such as the kind of the etching gas, the partial pressure and the pressure are adjusted in the first etching step and the second etching step so that the desired etching is performed.

For example, in the first etching step, a gas obtained by mixing sulfur hexafluoride gas (SF ₆ ) and oxygen gas (O ₂ ) can be used. Here, sulfur hexafluoride gas acts to etch the first semiconductor layer 302 and / or the first tunneling layer 52. Oxygen gas acts on the surface of the first semiconductor layer 302 and / or the first tunneling layer 52 to form an oxide film and functions similarly to the mask to lower the etching rate, 1 semiconductor layer 302, or the first semiconductor layer 302 and the first tunneling layer 52, as shown in FIG. If only the oxygen gas is used together with the hexavalent harmful gas, the first semiconductor layer 302 or the first semiconductor layer 302 and the first tunneling layer 52 are isotropically etched at a slow etching rate, Only the first semiconductor layer 302 or the first semiconductor layer 302 and the first tunneling layer 52 can be selectively etched without damaging the semiconductor substrate 110 by the selection ratio with respect to the semiconductor substrate 110 .

At this time, the volume ratio of sulfur hexafluoride gas (in particular, the ratio of standard cubic centimeter per minute (sccm), hereinafter the same) may be larger than oxygen gas. This is because the hexafluoride gas is a gas that actually contributes to the etching, so that it can be injected in a sufficient amount to smooth the etching. As an example, the volume ratio of sulfur hexafluoride gas to oxygen gas may be between 10 and 50. If the volume ratio is less than 10, the volume ratio of the hexafluoride gas is small and the etching rate is not large, so that the processing time can be increased. If the volume ratio is more than 50, the etching rate becomes excessively large and the selectivity ratio of the first semiconductor layer 302, or the first semiconductor layer 302 and the first tunneling layer 52 to the semiconductor substrate 110 becomes small, The substrate 110 may be etched together. However, the present invention is not limited thereto, and the ratios may have different values.

And the pressure in the first etching step may be from 0.1 torr to 1 torr. If the pressure is less than 0.1 torr, the density of the plasma may become unstable. If the pressure exceeds 1 torr, the plasma density can be increased and the etching rate can be increased, whereby the first semiconductor layer 302, or the first semiconductor layer 302 and the first tunneling layer 52, The selectivity of the semiconductor substrate 110 may be reduced and the semiconductor substrate 110 may be etched together. However, the present invention is not limited thereto, and the second etching step may have different pressures.

In the second etching step, a gas obtained by further mixing chlorine gas (Cl ₂ ) together with hexafluoride gas and oxygen gas can be used. Here, the roles of hexafluoride gas and oxygen gas are the same as or very similar to those described in the first etching step. The chlorine gas increases the etching rate and induces the anisotropic etching, and controls the width, height, and the like of the second concave-convex portion 112b formed on the front surface of the semiconductor substrate 110. Accordingly, the second etching step is basically etched by isotropic etching, and anisotropic etching can be partially induced by chlorine gas. Accordingly, the entire surface of the semiconductor substrate 110 can be uniformly and finely etched to form the second concavo-convex portion 112b smaller than the first concavo-convex portion 112a.

At this time, the volume ratio of sulfur hexafluoride gas may be equal to or larger than the volume ratio of oxygen gas. In the second etching step, even if the ratio of the hexafluoride gas to the oxygen gas is relatively reduced, the chlorine gas can have a sufficient etching rate. Therefore, the oxygen gas is injected at a relatively large volume ratio to sufficiently realize the mask effect, thereby effectively preventing the semiconductor substrate 110 from being damaged. For example, the volumetric ratio of the hexafluoride gas to the oxygen gas may be 1 to 2. If the volume ratio is less than 1, the width of the second irregular portion 112b may be narrowed. If the volume ratio is more than 2, the height of the second irregular portion 112b may be reduced, 112b may be difficult to have a shape suitable for preventing reflection or may be difficult to be formed finely and uniformly.

And the volume ratio of chlorine gas may be equal to or less than the volume ratio of oxygen gas. This is because the chlorine gas can increase the etching rate even in a small amount. As an example, the volume ratio of chlorine gas to oxygen gas may be 0.2 to 1. If the volume ratio is less than 0.2, the width of the second concavo-convex portion 112b may be narrowed. If the volume ratio exceeds 1, the height of the second concavo-convex portion 112b may be decreased. May be difficult to have a shape suitable for preventing reflection or may be difficult to be formed finely and uniformly.

And the pressure in the second etching step may be less than the pressure in the first etching step. This is because oxygen gas for use as a mask is used in a large volume ratio in the second etching step, and therefore, if the pressure is high, the byproducts are increased and it is difficult to form the second concave and convex portions 112b. As an example, the pressure of the second etching step may be between 0.1 torr and 0.8 torr. If the pressure is less than 0.1 torr, the density of the plasma may become unstable. If the pressure exceeds 0.8 torr, the byproduct on the surface of the semiconductor substrate 110 increases and it may be difficult to form the second concavo-convex portion 112b. However, the present invention is not limited thereto, and the second etching step may have different pressures.

The second concave and convex portion 112b of the first concave and convex portion 112 formed by the second etching step is formed on the outer surface of the first concave and convex portion 112a and is formed on the outer side of the first concave and convex portion 112a It has a small average size. The reactive ion etching can form a fine second irregular portion 112b on the surface of the semiconductor substrate 110 irrespective of the crystal grain direction. At this time, the second concave and convex portion 112b may be formed to have a sharp top end, may have an average size on the order of nanometers, and the size deviation may have a second deviation smaller than the first deviation.

As described above, in this embodiment, the second concave-convex portion 112b having a smaller average size than the first concave-convex portion 112a of the first concavity and convexity 112 is formed on the first concavo- Can be minimized.

The first semiconductor layer 302 or the first semiconductor layer 302 and the first tunneling layer 52 located on the front surface of the semiconductor substrate 110 can be removed without damaging the semiconductor substrate 110 in the first etching step It can be easily etched.

The first concave and convex portion 112 includes the first concave and convex portion 112a and the second concave and convex portion 112b and the second concave and convex portion 114 includes the first concave and convex portion 114a, And does not have a portion 112b. Since the second etching step for forming the second concave-convex part 112b is performed after the first etching step for etching the first semiconductor layer 302, the rear surface of the semiconductor substrate 110 is etched by the second semiconductor layer 304 And the second etching step is performed by cross-sectional etching. Accordingly, the second concavo-convex portion 112b is formed on the front surface of the semiconductor substrate 110, and the second concavo-convex portion 112b is not formed on the rear surface. In this case, the surface area of the rear surface of the semiconductor substrate 110, in which light incidence is relatively small, can be minimized, and the damage caused by the reactive ion etching can be minimized, thereby improving the passivation characteristics.

Next, as shown in FIG. 4F, the second conductive type region 30 is formed by doping (or diffusing) the second conductive type dopant into the second semiconductor layer 304. Next, as shown in FIG. Various methods can be used for doping the second semiconductor layer 304 with the second conductive dopant. For example, a method such as ion implantation, thermal diffusion, or laser doping may be used. Alternatively, a dopant film (for example, a phosphorous silicate glass) may be formed on the second semiconductor layer 304 by using a dopant film containing a second conductive dopant , PSG) film) is formed on the first conductive type dopant, and then the second conductive type dopant is diffused by heat treatment, and then the dopant film is removed. Particularly, the ion implantation method or the method of forming the dopant film may be advantageous for cross-sectional doping.

Thus, in this embodiment, doping of the second conductivity type dopant is illustrated after the second semiconductor layer 304 having intrinsic characteristics is formed. The intrinsic semiconductor layer can be more easily etched so that the first semiconductor layer 304 can be more easily etched when the first semiconductor layer 304 is etched. However, the present invention is not limited to this. The first and second semiconductor layers 302 and 304 may be formed using a gas (for example, a PH ₃ gas) containing a second conductive dopant, And the second semiconductor layers 302 and 304 may have a second conductivity type. Since the second semiconductor layer 304 constitutes the second conductivity type region 30 without any additional doping process, the process for doping the second semiconductor layer 304 may be omitted to simplify the manufacturing process have. Other variations are possible.

After the doping of the second conductivity type dopant, a heat treatment for activation of the second conductivity type dopant may be additionally performed. This activation heat treatment is not essential and may be omitted depending on the doping method and the like.

4G, a first conductivity type region 20 is formed by doping (or diffusing) a first conductivity type dopant into the semiconductor substrate 110 from the front surface of the semiconductor substrate 110. [ A variety of methods may be used for doping the front surface of the semiconductor substrate 110 with the first conductive type dopant. For example, a method such as ion implantation, thermal diffusion, or laser doping may be used. Alternatively, a dopant film (for example, a boron silicate glass , BSG) film) is formed on the first conductive type dopant, and then the first conductive type dopant is diffused by heat treatment, and then the dopant film is removed. Particularly, the ion implantation method or the method of forming the dopant film may be advantageous for cross-sectional doping.

After the doping of the first conductivity type dopant, a heat treatment for activating the first conductivity type dopant may be additionally performed. This activation heat treatment is not essential and may be omitted depending on the doping method and the like.

For example, after forming the first and second conductivity type regions 20 and 30, the first conductivity type dopant of the first conductivity type region 20 and the second conductivity type dopant of the second conductivity type region 30 Can be activated together by co-activation heat treatment. For example, the temperature of the co-activation heat treatment may be between 850 ° C and 950 ° C. However, the present invention is not limited thereto, and the heat treatment temperature may have various values. However, the present invention is not limited thereto. Therefore, after the second conductive type region 30 is formed, the activation heat treatment is performed, and after that, the first conductive type region 20 is formed and then the activation heat treatment is performed to form the first and second conductive type regions 20 and 30, It is also possible to perform the activation heat treatment separately. Various other variations are possible.

In the above description, the second conductive type dopant is first doped and the first conductive type dopant is later doped. However, it is also possible to first doping the first conductive type dopant and later doping the second conductive type dopant. When the first and second conductivity type regions 20 and 30 are formed by dopant films, the dopant film for forming the first conductivity type region 20 and the second conductivity type region 30 for forming the second conductivity type region 30 The first and second conductive regions 20 and 30 may be formed together by heat treatment in the state where the dopant film is formed together, and then the dopant film may be removed. Various other variations are possible.

4H, a passivation film 22 and an antireflection film 24 are sequentially formed on the entire surface of the semiconductor substrate 110, and a passivation film 32 is formed on the rear surface of the semiconductor substrate 110 . That is, the passivation film 22 and the antireflection film 24 are entirely formed on the entire surface of the semiconductor substrate 110 and the passivation film 32 ). The passivation films 22 and 32 and the antireflection film 24 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating. The formation order of the passivation films 22 and 32 and the antireflection film 26 may be variously modified.

Next, first and second electrodes 42 and 44 connected to the first conductive type region 20 and the second conductive type region 30 are formed, respectively, as shown in FIG. 4I.

For example, after the opening 102 is formed in the passivation film 22 and the antireflection film 24 and the opening 104 is formed in the passivation film 32, a variety of plating methods, The first and second electrodes 42 and 44 can be formed.

As another example, after the paste for forming the first electrode is applied on the first passivation film 22 and the antireflection film 24 and the paste for forming the second electrode is applied on the second passivation film 32 by screen printing or the like, it is also possible to form the first and second electrodes 42 and 44 while forming the openings 102 and 104 by fire through or laser firing contact. In this case, since the openings 102 and 104 are formed at the time of firing the first and second electrodes 42 and 44, it is unnecessary to add a step of forming the openings 102 and 104 separately.

As described above, in this embodiment, the first semiconductor layer 302 and / or the first tunneling layer 52 located on the front surface of the semiconductor substrate 110 are removed by the first etching step. The first conductive type region 20 is formed as a doped region formed by doping (or diffusing) the first conductive type dopant into the semiconductor substrate 110. The second conductive type region 30 is formed by doping (or diffusing) a second conductive type dopant in the remaining second semiconductor layer 304 and is located between the semiconductor substrate 110 and the tunneling layer 54 And a semiconductor layer having a crystal structure different from that of the semiconductor substrate 110. This minimizes the interference of light from the front surface of the semiconductor substrate 110 and minimizes deterioration of recombination characteristics due to the second conductivity type region 30 located on the rear surface of the semiconductor substrate 110. Thus, the characteristics of the solar cell 100 can be greatly improved.

In this embodiment, in the first etching step and the second etching step, the semiconductor substrate 110 on which the tunneling layers 52 and 54 and the semiconductor layers 302 and 304 are formed is placed in the same reactive ion etching apparatus The material can be etched to have desired characteristics by controlling process conditions such as the kind of the etching gas, the volume ratio, and the pressure. That is, the semiconductor substrate 110 on which the tunneling layers 52 and 54 and the semiconductor layers 302 and 304 are formed is placed inside the reactive ion etching apparatus and oxygen gas: hexafluoride The first semiconductor layer 302 and / or the first tunneling layer 52 are etched by supplying the anti-gas at a volume ratio of 1:10 to 50. When the etching of the first semiconductor layer 302 and / or the first tunneling layer 52 is completed, oxygen gas: hexafluorosulfur gas: chlorine gas is supplied at a pressure of 0.1: 1 to 2: And the second concavo-convex portion 112b is formed on the entire surface of the semiconductor substrate 110 by supplying at a volume ratio of 0.2 to 1. Accordingly, the solar cell 100 having a desired structure can be manufactured while simplifying the process.

However, the present invention is not limited to this, and it is also possible to form the first etching step and the second etching step in a process other than a continuous in-situ process. Since the order of the various processes except for the first etching step and the second etching step is one example, it can be variously modified.

Hereinafter, a method of manufacturing a solar cell according to another embodiment of the present invention will be described in detail with reference to the accompanying drawings. The detailed description will be omitted for the same or extremely similar elements as those described above, and the different parts will be described in detail. Other embodiments, modifications and the like of the embodiments of the present invention described in one embodiment can be applied to other embodiments as they are.

5A to 5H are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

Tunneling layers 52 and 54 and semiconductor layers 302 and 304 are sequentially formed on both sides of the semiconductor substrate 110 as shown in FIG. This is the same as or very similar to the description with reference to Figs. 4A to 4C, and thus a detailed description thereof will be omitted.

Next, as shown in FIG. 5B, a dopant film 306 including a second conductive dopant is formed on a second semiconductor layer 304 located on the rear side of the semiconductor substrate 110. For example, when the second conductivity type region 30 is p-type, the dopant film 306 may be a boron silicate glass film, and when the second conductivity type region 30 is n-type, Glass film. For example, a boron silicate glass film or a phosphorus silicate glass film can be formed by a vapor deposition method or the like. However, the present invention is not limited thereto, and various materials and manufacturing methods may be used for the material of the dopant film 306.

Next, as shown in FIG. 5C, a first etching step for removing the first tunneling layer 52 and / or the first semiconductor layer 302 located on the front surface of the semiconductor substrate 110 is performed. In this embodiment, the second tunneling layer 54 and the second semiconductor layer 304, which are located on the rear side of the semiconductor substrate 110, are used as a mask, and the second tunneling layer 54 and the second Only the first tunneling layer 52 and / or the first semiconductor layer 302 located on the front side of the semiconductor substrate 110 can be removed without etching the semiconductor layer 304.

Accordingly, in this embodiment, the first etching step can be performed by wet etching. The wet etching may use an etching solution that can selectively etch the first semiconductor layer 302 and / or the first tunneling layer 54 without etching the dopant film 306. In one example, the etching solution may be an alkaline solution (e.g., a potassium hydroxide (KOH) solution). Using the wet etching as in the present embodiment, the first etching step can be performed by a simple process, and the second tunneling layer 54 and the second semiconductor layer 304 can be protected in the first etching step. However, the present invention is not limited thereto, and the first etching step may be performed by various etching methods other than wet etching.

Next, as shown in FIG. 5D, the second etching step is performed to form the second concave-convex portion 112b of the first concavity and convexity 112. Next, as shown in FIG. Since this is the same as or very similar to the description with reference to FIG. 4E, a detailed description will be omitted. At this time, the dopant film 306 located on the rear side of the semiconductor substrate 110 functions as a mask to protect the second tunneling layer 54 and the second semiconductor layer 304.

Next, as shown in FIG. 5E, the first conductive type region 20 is formed by doping the second semiconductor layer 304 with a first conductive type dopant. This is the same as or very similar to the description with reference to FIG. 4G, and thus a detailed description thereof will be omitted. At this time, the dopant film 306 located on the rear side of the semiconductor substrate 110 functions as a mask to prevent the second tunneling layer 54 and the second semiconductor layer 304 from being doped with the first conductive type dopant .

Next, as shown in FIG. 5F, the second conductive type dopant in the dopant film 306 is diffused into the second semiconductor layer 304 by heat treatment to form the second conductive type region 30. At this time, the first conductive type dopant in the first conductive type region 20 may be activated heat-treated together. Accordingly, the activation heat treatment of the first conductive type dopant in the first conductive type region 20 is not performed separately, so that the process can be simplified.

Alternatively, when the first conductive type region 20 is formed, the second conductive type dopant in the dopant film 306 may be diffused into the second semiconductor layer 304 to form the second conductive type region 30 together . For example, when the first conductive type region 20 is formed by a thermal diffusion method, the first conductive type dopant may be doped in the dopant film 306 at a high temperature (for example, 850 캜 to 950 캜) The second conductive type dopant is easily diffused into the second semiconductor layer 304. [ Accordingly, the second conductivity type region 30 may be formed together in the process of forming the first conductivity type region 20 without additional heat treatment for diffusing the second conductivity type dopant.

Then, as shown in Fig. 5G, the dopant film 306 is removed by etching. Various methods known as the etching method of the dopant film 306 may be applied.

Subsequently, passivation films 22 and 32, an antireflection film 24, and first and second electrodes 42 and 44 are formed as shown in FIG. 5H. This is the same as or very similar to the description with reference to FIG. 4H and FIG. 4I, and thus a detailed description thereof will be omitted.

In this embodiment, the first etching step is performed by wet etching using the dopant film 306 for doping the second conductivity type region 30 as a mask, so that the process can be simplified, and the etching process, the doping process, It is possible to effectively protect the second tunneling layer 54 and the second semiconductor layer 304 from being damaged.

In the above description, the dopant film 306 is formed on the second semiconductor layer 304. However, it is also possible to form a protective film that does not contain a dopant in place of the dopant film 306 on the second semiconductor layer 304 . When a protective film containing no dopant is used, the second semiconductor layer 304 may be formed so as to include the second conductive type dopant, or may be formed to include the second conductive type dopant in the second semiconductor layer 304, Type dopant may be doped. Various other variations are possible.

6A to 6G are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

The tunneling layers 52 and 54 and the semiconductor layers 302 and 304 are sequentially formed on both sides of the semiconductor substrate 110 as shown in FIG. This is the same as or very similar to the description with reference to Figs. 4A to 4C, and thus a detailed description thereof will be omitted.

Next, as shown in FIG. 6B, a first etching step of removing the first semiconductor layer 302 and the first tunneling layer 52 located on the front surface of the semiconductor substrate 110 by cross-sectional etching is performed. This is the same as or very similar to the description with reference to FIG. 4D, and thus a detailed description thereof will be omitted.

Next, as shown in FIG. 6C, a second etching step of forming a second uneven portion 112b on the entire surface of the semiconductor substrate 110 is performed. Since this is the same as or very similar to the description with reference to FIG. 4E, a detailed description will be omitted.

Subsequently, as shown in FIG. 6E, a dopant film 308 including a first conductive dopant is formed on the first semiconductor layer 302 located on the rear side of the semiconductor substrate 110. For example, when the first conductivity type region 20 is n-type, the dopant film 308 may be a phosphorous silicate glass film, and when the first conductivity type region 20 is p-type, the dopant film 308 may be a boron silicate Glass film. As an example, a phosphorous silicate glass film or a boron silicate glass film can be formed by a vapor deposition method or the like. However, the present invention is not limited thereto, and various materials and manufacturing methods can be used for the material of the dopant film 308 and the manufacturing method thereof.

Then, as shown in FIG. 6E, the second conductive type dopant is doped into the second semiconductor layer 304 to form the second conductive type region 30. This is the same as or very similar to the description with reference to FIG. 4F, and thus a detailed description thereof will be omitted. At this time, the dopant film 306 located on the front surface of the semiconductor substrate 110 functions as a mask, thereby effectively preventing doping of the second conductive dopant on the front surface of the semiconductor substrate 110.

The first conductive type dopant in the dopant film 308 is diffused into the semiconductor substrate 110 to form the first conductive type impurity on the entire surface of the semiconductor substrate 110. In this case, Regions 20 can be formed together. For example, if the second conductivity type region 30 is formed by a thermal diffusion method, the second conductivity type dopant may be doped into the dopant film 308 at a high temperature (e.g., 850 캜 to 950 캜) The first conductive type dopant is easily diffused into the semiconductor substrate 110. Accordingly, the first conductivity type region 20 may be formed together in the process of forming the second conductivity type region 30 without additional heat treatment for diffusing the first conductivity type dopant. As another example, when the second conductive type region 30 is formed by the ion implantation method, the first conductive type dopant is diffused by the activation heat treatment of the second conductive type region 30 to form the first conductive type region 20 . Thus, the process can be simplified.

Subsequently, as shown in Fig. 6F, the dopant film 308 is removed by etching. Various methods known as the etching method of the dopant film 308 can be applied.

Subsequently, passivation films 22 and 32, antireflection film 24, and first and second electrodes 42 and 44 are formed as shown in FIG. 6G. This is the same as or very similar to the description with reference to FIG. 4H and FIG. 4I, and thus a detailed description thereof will be omitted.

In this embodiment, in the process of forming the second conductive type region 30 by doping the second conductive type dopant in a state where the dopant film 308 for doping the first conductive type region 20 is located, the semiconductor substrate 110 Can be prevented from being doped to the front side of the first conductive type dopant. Thus, the characteristics of the solar cell 100 can be improved. In addition, when the doping process of the second conductive dopant is performed at a temperature higher than a predetermined temperature, the first conductive dopant in the dopant film 38 may be diffused to form the first conductive region 20 together. Thus, the manufacturing process can be simplified.

In the above description, the dopant film 308 is formed on the entire surface of the semiconductor substrate 110. However, it is also possible to form a protective film that does not contain a dopant in place of the dopant film 308 on the semiconductor substrate 110. When a protective film not containing a dopant is used, a separate doping process for forming the first conductivity type region 30 may be further performed.

5A to 5H illustrate the use of the dopant film 306 formed on the rear surface of the semiconductor substrate 110. FIGS. 6A to 6G illustrate a dopant film 308 formed on the front surface of the semiconductor substrate 110 . Alternatively, the dopant film 306 formed on the rear surface of the semiconductor substrate 110 and the dopant film 308 formed on the front surface of the semiconductor substrate 110 may all be used. In this case, after the second etching step, the dopant films 306 and 308 are formed by an in-situ process continuously performed in one equipment, and then heat treatment is performed at the same time to form the first conductive type The second conductivity type region 30 may be formed by diffusing the second conductivity type dopant into the second semiconductor layer 304 while forming the first conductivity type region 20 by diffusing the dopant into the semiconductor substrate 110 . Then, the process can be greatly simplified.

Features, structures, effects, and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
110: semiconductor substrate
112: 1st unevenness
114: second unevenness
112a, 114b: first concave-
112b: second uneven portion
20: first conductivity type region
30: second conductivity type region
42: first electrode
44: Second electrode

Claims (20)

Forming a first semiconductor layer on one surface of a semiconductor substrate and forming a second semiconductor layer on the other surface of the semiconductor substrate;
A first etching step of removing the first semiconductor layer located on one surface of the semiconductor substrate;
A second etching step of forming recesses and protrusions on one surface of the semiconductor substrate;
Forming a first conductive type dopant on one surface of the semiconductor substrate to form a first conductive type region and doping a second conductive type dopant on the second semiconductor type to form a second conductive type region;
Wherein the method comprises the steps of: The method according to claim 1,
Wherein the first etching step and the second etching step are performed by an in-situ process. The method according to claim 1,
The first etching step and the second etching step are respectively performed by reactive ion etching (RIE)
Wherein the process conditions of the first etching step and the second etching step are different from each other. The method of claim 3,
Wherein sulfur hexafluoride gas and oxygen gas are used in the first etching step,
And sulfur hexafluoride gas, oxygen gas, and chlorine gas are used in the second etching step. 5. The method of claim 4,
Wherein the volume ratio of the hexafluoride term in the first etching step is larger than the volume ratio of the oxygen gas,
Wherein the volume ratio of the sulfur hexafluoride in the second etching step is equal to or larger than the volume ratio of the oxygen gas and the volume ratio of the chlorine gas is equal to or smaller than the volume ratio of the oxygen gas. 5. The method of claim 4,
Wherein the volume ratio of the sulfur hexafluoride gas to the oxygen gas in the first etching step is greater than the volume ratio of the sulfur hexafluoride gas to the oxygen gas in the second etching step. The method according to claim 1,
Wherein the volume ratio of the sulfur hexafluoride gas to the oxygen gas in the first etching step is 10 to 50,
Wherein the volume ratio of the hexafluorosulfur gas to the oxygen gas is 1 to 2 in the second etching step. 8. The method of claim 7,
Wherein a volume ratio of the chlorine gas to the oxygen gas is 0.2 to 1 in the second etching step. The method of claim 3,
Wherein the pressure of the second etching step is equal to or less than the pressure of the first etching step. The method according to claim 1,
Wherein the first etching step is performed by wet etching,
Wherein the second etching step is performed by reactive ion etching. The method according to claim 1,
The conductive type region forming step may include:
Forming the first conductive type region by doping the first conductive type dopant on one side of the semiconductor substrate;
Forming a second conductive type region by doping the second semiconductor layer with the second conductive type dopant; And
Simultaneously heat-treating the first conductive type region and the second conductive type region;
Wherein the method comprises the steps of: The method according to claim 1,
Forming a dopant film including a second conductive dopant on the second semiconductor layer between the semiconductor layer forming step and the first etching step,
Wherein the second conductive type dopant in the dopant film diffuses into the second semiconductor layer to form a second conductive type region in the conductive type region forming step. The method according to claim 1,
Forming a dopant film including a first conductive type dopant on one surface of the semiconductor substrate between the second etching step and the conductive type region forming step,
Wherein the first conductive dopant in the dopant film diffuses into the semiconductor substrate to form the first conductive type region in the conductive type region forming step. The method according to claim 1,
And the size of the uneven portion formed by the second etching step is 100 nm to 500 nm. The method according to claim 1,
Wherein the semiconductor substrate has another concavo-convex portion having a size larger than that of the convexo-concave portion before the step of forming the semiconductor layer,
And the concave-convex portion formed in the second etching step is located on the surface of the another concave-convex portion. 1. A semiconductor device comprising: a semiconductor substrate having a base region and a first conductive type region doped with a first conductive type dopant, the first conductive type region being located on one side of the base region;
A tunneling layer formed on the other surface of the base region;
A second conductive type region which is located on the tunneling layer and has a crystal structure different from that of the semiconductor substrate and is doped with a second conductive type dopant; And
A first electrode coupled to the first conductivity type region, and a second electrode coupled to the second conductivity type region,
/ RTI >
And a concavo-convex portion having a smaller size than the other surface of the semiconductor substrate is disposed on one surface of the semiconductor substrate. 17. The method of claim 16,
The first conductivity type region constituting an emitter region,
And the second conductivity type region constitutes a rear electric field region. 17. The method of claim 16,
Wherein one surface of the semiconductor substrate is the front surface of the semiconductor substrate,
And the other surface of the semiconductor substrate is the rear surface of the semiconductor substrate. 17. The method of claim 16,
Wherein a size of the concavo-convex portion located on one surface of the semiconductor substrate is 100 nm to 500 nm. 17. The method of claim 16,
Wherein the first conductivity type region has a single crystal structure,
And the second conductivity type region has an amorphous, microcrystalline, or polycrystalline structure.

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