KR20140074468A

KR20140074468A - Testing apparatus for semiconductor

Info

Publication number: KR20140074468A
Application number: KR1020120142445A
Authority: KR
Inventors: 정성이
Original assignee: 엘지이노텍 주식회사
Priority date: 2012-12-10
Filing date: 2012-12-10
Publication date: 2014-06-18

Abstract

The embodiment includes a control unit including a main board and a plurality of channels; A probe card for receiving and driving an electrical signal of the main board; A plurality of probe pin pairs connected to the probe card; And a substrate disposed opposite to the plurality of probe pins.

Description

[0001] TESTING APPARATUS FOR SEMICONDUCTOR [0002]

The embodiment relates to a semiconductor inspection apparatus.

BACKGROUND ART Light emitting devices such as light emitting diodes and laser diodes using semiconductor materials of Group 3-5 or 2-6 group semiconductors have been widely used for various colors such as red, green, blue, and ultraviolet And it is possible to realize white light rays with high efficiency by using fluorescent materials or colors, and it is possible to realize low power consumption, semi-permanent life time, quick response speed, safety, and environment friendliness compared to conventional light sources such as fluorescent lamps and incandescent lamps It has the advantage of gender.

Therefore, a transmission module of the optical communication means, a light emitting diode backlight replacing a cold cathode fluorescent lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, a white light emitting element capable of replacing a fluorescent lamp or an incandescent lamp Diode lighting, automotive headlights, and traffic lights.

The semiconductor such as the above-mentioned light emitting element needs to be inspected after its fabrication. A conventional detection method for testing the luminescence characteristics of a semiconductor device on a wafer is a point testing device such as Taiwan Patent Publication No. M382577 and Taiwan Patent Publication No. M260860.

In a conventional point testing apparatus, a test is performed for each semiconductor. For example, when there are 2000 semiconductors on a 2-inch wafer, the test time is long and the efficiency is low when testing each semiconductor with a point testing apparatus.

The embodiment is intended to provide an apparatus for testing a plurality of semiconductors in a short time.

The semiconductor inspection apparatus may further include a heat sink disposed in a direction opposite to the probe pin with the substrate therebetween.

And a plurality of optical sensors respectively corresponding to the plurality of probe pin pairs.

And a plurality of semiconductors disposed on the substrate, wherein each of the plurality of semiconductors may be disposed in correspondence with the plurality of pairs of the probe pins and the photosensor.

In the semiconductor inspection apparatus, a plurality of semiconductors may be arranged in a flip chip type.

The semiconductor may include a first electrode and a second electrode and a light emitting structure disposed on a submount, and the pair of probe pins may be disposed corresponding to the first electrode and the second electrode.

The light emitting structure may emit light in the ultraviolet or deep ultraviolet region.

The probe pin can apply a current having a different magnitude to the semiconductor in aging and device characteristic inspection of the light emitting structure.

The aging may simultaneously apply a current to the plurality of probe pin pairs, and the device characteristic inspection of the light emitting structure may sequentially apply current to the plurality of prubu pin pairs.

The semiconductor inspection apparatus may further include a circuit disposed in the main board and generating an address signal in the pair of probe pins.

The semiconductor inspection apparatus according to the embodiment can reduce the aging time by progressing the aging process simultaneously from a pair of the probe pins for each of a plurality of semiconductors and can perform the inspection of the voltage and optical characteristics sequentially without rotating the substrate, have.

1 is a block diagram of an embodiment of a semiconductor inspection apparatus,
2 is a schematic view showing a structure of a semiconductor inspection apparatus,
3 is a view showing the semiconductor of FIG. 2,
FIG. 4 is a view showing an arrangement of semiconductors in FIG. 2,
5 is a view showing a semiconductor inspection process.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

In the description of the embodiment according to the present invention, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

FIG. 1 is a block diagram of an embodiment of a semiconductor inspection apparatus, and FIG. 2 is a diagram schematically showing the structure of a semiconductor inspection apparatus.

A semiconductor inspection apparatus 100 according to an embodiment of the present invention includes a controller 110, a probe card 120 and a substrate 140. The semiconductor inspection apparatus 100 includes a light emitting device chip 200, The semiconductor can be arranged so that the aging and current characteristics or optical characteristics of the semiconductor can be inspected.

The controller 110 controls driving of the semiconductor testing apparatus and may include a main board and one or a plurality of channels 115. The number of the channels 115 may be one, (200).

The channel 115 can supply an address signal to the channel 115 in a circuit such as a driver IC in the main board even if one channel 115 is used, A current can be applied to the probe pin pair 11a and 121b corresponding to the chip 200. [

The probe card 120 is controlled by receiving an electrical signal from the main board, and is configured by a circuit board or the like to control the intensity or time of a current applied to each pair of probe pins.

The substrate 140 is disposed facing a plurality of pairs of probe pins 121a and 121b. The substrate 140 may be a conductive or insulating material. When the substrate is made of a conductive material, an insulating layer may be formed on the surface.

A heat sink 145 may be disposed in a direction opposite to the pair of probe pins 121a and 121b with the substrate 140 therebetween, that is, below the substrate 140 in FIG. The heat sink 145 is made of a material having a good thermal conductivity and can emit heat emitted from the light emitting device chip 200 in an aging process or the like. As shown in the drawing, the heat sink 145 has a large surface area, . The heat sink 145 may be another type of heat dissipation unit, which may be particularly necessary for a light emitting device chip that emits light in the deep ultraviolet region.

A photosensor 125 is disposed corresponding to each of the pair of probe pins 121a and 121b so that the optical characteristics after aging of the light emitting device chip 200 can be inspected. A pair of probe pins 121a and 121b and one optical sensor 125 are arranged corresponding to the respective semiconductor devices such as the light emitting device chips 200 in FIG. Aging and characteristic inspection can be performed.

3 is a view showing the semiconductor of FIG.

The semiconductor according to this embodiment may be a light emitting device chip 200 and is arranged in a flip chip type and may be a blue light emitting diode or a light emitting diode that emits ultraviolet rays or deep ultraviolet rays according to a wavelength region of emitted light, And may be a horizontal type light emitting device or a vertical type light emitting device in addition to the flip chip type.

The light emitting device chip 200 includes a first electrode 222 and a second electrode 224 disposed on the submount 210 and a light emitting structure is formed on the first electrode 222 and the second electrode 224 with solder 232 And 234, respectively.

The light emitting structure includes a first conductive semiconductor layer 252, an active layer 254, and a second conductive semiconductor layer 256 sequentially disposed on a substrate 270 with a buffer layer 260 therebetween, A first bonding pad 242 and a second bonding pad 244 are disposed on the surfaces of the conductive type semiconductor layer 252 and the second conductive type semiconductor layer 256 to electrically connect the sub- May be electrically connected to the first electrode 222 and the second electrode 224 on the substrate 210, respectively.

The first electrode 222 and the second electrode 224 may be made of a conductive material, specifically, a metal. More specifically, the sub-mount 210 may be made of copper (Cu) or aluminum Al) or the like.

The first conductive semiconductor layer 252 may be formed of a semiconductor compound, for example, a compound semiconductor such as a group III-V element or a group II-VI element. Also, the first conductivity type dopant may be doped. When the first conductive type semiconductor layer 252 is an n-type semiconductor layer, the first conductive type dopant may include Si, Ge, Sn, Se, and Te as an n-type dopant.

Electrons injected through the first conductive type semiconductor layer 252 and holes injected through the second conductive type semiconductor layer 256 which are formed later are brought into mutual contact with each other in the active layer 254, Is a layer that emits light having energy determined by the energy.

The second conductive semiconductor layer 256 may be formed of a semiconductor compound, for example, a compound semiconductor such as a group III-V element or a group II-VI element doped with a second conductive type dopant. The second conductivity type semiconductor layer 256 may be formed of, for example, In _x Al _y Ga ₁ _-x- _y N (0? X? 1, 0? _Y? 1, 0? _X + y? And the like. When the second conductivity type semiconductor layer 256 is a p-type semiconductor layer, the second conductivity type dopant may include, but not limited to, Mg, Zn, Ca, Sr, and Ba as a p-type dopant.

3, a pair of probe pins 121a and 121b are electrically connected to the first electrode 222 and the second electrode 224 to perform aging and device characteristic inspection. This aging and inspection can be done simultaneously on each of the semiconductors, and FIG. 4 shows the arrangement of the semiconductors in FIG.

The light emitting device chips 200 arranged on the substrate 140 on a plurality of semiconductors, that is, on the submount in this embodiment, are arranged in rows and columns and arranged at the wafer level, Pairs of the same number of the probe pins 121a and 121b are arranged so that aging and device characteristic inspection can be simultaneously performed for each semiconductor at the wafer level.

5 is a view showing a semiconductor inspection process.

First, a light emitting device chip (LED chip) is arranged on a substrate (S100), and arranged in a plurality of rows and columns as shown in FIG.

Then, a plurality of light emitting device chips are aged (S110). Aging can be performed by applying current to each light emitting device chip, for example, a current of 20 milliamperes (mA) or more for 24 hours. At this time, since each of the light emitting device chips is driven, heat may be generated, and the heat can be dissipated by the above-described heat sink.

Then, a current is supplied to each light emitting element chip (S120), and the voltage and optical characteristics of each light emitting element chip can be detected (S130). At this time, 0.01 microamperes, 0.1 microamperes, 1 microamperes, and 10 microamperes may be sequentially applied to each light emitting element chip, and the applied time may be one second to several seconds and less than one second . Aging requires confirmation of deterioration of the light emitting device chip, so that a relatively higher current can be applied for a long time than in the voltage and optical property test of the light emitting device chip.

If the number of probe pin pairs is smaller than the number of semiconductor elements, the substrate or probe pin pair must be rotated or moved for aging and inspection of voltage and optical characteristics. In this embodiment, such a process can be omitted.

At this time, the electrical characteristics of the light emitting device can be inspected by measuring the voltage of the light emitting device chip from two electrodes connected to the light emitting device chip after applying the current in the above-mentioned probe pin pair. Also, the brightness and / or the color temperature of light emitted from the light emitting device chip in the above-described optical sensor may be inspected.

The aging process described above is performed for a plurality of light emitting device chips at the same time, but the voltage and optical characteristic tests can be sequentially performed because the aging is performed for a long time, but the voltage and optical characteristic tests can be performed for a short time.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100: semiconductor inspection apparatus 110:
115: channel 120: probe card
121a, 121b: a pair of probe pins 125: a light sensor
140: substrate 145: heat sink
200: light emitting device chips 222, 224: first and second electrodes
232, 234: solder 242, 244: first and second bonding pads
252, 256: first conductivity type semiconductor layer 254: active layer
260: buffer layer 270: substrate

Claims

A control unit including a main board and at least one channel;
A probe card for receiving and driving an electrical signal of the main board;
A plurality of probe pin pairs connected to the probe card; And
And a substrate disposed opposite to the plurality of probe pin pairs.

The method according to claim 1,
Further comprising a heat sink disposed opposite to the probe pin with the substrate interposed therebetween.

The method according to claim 1,
And a plurality of optical sensors respectively corresponding to the plurality of probe pin pairs.

The method of claim 3,
And a plurality of semiconductors disposed on the substrate, wherein the plurality of semiconductors are disposed so as to correspond to the plurality of pairs of probe pins and the optical sensors, respectively.

The method of claim 3,
Wherein the plurality of semiconductors are arranged in a flip chip type.

The method of claim 3,
Wherein the semiconductor has a first electrode and a second electrode and a light emitting structure disposed on a submount, and the pair of probe pins are disposed corresponding to the first electrode and the second electrode.

The method according to claim 6,
Wherein the light emitting structure emits light in the ultraviolet or deep ultraviolet region.

The method according to claim 6,
Wherein the probe pin applies a current having a different magnitude to the semiconductor in aging and in a device characteristic inspection of the light emitting structure.

9. The method according to any one of claims 6 to 8,
Wherein the aging simultaneously applies a current to the plurality of probe pin pairs and the device characteristic inspection of the light emitting structure sequentially applies a current to the plurality of prubu pin pairs.

The method according to claim 1,
And a circuit disposed in the main board and generating an address signal in the pair of probe pins.