KR20140056615A - Display device and driving method the same - Google Patents

Abstract

The present invention provides a display device comprising a display panel; a gate driver supplying a gate signal to the display panel; data drivers supplying a data signal to the display panel; and a timing controller controlling the data drivers to converge optimal transmission conditions automatically by observing an interrupt signal generated from the data driver and responding to impedance characteristics of each transmission line connected to the data drivers.

Description

DISPLAY DEVICE AND DRIVING METHOD THEREOF

An embodiment of the present invention relates to a display device and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Currently, display devices such as liquid crystal display devices and organic electroluminescent display devices are being implemented to a small size, a medium size and a large size.

The display device as described above includes a display panel including sub-pixels arranged in a matrix form, a driver for driving the display panel, and a timing controller for controlling the driver. The driver includes a gate driver for supplying a gate signal to the display panel and a data driver for supplying a data signal to the display panel.

Some of the display devices described above are connected in a high-speed point-to-point interface manner in transmission lines between the timing controller and the data driver.

The high-speed point-to-point interface scheme should define the optimal transmission conditions for transmitting and receiving data according to the impedance characteristics of the transmission path. Variables that define the optimal transmission conditions include differential swing level, pre-emphasis, equalizer, and termination resistor value of the transmitter and receiver (Tx & Rx Termination Resistor Value).

However, in the conventional high-speed point-to-point interface method, a development step for detecting an optimal transmission condition must be performed in order to match impedances between devices. In addition, the conventional high-speed point-to-point interface method can not cope with a change in characteristics due to temperature or surrounding environment even if an optimum transmission condition is detected. Therefore, in the conventional high speed point-to-point interface method, it is necessary to improve not only the hardware access but also the time consuming to reset it from the development stage in order to change the detected optimal transmission condition.

In order to solve the problems of the background art described above, according to the present invention, optimal transmission conditions are automatically converged corresponding to impedance characteristics of transmission lines, and transmission conditions are automatically changed in response to changes in characteristics due to temperature, The present invention also provides a display device having a timing controller and a data driver connected by a high-speed point-to-point interface method and a method of driving the same.

According to an aspect of the present invention, A gate driver for supplying a gate signal to the display panel; A data driver for supplying a data signal to the display panel; And a timing controller for controlling the data drivers and observing the interrupt signal generated from the data driver and automatically converging the optimum transmission condition corresponding to the impedance characteristic of each transmission line connected to the data driver .

The timing control unit may change the differential swing level of the data packet to be supplied to the data drivers in accordance with the impedance characteristic of each transmission line connected to the data drivers.

The timing controller may activate or deactivate the preamplifier for the data packet to be supplied to the data drivers in accordance with the impedance characteristic of each transmission line connected to the data drivers.

The timing controller may enable or disable the equalizers included in the data drivers according to the impedance characteristics of the transmission lines connected to the data drivers.

The timing controller may change at least one of the terminal resistor value of the data driver and the terminal resistor value of the data drivers in accordance with the impedance characteristic of the transmission line connected to the data driver.

The data driving units generate respective interrupt signals. The timing control unit changes the differential swing levels of the data packets to be supplied to the data drivers in accordance with the occurrence of the interrupt signal, or changes the differential swing level of the data packets to be supplied to the data drivers, It is possible to individually change the resistance value of the terminating resistor of the receiving end of the data driving units respectively, to activate or deactivate the preamps of the data packets to be supplied to the data driving units respectively, or to activate or deactivate the equalizers respectively included in the data driving units.

According to another aspect of the present invention, there is provided a method of driving a display device having a timing controller and a data driver connected by a point-to-point interface, the method comprising: changing a differential swing level of a data packet to be supplied to a data driver; Changing the resistance value of the terminal resistor of the transmitting end of the timing control unit and the resistance value of the terminating resistor of the receiving end of the data driving unit; Activating or deactivating a preamplification of a data packet to be supplied to the data driver; And a step of activating or deactivating the equalizer included in the data driver.

If an interrupt signal is generated from the data driving unit after the differential swing level is lowered, the differential swing level is raised. If the interruption signal is generated from the data driving unit after the preamplification is deactivated, the preamplifier is activated and the equalizer is deactivated. When an interrupt signal is generated, the equalizer can be activated.

The timing control unit can automatically converge the optimum transmission condition corresponding to the impedance characteristic of each transmission line connected between the data drivers by changing the changing condition in stages according to the interrupt signal generated from the data driver.

The timing controller may fix the currently set condition after the optimal transmission condition is detected, and then update the optimal transmission condition by observing the interrupt signal generated from the data driver for every N (N is an integer greater than or equal to 1) vertical blank interval .

The present invention relates to a display device having a timing control part and a data driving part connected to each other by a high-speed point-to-point interface method capable of automatically transmitting optimum transmission conditions in accordance with impedance characteristics of each transmission line, There is an effect to provide. The present invention also provides a display device having a timing controller and a data driver connected by a high-speed point-to-point interface system capable of automatically changing transmission conditions in response to a change in characteristics due to temperature, surrounding environment, and a driving method thereof .

1 is a block diagram schematically showing a display device according to an embodiment of the present invention;
Fig. 2 is a schematic view showing the subpixel shown in Fig. 1. Fig.
3 is a schematic configuration diagram of the apparatus shown in Fig.
4 is a block diagram of a timing controller and data drivers according to an embodiment of the present invention.
5 is an equivalent circuit diagram for explaining a transmission line between a timing control section and a data driving section;
6 is a diagram showing a form of a data packet output from the timing control unit;
7 is an exemplary view of an interrupt signal promised between a timing controller and data drivers;
8 is an exemplary view of an optimal transmission condition detection method by changing the differential swing level;
9 is an illustration of an optimal transmission condition detection method by changing the resistance value of a terminating resistor.
10 is an exemplary view of an optimal transmission condition detection method by changing a preamplification.
11 is an exemplary diagram for explaining a process of detecting an optimum transmission condition;
12 is an exemplary diagram for explaining that an optimal transmission condition can be detected during a vertical blank period;
13 is a flowchart of a method of detecting an optimal transmission condition according to the first embodiment of the present invention.
14 is a flowchart of a method of detecting an optimal transmission condition according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram schematically showing a display device according to an embodiment of the present invention, Fig. 2 is a schematic diagram showing the subpixel shown in Fig. 1, Fig. 3 is a schematic Fig.

1, a display device according to an exemplary embodiment of the present invention includes a timing controller 130, a memory unit 120, a gate driver 140, data drivers 150, and a display panel 160 .

The memory unit 120 supplies the internally stored data to the timing controller 130. The memory unit 120 stores the extended display identification data (EDID) including the resolution, frequency, and timing information of the display panel 160, compensation data, and the like.

The timing controller 130 collects device information (Extended Display Identification Data (EDID), compensation data, etc.) including the resolution, frequency, and timing information of the display panel 160 from the memory unit 120 through an I2C interface or the like . The timing controller 130 outputs a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data drivers 150. The timing controller 130 supplies the data driver 150 with the data signal DATA along with the data timing control signal DDC.

The gate driver 140 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 130. The gate driver 140 supplies gate signals to the sub-pixels SP included in the display panel 160 through the gate lines GL.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 130 and converts the sampled data signal into a gamma reference voltage. The data driver 150 supplies the data signal DATA to the sub-pixels SP included in the display panel 160 through the data lines DL.

The display panel 160 displays an image corresponding to the gate signal supplied from the gate driver 140 and the data signal DATA supplied from the data driver 150. The display panel 160 includes sub-pixels SP for controlling light to display an image.

As shown in FIG. 2, one sub-pixel is operated in response to a data signal DATA supplied through a switching transistor SW and a switching transistor SW connected to a gate line GL1 and a data line DL1 A pixel circuit PC is provided. According to the configuration of the pixel circuit PC, the sub-pixels SP may be constituted by a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element.

When the display panel 160 is composed of a liquid crystal display panel, it may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) mode, or an ECB (Electrically Controlled Birefringence) Mode. When the display panel 160 is formed of an organic light emitting display panel, the display panel 160 may be a top emission type, a bottom emission type, or a dual emission type.

As shown in FIG. 3, the memory unit 120 and the timing controller 130 are formed in an integrated circuit (IC) form and mounted on the printed circuit board 131. The data drivers 150a to 150c are also formed in an IC form and mounted on the flexible circuit boards 151 to 153 separately. The gate driver 140 is formed in a gate in panel (GIP) manner and is formed in a thin film shape on a bezel area outside the display area AA of the display panel 160. The printed circuit board 131, the flexible circuit boards 151 to 153, and the display panel 160 are electrically connected by an anisotropic conductive film (ACF) or the like.

In the display device of the present invention described above, transmission lines between the timing controller 130 and the data drivers 150a to 150c are connected by a high-speed point-to-point interface.

The high-speed point-to-point interface scheme should define the optimal transmission conditions for transmitting and receiving data according to the impedance characteristics of the transmission path. Variables that define the optimal transmission conditions include differential swing level, pre-emphasis, equalizer, and termination resistor value of the transmitter and receiver (Tx & Rx Termination Resistor Value).

However, in the conventional high-speed point-to-point interface method, a development step for detecting an optimal transmission condition must be performed in order to match impedances between devices. In addition, the conventional high-speed point-to-point interface method can not cope with a change in characteristics due to temperature or surrounding environment even if an optimum transmission condition is detected. Therefore, the conventional high-speed point-to-point interface scheme is very time consuming to reset the detected optimum transmission conditions as well as hardware access from the development stage.

The present invention solves the above problems and is configured as follows so that optimal transmission conditions between the timing controller 130 and the data drivers 150a to 150c can be automatically set.

FIG. 4 is a block diagram of a timing controller and data drivers according to an embodiment of the present invention. FIG. 5 is an equivalent circuit diagram illustrating a transmission line between a timing controller and a data driver. FIG. 7 is a diagram showing an example of an interrupt signal promised between the timing controller and the data drivers. FIG.

4 to 7, the timing controller 130 and the first to third data drivers 150a to 150c are connected by a high-speed point-to-point interface.

The timing controller 130 and the first data driver 150a are selected as an example of the high-speed point-to-point interface connected between the timing controller 130 and the first to third data drivers 150a to 150c The following is an explanation.

The transmitting terminal Tx of the timing controller 130 and the receiving terminal Rx of the first data driver 150a are connected to an EPI (Embedded Clock Point Interface) for transmitting / receiving data in a voltage form of differential swing level Respectively. A positive voltage is provided through EPI +, and a negative voltage is provided through EPI-. Termination resistors R _T for matching the impedance Zo on the transmission line are formed at the ends of the transmission terminal Tx of the timing controller 130 and the reception terminal Rx of the first data driver 150a.

The timing controller 130 transmits the first to third data packets SD # 1 to SD # 3 through the transmission line connected to the first to third data drivers 150a to 150c. The first to third data packets SD # 1 to SD # 3 are configured in the form of a clock pattern, a control signal CTR and a data signal DATA.

The interval in which the clock pattern signal is supplied is a period in which device definition is performed between the timing controller 130 and the first to third data drivers 150a to 150c. The period during which the control signal CTR is supplied is a period during which the device control is performed between the timing controller 130 and the first to third data drivers 150a to 150c. A period during which the data signal DATA is supplied is a period during which the data signal DATA is supplied from the timing controller 130 to the first to third data drivers 150a to 150c.

The timing controller 130 and the first to third data drivers 150a to 150c have the following configuration for automatically setting optimal transmission conditions.

The first to third data drivers 150a to 150c include first to third signal generators 155 to 157, respectively. The first signal generator 155 generates a logic low first interrupt signal IRQ1 and supplies the first interrupt signal IRQ1 to the timing controller 130. The second signal generator 156 generates a logic low second interrupt signal IRQ2 and supplies the second interrupt signal IRQ2 to the timing controller 130. The third signal generator 157 generates a logic low third interrupt signal IRQ3 and supplies the third interrupt signal IRQ3 to the timing controller 130. [ For example, the interrupt interval of the logic low in the first interrupt signal IRQ1 is set to 100 ms, the interrupt interval of the logic low in the second interrupt signal IRQ2 is set to 200 ms, the logic low in the third interrupt signal IRQ3, Can be set to 300 ms.

On the other hand, the first to third interrupt signals IRQ1 to IRQ3 are in a logic high state, which means a phase lock state. Conversely, the first to third interrupt signals IRQ1 to IRQ3 are in a logic low state, which means that a phase unlock state has occurred.

Thus, the first to third signal generators 155 to 157 generate and output the first to third interrupt signals IRQ1 to IRQ3, respectively, which are not limited to those shown in FIG. In the following description, it is explained that an interrupt signal has occurred for the sake of explanation that the state of the signal changes from logic high to low.

The timing controller 130 includes an interrupt signal analyzer 135 and an output signal controller 137. The interrupt signal analyzer 135 analyzes the signal generators 155 to 157 output from the first to third data drivers 150a to 150c and outputs the analysis results.

The first to third interrupt signals IRQ1 to IRQ3 output from the first to third signal generators 155 to 157 are used as an identification signal promised to the timing controller 130. [ For example, in order to detect the optimal transfer condition between the first to third data drivers 150a to 150c, the timing controller 130 controls the first to third interrupts 150a to 150c output from the first to third data drivers 150a to 150c, Observe the signals (IRQ1 to IRQ3) and adjust the parameters according to the impedance characteristics. At this time, the occurrence of the first to third interrupt signals IRQ1 to IRQ3 under a specific condition means that the currently changed conditions are not suitable for the first to third data drivers 150a to 150c.

The interrupt signal analyzer 135 regards that the first to third data drivers 150a to 150c are not set to optimal conditions when the first to third interrupt signals IRQ1 to IRQ3 are generated. The interrupt signal analyzer 135 outputs a signal so that the output signal controller 137 can detect an optimal transmission condition.

The output signal control unit 137 outputs the differential swing signal of the first to third data packets SD # 1 to SD # 3 output through the transmitting terminal Tx of its own in response to the signal output from the interrupt signal analyzing unit 135. [ Adjust the level (differential swing level). Also, the output signal controller 137 activates or deactivates the pre-emphasis in response to the signal output from the interrupt signal analyzer 135. The output signal controller 137 controls the use of the equalizer included in the first to third data drivers 150a to 150c in response to the signal output from the interrupt signal analyzer 135. [ In addition, the output signal controller 137 controls the terminal resistors R _T included in the first through third data drivers 150a through 150c, as well as the terminal resistors R _{T thereof} , corresponding to the signals output from the interrupt signal analyzer 135. [ (R _T ).

When the optimal transmission condition is detected between the timing controller 130 and the first to third data drivers 150a to 150c, the timing controller 130 controls the first to third data drivers 150a to 150c Phase lock is performed to fix the currently set conditions so that optimum transmission conditions are maintained.

The timing controller 130 performs the following operations to detect optimal transmission conditions with respect to the first to third data drivers 150a to 150c.

The interrupt signal analyzing unit 135 analyzes whether the first to third interrupt signals IRQ1 to IRQ3 are generated from the first to third signal generators 155 to 157. [ For example, the interrupt signal analyzing unit 135 may determine that an interrupt has occurred when the first to third interrupt signals IRQ1 to IRQ3 are switched from logic high to logic low. The analysis of whether or not an interrupt signal is generated is performed in a section in which a clock pattern signal is supplied. The timing control unit 130 can distinguish the data driving unit in which the phase locking is already performed and the data driving unit in which the phase locking is not yet performed by the interrupt signal analyzing unit 135. [

The output signal controller 137 controls the differential swing level, the pre-emphasis, the equalizer, and the termination resistor value to detect the optimum transmission condition for the data driver that is not phase-locked. (Tx Termination Resistor Value).

Hereinafter, an operation for automatically setting an optimal transmission condition between the timing controller 130 and the first to third data drivers 150a to 150c will be schematically described.

FIG. 8 is an exemplary view of an optimum transmission condition detection method by changing a differential swing level, FIG. 9 is an exemplary view of an optimal transmission condition detection method by changing a resistance value of a terminating resistor, and FIG. And FIG.

As shown in FIGS. 1 to 8, the timing controller 130 can detect the optimal transmission condition by changing the differential swing level. For example, the timing controller 130 detects an optimal transmission condition by raising the differential swing level of a data packet supplied through a transmission line having a higher impedance than a differential swing level of a data packet supplied through a transmission line having a low impedance .

The case where the impedance formed in the transmission line between the timing controller 130 and the first data driver 150a is the lowest and the impedance formed in the transmission line between the timing controller 130 and the third data driver 150c is the highest, Respectively.

The timing controller 130 sets the first data packet SD # 1 to the first differential swing level DIFF1 and supplies the first data packet SD # 1 to the first data driver 150a. The timing controller 130 sets the second data packet SD # 2 to the second differential swing level DIFF2 and supplies the second data packet SD # 2 to the second data driver 150b. The timing controller 130 sets the third data packet SD # 3 to the third differential swing level DIFF3 and supplies the third data packet SD # 3 to the third data driver 150c.

As shown in FIGS. 1 to 9, the timing controller 130 can detect an optimal transmission condition by changing its terminal resistor value. For example, the terminating resistor R _T of the timing controller 130 may include resistors R1 to Rn and switches SW1 to SWn connected in series.

According to this configuration, the terminal resistor R _T of the timing controller 130 changes the resistance value of the resistors R1 to Rn in response to the switch signal CN. The termination resistors included in the first to third data drivers 150a to 150c may also be configured as shown in FIG. 9 to change the resistance value. On the other hand, the configuration shown in FIG. 9 is intended only to help understand the variable resistor, but it is also possible to change the resistance value of the terminating resistor R _{T at the} transmitting / receiving end with another configuration.

As shown in FIGS. 1 to 10, the timing controller 130 can detect the optimal transmission condition by changing the preamplification. For example, the timing controller 130 deactivates the preamplification of a data packet supplied through a transmission line having a low impedance and activates a preamplification of a data packet supplied through a transmission line having a high impedance, Can be detected.

The impedance formed in the transmission line between the timing controller 130 and the first and second data drivers 150a and 150b is low and the impedance formed in the transmission line between the timing controller 130 and the third data driver 150c is high The following is an explanation.

The timing controller 130 deactivates the preamplifier for the first data packet SD # 1 and supplies it to the first data driver 150a. The timing controller 130 deactivates the preamplifier for the second data packet SD # 2 and supplies it to the second data driver 150b. The timing controller 130 activates the preamplifier Pemp for the third data packet SD # 3 and supplies it to the third data driver 150c.

Meanwhile, the first to third data drivers 150a to 150c include an equalizer for improving the quality of the attenuated signal. The transmission line between the timing controller 130 and the first to third data drivers 150a to 150c can be changed according to the usage environment. Accordingly, the timing controller 130 can detect optimal transmission conditions by activating or deactivating the equalizers included in the first to third data drivers 150a to 150c.

Hereinafter, a process of detecting an optimal transmission condition between the timing controller 130 and the first to third data drivers 150a to 150c will be described.

FIG. 11 is an exemplary diagram for explaining a process of detecting an optimal transmission condition, and FIG. 12 is an exemplary diagram for explaining that an optimal transmission condition can be detected during a vertical blank period.

The timing controller 130 controls the first to third data drivers 150a to 150c in such a manner that the differential swing level is increased and the preamplifier is activated and then the differential swing level is lowered or the preamp is deactivated. Impedance matching can be performed.

For example, the timing controller 130 activates the preamplifier Pemp for the third data packet SD # 3 and sets it as the third differential swing level DIFF3 as shown in FIG. 11A, And supplies it to the driving unit 150c. At this time, it is assumed that the third interrupt signal IRQ3 is not generated from the third data driver 150c.

Then, the timing controller 130 activates the preamplifier Pemp for the third data packet SD # 3 as shown in FIG. 11 (b), and sets the third differential swing level DIFF3 to the second differential swing level (DIFF2) and supplies it to the third data driver 150c. At this time, it is assumed that the third interrupt signal IRQ3 is not generated from the third data driver 150c.

11C, the timing controller 130 deactivates the preamplifier for the third data packet SD # 3 and sets the second differential swing level DIFF2 to the first differential swing level DIFF1, And supplies it to the third data driver 150c. At this time, it is assumed that the third interrupt signal IRQ3 is not generated from the third data driver 150c.

However, if the third interrupt signal IRQ3 is generated from the third data driver 150c, the timing controller 130 regards FIG. 11 (b) as the optimum transfer condition. Thereafter, the preamplifier Pemp for the third data packet SD # 3 is activated to be reset to the second differential swing level DIFF2 and supplied to the third data driver 150c.

As described above, the timing controller 130 controls the first to third data drivers 150a to 150c according to whether or not the first to third data drivers 150a to 150c can converge the changed transfer conditions according to the occurrence of the interrupt signals IRQ1 to IRQ3, Change one or more variables used in matching. The timing controller 130 detects an optimal transmission condition with respect to the first through third data drivers 150a through 150c through the above process and outputs a phase lock signal so that the optimal transmission condition is maintained when the optimal transmission condition is detected. .

However, even if the optimum transmission condition is detected between the timing controller 130 and the first to third data drivers 150a to 150c, the characteristics may vary depending on the temperature, the surrounding environment, and the like (environment variables). Accordingly, the timing controller 130 may generate the interrupt signals IRQ1 to IRQ3 generated from the first to third data drivers 150a to 150c for the Nth (N is an integer equal to or greater than 1) vertical blank interval VB as shown in FIG. 12 And can perform an operation of observing and updating the optimum transmission condition. At this time, the timing controller 130 repeats a series of processes such as outputting a clock pattern and changing various variables in order to observe the states of the first to third data drivers 150a to 150c.

Hereinafter, a method for automatically detecting an optimum transmission condition between the timing control section and the data driving section will be described.

FIG. 13 is a flowchart of a method of detecting an optimal transmission condition according to the first embodiment of the present invention, and FIG. 14 is a flowchart of a method of detecting an optimal transmission condition according to the second embodiment of the present invention.

As shown in FIG. 13, when power is supplied to the display device (Power On), an initial operation is performed between the timing controller and the data driver (S110).

First, the timing controller changes the differential swing level of the data packet to be supplied to the data driver (EPI Differentail Swing Level Change) (S120).

Next, the timing controller changes the termination resistor value of its transmitting end and the terminating resistor value of the receiving end of the data driving unit (Rx. & Tx Termination Resistor Change) (S130).

Next, the timing controller activates or deactivates the preamplification of the data packet to be supplied to the data driver (Tx. Pre-emphasis Enable / Disable) (S140).

Next, the timing controller activates or deactivates the equalizer included in the data driver (Rx. Equalizer Enable / Disable) (S150).

Next, the timing control unit judges whether or not an interrupt signal is generated from the data driver (Lock = High) (S160). Here, if the interrupt signal is logic high (YES), no interrupt has occurred. On the other hand, if the interrupt signal is not logic high (No), an interrupt has occurred.

Next, when the interrupt signal corresponding to logic high is held from the data driver (YES), the timing control unit repeats the above step three times (S170). If the above step is repeated three times (YES), the process of detecting the optimal condition is terminated.

Alternatively, when an interrupt signal corresponding to a logic low, which is not a logic high, is generated from the data driver (No), the differential swing level is changed from a step S120 to a step S150 for activating or deactivating the equalizer Try changing the variable.

In the above description, the step of changing the differential swing level (S120) to activating or deactivating the equalizer (S150) is repeated three times. However, the above changing step can be changed by repeating from 1 time to N (N is an integer of 2 or more) times.

In the above description, it is assumed that the condition is reset according to whether or not an interrupt signal has been generated after sequentially changing the differential swing level (S120) from the step of activating or deactivating the equalizer (S150) . However, in the following, a method of changing the condition by referring to whether or not an interrupt signal has occurred in each step will be described as an example.

As shown in FIG. 14, when power is supplied to the display device (Power On), an initial operation is performed between the timing controller and the data driver (S110).

First, the timing controller changes the differential swing level of the data packet to be supplied to the data driver (EPI Differentail Swing Level Down) (S220).

Next, the timing control unit judges whether an interrupt signal is generated from the data driving unit (Lock = High) (S230). Here, if the interrupt signal is logic high (YES), no interrupt has occurred. On the other hand, if the interrupt signal is logic low rather than logic high (No), an interrupt has occurred.

If the interrupt signal is logic high (YES), the process proceeds to the next step S240. If the interrupt signal is not logic high (No), the timing controller changes the differential swing level of the data packet to be supplied to the data driver (EPI Differentail Swing Level Up) (S235).

Next, the timing controller changes the termination resistor value of the transmitting terminal of the transmitting terminal and the terminating resistor value of the receiving terminal of the data driving unit (Rx. & Tx Termination Resistor Change) (S240). At this time, the timing control unit may change only one of the terminal resistor value of the transmitting terminal of the transmitting terminal and the terminal resistor value of the receiving terminal of the data driving unit.

Next, the timing control unit judges whether an interrupt signal is generated from the data driving unit (Lock = High) (S250).

If the interrupt signal is logic high (YES), the process proceeds to the next step S260. Alternatively, if the interrupt signal is not logic high but is logic low (No), the timing controller changes the termination resistor value of its transmitting terminal and the terminating resistor value of the receiving terminal of the data driving unit (Rx. & Tx. (S255).

Next, the timing control unit deactivates the preamble of the data packet to be supplied to the data driver (Tx. Pre-emphasis Disable) (S260).

Next, the timing control unit judges whether or not an interrupt signal is generated from the data driver (Lock = High) (S270).

If the interrupt signal is logic high (YES), the process proceeds to the next step S280. Otherwise, if the interrupt signal is not logic high (No), the timing controller activates the preamplification of the data packet to be supplied to the data driver (S275).

Next, the timing controller deactivates the equalizer included in the data driver (Rx. Equalizer Disable) (S280).

Next, the timing control unit judges whether or not an interrupt signal is generated from the data driving unit (Lock = High) (S290).

If the interrupt signal is logic high (YES), the process of detecting the optimum condition is ended. Alternatively, if the interrupt signal is not logic high (No), the timing controller activates the equalizer included in the data driver (Rx. Equalizer Enable) (S295). Then, the process of detecting the optimal transmission condition is terminated.

In the first and second embodiments, the optimum transmission conditions are (1) a differential swing level change, (2) a resistance value change of the terminating resistor, (3) activation or deactivation of preamplification, and (4) As shown in Fig. However, the order of (1) to (4) is not limited to this, and can proceed at random. On the other hand, when the "Lock" is again set to logic high by the above step, the changed value is applied and the data packet corresponding to the optimum transmission condition is output.

As described above, the present invention provides a display device having a timing controller and a data driver connected to each other by a high-speed point-to-point interface system capable of automatically transmitting optimum transmission conditions in response to impedance characteristics of each transmission line, . The present invention also provides a display device having a timing controller and a data driver connected by a high-speed point-to-point interface system capable of automatically changing transmission conditions in response to a change in characteristics due to temperature, surrounding environment, and a driving method thereof .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. It is to be understood that within the scope of the appended claims all such changes and modifications as come within the scope of the appended claims are intended to be embraced therein.

130: timing controller 140: gate driver
150: Data drivers 160: Display panel
155 to 157: Signal generator IRQ1 to IRQ3: Interrupt signal
135: Interrupt signal analyzer 137: Output signal controller

Claims (10)

Display panel;
A gate driver for supplying a gate signal to the display panel;
A data driver for supplying a data signal to the display panel; And
And a timing controller for controlling the data drivers to observe the interrupt signal generated from the data driver and automatically converge the optimal transmission condition corresponding to the impedance characteristic of each transmission line connected to the data driver. The method according to claim 1,
Wherein the timing controller changes a differential swing level of a data packet to be supplied to the data drivers in accordance with an impedance characteristic of each transmission line connected to the data drivers. The method according to claim 1,
Wherein the timing controller activates or deactivates a preamplifier for a data packet to be supplied to the data drivers in accordance with an impedance characteristic of each transmission line connected to the data drivers. The method according to claim 1,
Wherein the timing controller activates or deactivates the equalizer included in the data drivers according to an impedance characteristic of each transmission line connected to the data drivers. The method according to claim 1,
Wherein the timing controller changes at least one of a termination resistor value of the data driving units and a termination resistor value of the data driving units in accordance with an impedance characteristic of each transmission line connected to the data driving units. The method according to claim 1,
The data drivers generate an interrupt signal,
Wherein the timing control unit changes the differential swing level of the data packet to be supplied to the data drivers in response to the occurrence of the interrupt signal,
The resistance value of the terminating resistor of the transmitting end of the timing control unit and the resistance value of the terminating resistor of the receiving end of the data driving units are respectively changed,
The preamplification of the data packet to be supplied to the data drivers is activated or deactivated respectively,
And activates or deactivates the equalizers included in the data drivers. A method of driving a display apparatus having a timing controller and a data driver connected by a point-to-point interface,
Changing a differential swing level of a data packet to be supplied to the data driver;
Changing a resistance value of the terminating resistor of the transmitting end of the timing control unit and a resistance value of the terminating resistor of the receiving end of the data driving unit;
Activating or deactivating a preamplification of a data packet to be supplied to the data driver; And
And activating or deactivating the equalizer included in the data driver. 8. The method of claim 7,
When the interrupt signal is generated from the data driver after the differential swing level is lowered, the differential swing level is increased,
Activating the preamplifier when an interrupt signal is generated from the data driver after deactivating the preamplifier,
And activating the equalizer when an interrupt signal is generated from the data driver after the equalizer is deactivated. 8. The method of claim 7,
The timing control unit
Wherein the controller is configured to automatically change an optimum transmission condition according to an impedance characteristic of each transmission line connected between the data driver and a change condition for each of the data driver in response to an interrupt signal generated from the data driver. Way. 10. The method of claim 9,
The timing control unit
The present invention is characterized by fixing the currently set condition after the optimal transmission condition is detected and then observing the interrupt signal generated from the data driver for every N (N is an integer of 1 or more) vertical blank interval and updating the optimal transmission condition And a driving method of the display device.

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