KR20120065570A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to individually control a swing level of signals which are transmitted to a source drive IC from a timing controller. CONSTITUTION: A timing controller outputs a signal through a comparator on a transmitter side. One or more source drive ICs receive a signal of the timing controller through the comparator on a transmitter side. Source drive ICs supply a data voltage to data lines of a display panel. A memory stores option information for controlling a swing level of output signals. The memory supplies option information to the timing controller.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device capable of individually controlling a swing level of signals transmitted to source drive ICs.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in portable information equipment, office equipment, computer, etc., and is also rapidly replaced by a cathode ray tube.

A liquid crystal display device includes a plurality of source drive integrated circuits (“ICs”) for supplying data voltages to data lines of a liquid crystal display panel, and gate pulses (or scan pulses) to gate lines of the liquid crystal display panel. ) And a plurality of gate drive ICs for sequentially supplying the < RTI ID = 0.0 >

The timing controller supplies digital video data, a clock signal for sampling digital video data, a control signal for controlling the operation of the source drive ICs, and the like through an interface such as mini LVDS (Low Voltage Differential Signaling). do. The source drive ICs convert digital video data input in series from a timing controller into a parallel scheme, and then convert an analog data voltage using a gamma compensation voltage to supply data lines.

As shown in FIG. 1, when the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 are connected in a multi-drop method through a mini low voltage differential signaling (LVDS) interface, timing may be used. Controls the R data transfer wiring, the G data transfer wiring, the B data transfer wiring, the output timing of the source drive ICs and the operation timing of the polarity conversion operation between the controller TCON and the source drive ICs SIC # 1 to SIC # 8. Many wirings are needed, including control wiring and clock transmission wiring. For example, in the mini-LVDS interface, RGB data transmission is performed by transmitting the RGB digital video data and the clock as differential signal pairs. Therefore, the timing controller (TCON) and the source are simultaneously transmitted when the odd and even data are simultaneously transmitted. At least 14 wires are required between the drive ICs SIC # 1 to SIC # 8 to transmit RGB data. If the RGB data is 10bit data, 18 wires are needed. Therefore, since a plurality of wires must be formed in the source printed circuit board (PCB) mounted between the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8, it is difficult to reduce the width thereof.

As shown in FIG. 2, the present applicant connects the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 in a point-to-point manner to connect the timing controller TOCN and the source drive ICs (see FIG. 2). A new signal transmission protocol for minimizing the number of wires between SIC # 1 to SIC # 8 and stabilizing signal transmission is disclosed in Korean Patent Application No. 10-2008-0127458 (2008-12-15), US Application No. 12 / 543,996 (2009- 08-19), Korean Patent Application 10-2008-0127456 (2008-12-15), US Application 12 / 461,652 (2009-08-19), Korean Patent Application 10-2008-0132466 (2008-12-23), Suggested in US Application 12 / 537,341 (2009-08-07) and the like. In FIG. 2, "P1 to P8" is a data wire pair in which the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 are connected in series.

1 and 2, the distance between the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 depends on the position of the source drive ICs SIC # 1 to SIC # 8. As a result, since the wiring resistance between the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 is different, it is received by the source drive ICs SIC # 1 to SIC # 8 due to the voltage drop difference. The swing level of the signal may vary.

The timing controller TCON may support an option pin for adjusting the swing level of the voltage output through the transmitter comparator. This option pin is known as the RMLVDS pin.

In FIG. 1, when the resistor of the RMLVDS pin of the timing controller TCON is connected to the ground voltage source GND, the current of the transmitter comparator Tx built in the timing controller TCON increases to increase the source drive ICs SIC # 1 to SIC. You can adjust the swing level of the signals sent to # 8). However, as shown in FIG. 1, since the source drive ICs SIC # 1 to SIC # 8 are commonly connected to the timing controller TCON, swings of signals transmitted to the source drive ICs SIC # 1 to SIC # 8 are performed. The level can be controlled equally, but the swing levels of the signals cannot be controlled individually.

As shown in FIG. 2, the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 are connected in a point-to-point manner, and the RMLVDS pins are connected to the timing controller TCON by the number of output channels of the timing controller TCON. Can provide additional. In this case, the swing level of the signals transmitted to the source drive ICs SIC # 1 to SIC # 8 can be individually controlled, but the circuit configuration of the timing controller TCON is increased due to the increase in the number of pins of the timing controller TCON. Complicated and large in size. Therefore, when the timing controller TCON and the source drive ICs SIC # 1 to SIC # 8 are connected in a point-to-point manner as shown in FIG. 2, the method of additionally installing the RMLVDS pins to the timing controller TCON is applied. It is not.

The present invention provides a liquid crystal display that can individually control the swing level of signals transmitted from the timing controller to the source drive ICs without adding the RMLVDS pins to the timing controller.

The liquid crystal display of the present invention includes a timing controller for outputting a signal through a transmitter comparator; One or more source drive ICs receiving a signal from the timing controller through a receiver comparator to supply data voltages to data lines of the display panel; And a memory configured to store option information for controlling the swing level of each of the output signals of the timing controller and to supply the option information to the timing controller. The timing controller adjusts the swing level of each of the output signals by adjusting the number of turn-on of the switch elements according to the option information, including each switch element for supplying current to the transmitter comparator.

The present invention stores option information for individually controlling the swing level of each of the signals output from the timing controller in a memory in advance, and controls on / off switch elements for adjusting current according to the option information. Thus, the present invention can individually control the swing level of signals transmitted from the timing controller to the source drive ICs without adding RMLVDS pins to the timing controller.

1 is a diagram illustrating a timing controller and source drive ICs connected in a multi-drop manner.
2 shows a timing controller and source drive ICs connected in a point-to-point manner.
3 is a diagram illustrating a liquid crystal display according to a first embodiment of the present invention.
4 is a diagram illustrating an external clock and data transmitted between the timing controller and the source drive IC shown in FIG.
FIG. 5 is a diagram illustrating a transmitter comparator embedded in a timing controller and a receiver comparator embedded in a source drive IC.
FIG. 6 is a circuit diagram illustrating a transmitter current adjusting circuit of the timing controller of FIG. 3.
7 is a waveform diagram illustrating an example of individually controlling swing levels of signals output from a timing controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Referring to FIG. 3, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel LCP, a timing controller TCON, a memory EEPROM, and one or more source drive ICs SIC # 1 to SIC # 8. And gate drive ICs (GIC).

The liquid crystal layer is formed between the substrates of the liquid crystal display panel LCP. The liquid crystal display panel LCP includes liquid crystal cells Clc arranged in a matrix by a cross structure of the data lines DL and the gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and a storage capacitor Cst is formed on the TFT array substrate of the liquid crystal display panel LCP. The liquid crystal cells Clc are driven by an electric field between the pixel electrode supplied with the data voltage through the TFT and the common electrode supplied with the common voltage Vcom. The gate electrode of the TFT is connected to the gate line GL, and the drain electrode thereof is connected to the data line DL. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the data voltage from the data line DL to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, a common electrode, and the like are formed on the color filter substrate of the liquid crystal display panel LCP. A polarizing plate is attached to each of the TFT array substrate and the color filter array substrate of the liquid crystal display panel LCP, and an alignment film for setting the pre-tilt angle of the liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc may be formed between the TFT array substrate and the color filter array substrate of the liquid crystal display panel LCP.

The liquid crystal display panel (LCP) is a vertical field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, or a horizontal field driving method such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. Can be implemented. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller (TCON) enables vertical / horizontal synchronization signals (Vsync, Hsync) and external data from an external host system (not shown) through interfaces such as Low Voltage Differential Signaling (LVDS) interface and Transition Minimized Differential Signaling (TMDS) interface. An external timing signal such as a signal Data Enable (DE) and a dot clock CLK is input. The timing controller TCON is connected in series to each of the source drive ICs SIC # 1 to SIC # 8 through a point-to-point interface.

As shown in FIG. 4, the timing controller TCON generates the difference signal pairs EPI + and EPI- from the external clock signal CLK and the RGB digital video data, and generates the source drive ICs SIC through the data wire pairs P1 to P8. # 1 to SIC # 8). In addition, the timing controller TCON may generate control data as a difference signal pair and transmit the control data to the source drive ICs SIC # 1 to SIC # 8 through the data wire pairs P1 to P8. The control data includes source control data for controlling the output timing of the data voltages output from the source drive ICs SIC # 1 to SIC # 8, polarities of the data voltages, and the like. In addition, the control data may include gate control data for controlling an operation timing of the gate drive IC (GIC). The signal transmission protocol between the timing controller (TCON) and the source drive ICs (SIC # 1 to SIC # 8) is described in Korean Patent Application No. 10-2008-0127458 (2008-12-15), US Application No. 12 / 543,996 (2009-08). -19), Republic of Korea Patent Application 10-2008-0127456 (2008-12-15), United States Application 12 / 461,652 (2009-08-19), Republic of Korea Patent Application 10-2008-0132466 (2008-12-23), United States Application 12 / 537,341 (2009-08-07) et al.

The timing controller TCON includes a transmitter current adjusting circuit as shown in FIG. 6 connected to the RMLVDS pin for adjusting the swing level of the output channels. The memory EEPROM stores option information for adjusting the output current of the transmitter current adjusting circuit of the timing controller TCON. The memory EEPROM may be selected as a nonvolatile memory, for example, EEPROM (Electrically Erasable Programmable Read-Only Memory) so that the option information may be updated. The timing controller TCON reads option information from the memory EEPROM and individually adjusts swing levels of signals output through each of the output channels.

The source drive ICs SIC # 1 to SIC # 8 are connected in a point-to-point form with the timing controller TCON through the data wire pairs P1 to P8. Each of the source drive ICs SIC # 1 to SIC # 8 may be connected to data lines of a liquid crystal display panel LCP through a chip on glass (COG) process or a tape automated bonding (TAB) process.

The source drive ICs SIC # 1 to SIC # 8 receive RGB digital video data, an external clock signal CLK, control data, and the like through the data wire pairs P1 to P8 through the receiver comparator Rx shown in FIG. 5. Get input. The source drive ICs SIC # 1 to SIC # 8 convert the frequency of the received external clock signal CLK into a RGB digital signal through a phase locked loop (PLL) or a delay locked loop (DLL). A number of bits of video data x two internal clock signals are generated, and RGB digital video data is sampled and converted into a parallel data system according to the internal clock signal.

The source drive ICs SIC # 1 to SIC # 8 decode the control data input through the data wire pair by code mapping to restore the source control data and the gate control data. The source drive ICs SIC # 1 to SIC # 8 convert the RGB digital video data, which is converted into a parallel scheme according to the source control data, into positive / negative analog data voltages, thereby converting the data lines of the liquid crystal display panel LCP. Supply to (DL). The source drive ICs SIC # 1 to SIC # 8 may transmit gate control data to one or more of the gate drive ICs GIC.

The gate drive IC (GIC) may be directly connected to the gate lines of the TFT array substrate of the liquid crystal display panel through a TAP process or may be directly formed on the TFT array substrate of the liquid crystal display panel (LCP) by a gate in panel (GIP) process. . The gate drive IC GIC is sequentially supplied with the gate pulse to the gate lines GL according to the gate control data supplied from the timing controller TCON or supplied through the source drive ICs SIC # 1 to SIC # 8. Supply. The gate control data includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the start horizontal line at which the scan starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate drive IC GIC to sequentially shift the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive IC GIC.

FIG. 5 is a diagram illustrating a transmitter comparator Tx built into the timing controller TCON and a receiver comparator Rx built into the source drive ICs SIC # 1 to SIC # 8.

The data line pair ZO is connected between the transmitter / receiver comparators Tx and Rx. Two terminal resistors RT are connected between the one side data line ZO and the other side data line ZO of the data line pair ZO, and the terminal voltage Vterm is supplied to a node between the terminal lines. Can be. The terminal voltage Vterm may be set to about 1.2V.

6 is a circuit diagram illustrating a transmitter current adjusting circuit of the timing controller TCON.

Referring to FIG. 6, the transmitter current adjusting circuit of the timing controller TCON includes an operational amplifier AMP, a plurality of transistors M1 to M2, Q1 to Q4, and a plurality of switch elements S1 to S4. do. The transistors M1 to M2 and Q1 to Q4 and the switch elements S1 to S4 may be implemented with an n type MOSFET (Metal Oxide Semiconductor Field-Effect Transistor).

The reference voltage VREF is applied to one input terminal of the operational amplifier AMP. The other input terminal of the operational amplifier AMP is connected to a node between the source electrode of the first transistor M1 and the variable resistor R. The output of the operational amplifier AMP is applied to the gate electrodes of the transistors M1 to M2 and Q1 to Q4.

The high potential power voltage VDD is supplied to the drain electrodes of the first and second transistors M1 to M2. The high potential power voltage VDD may be supplied to the drain electrodes of the third to sixth transistors Q1 to Q4 through the switch elements S1 to S4. The variable resistor R is connected between the source electrode of the first transistor M1 and the ground voltage source GND through the RMLVDS pin. Source electrodes of the second to sixth transistors M2 and Q1 to Q4 are connected to a current supply terminal of a transmission comparator of the timing controller TCON.

The switch elements S1 to S4 are connected between the high potential power supply voltage source VDD and the drain terminals of the third to sixth transistors Q1 to Q4 to selectively select the third to sixth transistors Q1 to Q4. Supplies the high potential supply voltage (VDD). The switch elements S1 to S4 are turned on / off according to the option information previously stored in the memory EEPROM.

When the variable resistor R is connected to the RMLVDS pin of the timing controller TCON, the reference current IREF is changed according to the resistance value of the variable resistor R. The output current of the transmitter comparator Tx of the timing controller TCON varies in proportion to the reference current IREF. Therefore, the output of the transmitter comparator Tx of the timing controller TCON may be adjusted according to the resistance value of the variable resistor R. FIG.

The option information stored in the memory EEPROM may include option values for variously adjusting the output swing level of the transmitter comparator Tx of the timing controller TCON. For example, the option information may include first to second option values. The first option value may be switch control information for adjusting the output swing level of the transmitter comparator Tx to 200 mV. The second option value may be switch control information for adjusting the output swing level of the transmitter comparator Tx to 250 mV, and the third option value may be switch control information for adjusting the output swing level of the transmitter comparator Tx to 300 mV. Can be. The fourth option value may be switch control information for adjusting the output swing level of the transmitter comparator Tx to 350 mV.

The timing controller TCON turns off the first to fourth switch elements S1 to S4 in response to the first option value, and supplies a current of I = I1 to the transmitter comparator Tx in FIGS. 3 and 7. In FIG. 7, the swing level of a signal output through the fourth and fifth wire pairs P4 and P5 having the shortest wire length may be adjusted to 200 mV (V1 in FIG. 7). The timing controller TCON turns on the first switch element S1 and turns off the second to fourth switch elements S2 to S4 in response to the second option value, thereby causing a current of I = I1 + I2. Is supplied to the transmitter comparator Tx to adjust the swing level of the signal output through the third and sixth wire pairs P3 and P6 in FIGS. 3 and 7 to 250 mV (V2 in FIG. 7). The timing controller TCON turns on the first and second switch elements S1 and S2 and turns off the third and fourth switch elements S3 and S4 in response to the third option value. By supplying a current of I1 + I2 + I3 to the transmitter comparator Tx, the swing level of the signal output through the second and seventh wire pairs P2 and P7 in FIGS. 3 and 7 is 300 mV (V3 in FIG. 7). Can be adjusted. The timing controller TCON turns on the first to third switch elements S1 to S3 and turns off the fourth switch elements S4 in response to the fourth option value, so that I = I1 + I2 +. By supplying a current of I3 + I4 to the transmitter comparator Tx, the swing level of the signal output through the first and eighth wire pairs P2 and P7 having the longest wiring length in FIG. 3 and FIG. 7 is 350 mV (FIG. 7 to V4). In addition, the timing controller TCON turns on all of the first to fourth switch elements S1 to S4 in response to the fifth option value to transmit current of I = I1 + I2 + I3 + I4 + I5 to the transmitter comparator. The swing level of the signal output through the first and eighth wire pairs P2 and P7 in FIGS. 3 and 7 may be adjusted to 400 mV by supplying the signal to Tx. Therefore, according to the present invention, the swing levels of the output signals of the timing controller TCON are individually controlled to adjust the swing levels in proportion to the lengths of the data wire pairs P1 to P8. The difference in length may compensate for the difference in signal attenuation of the timing controller TCON.

According to another exemplary embodiment of the present invention, the timing controller TCON is omitted by omitting the RMLVDS pin, the resistor, and the operational amplifier AMP in FIG. The swing level of each of the signals output from the () may be adjusted. In this case, the swing level variation of the output signal of the timing controller TCON may be greater than in the above-described embodiment.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TCON: Timing Controllers SIC: Source Drive ICs
GIC: Gate Drive IC Tx: Transmitter Comparator
Rx: Receiver Comparator M1 ~ M2, Q1 ~ Q4: Transistor
S1 ~ S4: Switch element

Claims (3)

A timing controller for outputting a signal through a transmitter comparator;
One or more source drive ICs receiving a signal from the timing controller through a receiver comparator to supply data voltages to data lines of the display panel; And
A memory for storing option information for controlling the swing level of each of the output signals of the timing controller and supplying the option information to the timing controller,
The timing controller,
And a switch level for controlling the swing level of each of the output signals by adjusting the number of the switch elements turned on according to the option information, including each switch element for supplying current to the transmitter comparator. .
The method of claim 1,
The timing controller,
RMLVDS pin;
A variable resistor coupled between the RMLVDS pin and a ground voltage source;
An operational amplifier to which a reference voltage is input;
A first transistor including a gate electrode to which an output of the operational amplifier is input, a drain electrode to which a high potential power voltage is input, and a source electrode connected to the variable resistor;
A second transistor including a gate electrode to which an output of the operational amplifier is input, a drain electrode to which the high potential power voltage is input, and a source electrode connected to a current supply terminal of the transmitter comparator;
A third transistor including a gate electrode to which an output of the operational amplifier is input, a drain electrode to which the high potential power voltage is input, and a source electrode connected to a current supply terminal of the transmission comparator; And
And a first switch element connected to the source electrode of the third transistor and turned on / off according to the option information to supply the high potential power voltage to the third transistor.
The method of claim 1,
The timing controller,
A fourth transistor including a gate electrode to which an output of the operational amplifier is input, a drain electrode to which the high potential power voltage is input, and a source electrode connected to a current supply terminal of the transmitter comparator;
A second switch element connected to the source electrode of the fourth transistor and turned on / off according to the option information to supply the high potential power voltage to the fourth transistor;
A fifth transistor including a gate electrode to which an output of the operational amplifier is input, a drain electrode to which the high potential power voltage is input, and a source electrode connected to a current supply terminal of the transmission comparator;
A third switch element connected to the source electrode of the fifth transistor and turned on / off according to the option information to supply the high potential power voltage to the fifth transistor;
A sixth transistor including a gate electrode to which an output of the operational amplifier is input, a drain electrode to which the high potential power voltage is input, and a source electrode connected to a current supply terminal of the transmission comparator; And
And a fourth switch element connected to the source electrode of the sixth transistor and turned on / off according to the option information to supply the high potential power voltage to the sixth transistor.

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