KR101696477B1 - Inverter and liquid crystal display using the same - Google Patents

Abstract

The present invention relates to an inverter circuit and a liquid crystal display device using the same, wherein the inverter circuit is turned on when a digital input signal inputted through an input terminal is transitioned from a high logic level to a low logic level, Type first p-type transistor; A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor; A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal; A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level; A second n-type transistor forming a current path between the low potential power source and the first n-type transistor; And a third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit and a liquid crystal display device using the same,

The present invention relates to an inverter circuit and a liquid crystal display using the same.

In a high-speed digital transmission system, a delay cell of an integrated circuit (hereinafter referred to as an " IC ") and a current starved inverter are mainly used in a voltage controlled oscillator (VCO). An example of a conventional current blocking inverter is shown in FIG.

Referring to Fig. 1, the current interruption inverter circuit includes p-type transistors MP1 and MP2 and n-type transistors MN1 and MN2. Each of the transistors is implemented as a metal oxide semiconductor field effect transistor (MOSFET).

The gate electrodes of the first p-type transistor MP1 and the first n-type transistor MN1 are connected in common to the input terminals. A digital input signal Vin is input to the input terminal. The source electrode of the first p-type transistor MP1 is connected to the drain electrode of the second p-type transistor MP2, and the drain electrode of the first p-type transistor MP1 is connected to the output terminal. The output signal Vout generated as the inverted signal of the input signal is output to the output terminal as shown in Figs. A load capacitor (C _L ) is connected to the output terminal. A first bias voltage Vbiasp is input to the gate electrode of the second p-type transistor MP2. The source electrode of the second p-type transistor MP2 is supplied with the high-potential power supply voltage Vcc.

The source electrode of the first n-type transistor MN1 is connected to the drain electrode of the second n-type transistor MN2, and the drain electrode of the first n-type transistor MN1 is connected to the output terminal. A second bias voltage Vbiasn is input to the gate electrode of the second n-type transistor MN2. A ground voltage GND is supplied to the source electrode of the second p-type transistor MP2.

When the digital input signal Vin changes from a low logic level to a high logic level, the first n-type transistor MN1 is turned on as shown in FIG. At this time, since the second n-type transistor MN2 is kept on by the second bias voltage Vbiasn, the voltage of the load capacitor C _L connected to the output terminal is lower than the voltage of the first and second n-type transistors MN1 , MN2) to the ground voltage source through the source and drain electrodes. When the digital input signal Vin changes from a low logic level to a high logic level, the current i flows through the n-type transistors MN1 and MN2.

When the digital input signal Vin changes from a high logic level to a low logic level, the first p-type transistor MP1 is turned on as shown in Fig. At this time, since the second p-type transistor MP2 is kept ON by the first bias voltage Vbiasp, the voltage of the load capacitor C _L connected to the output terminal is lower than the voltage of the first and second p-type transistors MP1 , MP2 of the source and drain electrodes.

In order to increase the slew rate (SR) of the current interruption inverter as shown in FIG. 1, the capacity of the load capacitor C _L must be reduced or the constant current i must be increased. However, since the load capacitor C _L is determined according to the load connected to the output terminal, if the load is fixed like the display device, it is impossible to reduce the capacity. In addition, if the constant current (i) is increased, the power consumption (P _total ) increases as shown in Equation (2). Equations (1) and (2) below represent the slew rate (SR) and power consumption (P _total ).

Here, f is the transition frequency of the digital input signal Vin. P _static is static power consumption, and P _dynamic is dynamic power consumption.

The present invention provides an inverter circuit for increasing the slew rate without increasing power consumption and a liquid crystal display using the same.

The inverter circuit of the present invention includes: a first p-type transistor for turning on a voltage of an output terminal when the digital input signal inputted through an input terminal is turned on from a high logic level to a low logic level; A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor; A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal; A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level; A second n-type transistor forming a current path between the low potential power source and the first n-type transistor; And a third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source. A gate electrode of the first p-type transistor and a gate electrode of the third p-type transistor are connected to the input terminal, and a first bias voltage is input to a gate electrode of the second p-type transistor. A gate electrode of the first n-type transistor and a gate electrode of the third n-type transistor are connected to the input terminal, and a second bias voltage is input to a gate electrode of the second n-type transistor.

The inverter circuit of the present invention includes: a first p-type transistor for turning on a voltage of an output terminal when the digital input signal inputted through an input terminal is turned on from a high logic level to a low logic level; A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor; A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal; A first switch for switching the current path between the first p-type transistor and the third p-type transistor according to the first digital control data; A fourth p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal; A second switch for switching a current path between the first p-type transistor and the fourth p-type transistor according to second digital control data; A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level; A second n-type transistor forming a current path between the low potential power source and the first n-type transistor; A third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source; A third switch for switching a current path between the first n-type transistor and the third n-type transistor according to third digital control data; A fourth n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source; And a fourth switch for switching the current path between the first n-type transistor and the fourth n-type transistor according to the fourth digital control data. A gate electrode of the first p-type transistor, a gate electrode of the third p-type transistor, and a gate electrode of the fourth p-type transistor are connected to the input terminal, a first bias is applied to the gate electrode of the second p- Voltage is input. Type transistor, the gate electrode of the first n-type transistor, the gate electrode of the third n-type transistor, and the gate electrode of the fourth n-type transistor are connected to the input terminal, and the gate electrode of the second n- Voltage is input.

A liquid crystal display device of the present invention includes: a timing controller for outputting data and an external clock signal as differential signal pairs; One or more source drive ICs for generating internal clock signals having a frequency higher than the external clock signal and sampling the data according to the internal clock signals; A pair of data lines for serially connecting the timing controller and the source drive ICs and serially transmitting the data to the source drive ICs; And a clock signal wiring pair for connecting the timing controller and the source drive ICs in a cascade form and transmitting the clock signal to the source drive ICs. At least one of the timing controller and the source drive ICs includes the inverter circuit.

In the present invention, two or more p-type transistors are connected in parallel between a high potential power source and an output terminal, and two or more n-type transistors are connected in parallel between the low potential power source and the output terminal. As a result, the present invention can increase the slew rate without increasing the power consumption of the inverter circuit, and can be applied to the timing controller or the source drive ICs of the liquid crystal display, thereby minimizing data transmission / reception errors.

1 is a circuit diagram showing a current interruption inverter circuit of the prior art.
FIGS. 2 and 3 are circuit diagrams showing the operation of the inverter circuit shown in FIG.
4 is a circuit diagram showing an inverter circuit according to the first embodiment of the present invention.
5 and 6 are circuit diagrams showing the operation of the inverter circuit shown in FIG.
FIG. 7 is a graph showing the results of a comparative experiment of the conventional inverter circuit shown in FIG. 1 and the inverter circuit of the present invention shown in FIG. 4 under the same experimental conditions.
8 is a circuit diagram showing an inverter circuit according to a second embodiment of the present invention.
FIG. 9 is a graph showing the results of a comparative experiment of the conventional inverter circuit shown in FIG. 1 and the inverter circuit of the present invention shown in FIG. 8 under the same experimental conditions.
10 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
11 is a timing chart showing an external clock signal and data generated in the differential signal pair from the timing controller.
12 is a timing chart showing a circuit configuration of the source drive IC shown in FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

4 to 6, an inverter circuit according to the first embodiment of the present invention includes p-type transistors MP1, MP2, MPR and n-type transistors MN1, MN2, MNR. Each of the transistors is implemented as a metal oxide semiconductor field effect transistor (MOSFET).

The gate electrode of the first p-type transistor MP1, the gate electrode of the third p-type transistor MPR, the gate electrode of the first n-type transistor MN1, and the gate electrode of the third n-type transistor MNR are connected to the input Terminal. A digital input signal Vin is input to the input terminal. The source electrode of the first p-type transistor MP1 is connected to the drain electrode of the second p-type transistor MP2, and the drain electrode of the first p-type transistor MP1 is connected to the output terminal. The output signal Vout generated by the inverted signal of the input signal is outputted to the output terminal as shown in Figs. A load capacitor (C _L ) is connected to the output terminal. A first bias voltage Vbiasp is input to the gate electrode of the second p-type transistor MP2. The first bias voltage Vbiasp is a gate bias voltage that allows the constant current i to flow. The second p-type transistor MP2 operates in a saturation state according to the first bias voltage Vbiasp to cause the constant current i to flow toward the output terminal. The source electrode of the second p-type transistor MP2 is supplied with the high-potential power supply voltage Vcc. The high-potential power supply voltage (Vcc) was applied at 1.8 V in the experiments of FIGS. 7 and 9.

And the high potential power supply voltage Vcc is supplied to the source electrode of the third p-type transistor MPR. The drain electrode of the third p-type transistor MPR is connected to the source electrode of the first p-type transistor MP1 and the drain electrode of the second p-type transistor MP2. The third p-type transistor MPR is turned on when the digital input signal Vin changes from a high logic level to a low logic level to increase the amount of current flowing to the output terminal.

The source electrode of the first n-type transistor MN1 is connected to the drain electrode of the second n-type transistor MN2, and the drain electrode of the first n-type transistor MN1 is connected to the output terminal. A second bias voltage Vbiasn is input to the gate electrode of the second n-type transistor MN2. The second bias voltage Vbiasn is a gate bias voltage that allows the constant current i to flow. The second n-type transistor MN2 operates in a saturated state according to the first bias voltage Vbiasn to flow the constant current i toward the base voltage source. A base voltage (GND or low-potential power supply voltage) is supplied to the source electrode of the second n-type transistor MN2. The ground voltage (GND) or the low potential power supply voltage can be set to 0V.

A ground voltage GND is supplied to the source electrode of the third n-type transistor MNR. The drain electrode of the third n-type transistor MNR is connected to the source electrode of the first n-type transistor MN1 and the drain electrode of the second n-type transistor MN2. The third n-type transistor MNR is turned on when the digital input signal Vin changes from a low logic level to a high logic level to increase the amount of current discharged from the output terminal.

When the digital input signal Vin is transitioned from the low logic level to the high logic level, the first n-type transistor MN1 is turned on and turned on through the first and second n-type transistors MN1 and MN2 as shown in FIG. A current i flows from the load capacitor C _L to the base voltage source and at the same time the third n-type transistor MNR is turned on and the load capacitor C connected to the output terminal through the third n-type transistor MNR _L) a current (i _add) flows into the ground voltage source from. The third n-type transistor MNR is turned on when the digital input signal Vin is transitioned from the low logic level to the high logic level to increase the discharge current flowing toward the base voltage source so that the discharge current amount of the load capacitor C _L . As a result, the present invention can reduce the time for the voltage of the load capacitor C _L to change from the high logic level to the low logic level, thereby increasing the slew rate of the inverter circuit. When the digital input signal Vin transitions from a low logic level to a high logic level, the second n-type transistor MN2 is kept on by the second bias voltage Vbiasn, and the first, And the third p-type transistors (MP1, MP2, MPR) maintain the off state.

When the digital input signal Vin is transitioned from a high logic level to a low logic level, the first p-type transistor MP1 is turned on as shown in Fig. 6 and is turned on through the first and second p-type transistors MP1 and MP2 the high-potential power voltage source current (i) into the load capacitor (C _L) connected to the output terminal from the flow at the same time, the 3 p-type transistor (MPR) is turned on so that the high potential via a second 3 p-type transistor (MNR) A current i _add flows from the power supply voltage source toward the load capacitor C _L. Claim 3 p-type transistor (MNR) is a digital input signal (Vin) is turned on when the transition from high to low transition-load capacitor (C _L) by turns on increasing the charging current flowing to the load capacitor (C _L) Thereby increasing the amount of the charging current. As a result, the present invention can reduce the time for the voltage of the load capacitor C _L to change from the low logic level to the high logic level, thereby increasing the slew rate of the inverter circuit. When the digital input signal Vin transitions from a high logic level to a low logic level, the second p-type transistor MP2 is kept on by the first bias voltage Vbiasp and the first, And the third n-type transistors MN1, MN2, MNR remain off.

The third n-type transistor MNR may include two or more n-type transistors connected in parallel with each other as shown in FIG. The third p-type transistor MPR may include two or more p-type transistors connected in parallel with each other as shown in FIG.

When the digital input signal Vin is transited, the third n-type transistor MNR and the third p-type transistor MPR operate in a saturation state, and the current i _{add thereof} is expressed by Equation (3).

L is the channel length of the transistor, V _gs is the gate-source voltage of the transistor, and V _th is the threshold voltage of the transistor, respectively, where μ is the mobility of the transistor, C _ox is the parasitic capacitance of the transistor, W is the channel width of the transistor, it means.

A conventional inverter circuit must supply a large constant current to the inverter circuit in order to increase the slew rate. On the other hand, the inverter circuit of the present invention has a gate-source voltage V _{gs of} the third n-type transistor MNR and the third p-type transistor MPR when the digital input signal Vin is transitioned, And the dynamic current (i _add ) flows in a square, so that the slew rate can be increased while driving with low power. This was demonstrated in the experimental results of FIG. The results of the experiment of FIG. 7 were obtained in a comparative experiment under the same drive operating conditions as the inverter circuit of the prior art as shown in FIG. 1 and the inverter circuit of the present invention as shown in FIG.

8 is a circuit diagram showing an inverter circuit according to a second embodiment of the present invention. FIG. 9 is a graph showing the results of a comparative experiment of the conventional inverter circuit shown in FIG. 1 and the inverter circuit of the present invention shown in FIG. 8 under the same experimental conditions.

8, the inverter circuit according to the second embodiment of the present invention includes p-type transistors MP1, MP2, MPR1 to MPR4, n-type transistors MN1, MN2, MNR1 to MNR4, And switches S1 to S8 controlled by data. Each of the transistors is implemented as a metal oxide semiconductor field effect transistor (MOSFET).

The first and second p-type transistors MP1 and MP2 and the first and second n-type transistors MN1 and MN2 are substantially the same as those of the first embodiment described above.

The gate electrode of the first p-type transistor MP1, the gate electrodes of the third to sixth p-type transistors MPR1 to MPR4, the first n-type transistor MN1, and the third to sixth n-type transistors MNR1 To MNR4 are commonly connected to the input terminal. A digital input signal Vin is input to the input terminal. A load capacitor C _L is connected to an output terminal from which the output signal Vout is output.

A high potential power supply voltage Vcc is supplied to the source electrode of the third p-type transistor MPR1. The drain electrode of the third p-type transistor MPR1 is connected to the node between the source electrode of the first p-type transistor MP1 and the drain electrode of the second p-type transistor MP2 through the first switch S1. The third p-type transistor MPR1 turns on when the digital input signal Vin changes from the high logic level to the low logic level to increase the amount of current flowing to the output terminal. The first switch S1 is turned on / off in response to the first bit b1 of the digital control data so that the current between the drain electrode of the third p-type transistor MPR1 and the source electrode of the first p- Switch the path.

The source electrode of the fourth p-type transistor MPR2 is supplied with the high potential power supply voltage Vcc. The drain electrode of the fourth p-type transistor MPR2 is connected to the node between the source electrode of the first p-type transistor MP1 and the drain electrode of the second p-type transistor MP2 through the second switch S2. The fourth p-type transistor MPR2 turns on when the digital input signal Vin changes from the high logic level to the low logic level to increase the amount of current flowing to the output terminal. The second switch S2 is turned on / off in response to the second bit b2 of the digital control data so that the current between the drain electrode of the fourth p-type transistor MPR2 and the source electrode of the first p- Switch the path.

A high potential power supply voltage Vcc is supplied to the source electrode of the fifth p-type transistor MPR3. The drain electrode of the fifth p-type transistor MPR3 is connected to the node between the source electrode of the first p-type transistor MP1 and the drain electrode of the second p-type transistor MP2 through the third switch S3. The fifth p-type transistor MPR3 turns on when the digital input signal Vin changes from a high logic level to a low logic level to increase the amount of current flowing to the output terminal. The third switch S3 is turned on / off in response to the third bit b3 of the digital control data so that the current between the drain electrode of the fifth p-type transistor MPR3 and the source electrode of the first p- Switch the path.

A high potential power supply voltage Vcc is supplied to the source electrode of the sixth p-type transistor MPR4. The drain electrode of the sixth p-type transistor MPR4 is connected to the node between the source electrode of the first p-type transistor MP1 and the drain electrode of the second p-type transistor MP2 through the fourth switch S4. The sixth p-type transistor MPR4 turns on when the digital input signal Vin changes from the high logic level to the low logic level to increase the amount of current flowing to the output terminal. The fourth switch S4 is turned on / off in response to the fourth bit b4 of the digital control data so that the current between the drain electrode of the sixth p-type transistor MPR4 and the source electrode of the first p- Switch the path.

A ground voltage (GND) is supplied to the source electrode of the third n-type transistor MNR1. The drain electrode of the third n-type transistor MNR1 is connected to the node between the source electrode of the first n-type transistor MN1 and the drain electrode of the second n-type transistor MN2 through the fifth switch S5. The third n-type transistor MNR1 is turned on when the digital input signal Vin changes from a low logic level to a high logic level to increase the amount of current flowing from the output terminal to the base voltage source. The fifth switch S5 is turned on / off in response to the fifth bit b5 of the digital control data so that the current between the drain electrode of the third n-type transistor MNR1 and the source electrode of the first n-type transistor MN1 Switch the path.

A ground voltage (GND) is supplied to the source electrode of the fourth n-type transistor MNR2. The drain electrode of the fourth n-type transistor MNR2 is connected to the node between the source electrode of the first n-type transistor MN1 and the drain electrode of the second n-type transistor MN2 through the sixth switch S6. The fourth n-type transistor MNR2 is turned on when the digital input signal Vin changes from a low logic level to a high logic level to increase the amount of current flowing from the output terminal to the base voltage source. The sixth switch S6 is turned on / off in response to the sixth bit b6 of the digital control data so that the current between the drain electrode of the fourth n-type transistor MNR2 and the source electrode of the first n-type transistor MP1 Switch the path.

A ground voltage (GND) is supplied to the source electrode of the fifth n-type transistor MNR3. The drain electrode of the fifth n-type transistor MNR3 is connected to the node between the source electrode of the first n-type transistor MN1 and the drain electrode of the second n-type transistor MN2 through the seventh switch S7. The fifth n-type transistor MNR3 turns on when the digital input signal Vin changes from the low logic level to the high logic level, thereby increasing the amount of current flowing from the output terminal to the base voltage source. The seventh switch S7 is turned on / off in response to the seventh bit b7 of the digital control data so that the current between the drain electrode of the fifth n-type transistor MNR3 and the source electrode of the first n-type transistor MN1 Switch the path.

A ground voltage GND is supplied to the source electrode of the sixth n-type transistor MNR4. The drain electrode of the sixth n-type transistor MNR4 is connected to the node between the source electrode of the first n-type transistor MN1 and the drain electrode of the second n-type transistor MN2 through the eighth switch S8. The sixth n-type transistor MNR4 is turned on when the digital input signal Vin changes from a low logic level to a high logic level to increase the amount of current flowing from the output terminal to the base voltage source. The eighth switch S8 is turned on / off in response to the eighth bit b8 of the digital control data so that the current between the drain electrode of the sixth n-type transistor MNR4 and the source electrode of the first n-type transistor MN1 Switch the path.

The third to sixth p-type transistors MPR1 to MPR4 and the third to sixth n-type transistors MNR1 to MNR4 are individually turned on in response to the digital control data. Therefore, according to the present invention, the slew rate of the inverter circuit can be increased by using the digital control data, and the slew rate can be adjusted according to the input data and the load as shown in FIG.

The inverter circuit of the present invention can be effectively applied to reduce the bit error rate of a digital signal in a liquid crystal display device in which a panel resolution and a data transmission speed are increased in order to realize a high picture quality.

The present applicant has proposed a new interface that can reduce the data size and PCB size of a liquid crystal display device than a mini LVDS (low voltage differential signaling) interface that has been widely used as an interface between the timing controller and the source drive ICs. The proposed interface method is disclosed in Korean Patent Application No. 10-2008-0127458 (December 15, 2008), Korean Patent Application No. 10-2008-0127456 (December 15, 2008), Korean Patent Application No. 10- Korean Patent Application No. 10-2008-0132479 (2008.12.23), Korean Patent Application No. 10-2008-0132493 (December 23, 2008), Korean Patent Application No. 10-2009-2009- U.S. Patent Application No. 12 / 543,991 (2009.08.19), U.S. Patent Application No. 12 / 461,652 (Aug. 2009), U.S. Patent Application No. 12 / 537,341 (Aug. 2009) U.S. Patent Application No. 12 / 554,763 (September 4, 2009). 10 to 12 show an example of a liquid crystal display device to which the proposed interface is applied.

10 to 12, the liquid crystal display of the present invention includes a liquid crystal display panel (LCP), a timing controller (TCON), one or more source drive ICs (SIC # 1 to SIC # 8) (GIC).

A liquid crystal layer is formed between the glass substrates of the liquid crystal display panel (LCP). The liquid crystal display panel LCP includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines DL and the gate lines GL.

A pixel array including data lines DL, gate lines GL, thin film transistors (TFT), and a storage capacitor Cst is formed on a lower glass substrate of the liquid crystal display panel LCP. The liquid crystal cells Clc are driven by the electric field between the pixel electrode to which the data voltage is supplied through the TFT and the common electrode to which the common voltage Vcom is supplied. The gate electrode of the TFT is connected to the gate line GL, and the drain electrode thereof is connected to the data line DL. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the positive / negative analog video data voltage from the data line DL to the pixel electrode of the liquid crystal cell Clc. On the upper glass substrate of the liquid crystal display panel (LCP), a black matrix, a color filter, a common electrode, and the like are formed.

The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the driving method.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel (LCP), a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. A spacer for maintaining a cell gap of the liquid crystal cell Clc may be formed between the upper glass substrate and the lower glass substrate of the liquid crystal display panel LCP.

The liquid crystal display of the present invention can be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller (TCON) receives vertical / horizontal synchronization signals (Vsync, Hsync) from an external SoC (System On Chip) including a video source through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling , An external data enable signal (Data Enable, DE), and a dot clock (CLK). The timing controller TCON is connected in series to each of the source drive ICs (SIC # 1 to SIC # 8) in a point-to-point fashion.

The timing controller TCON generates data such as RGB digital video data and control data as a differential signal pair. The control data includes source control data for controlling the output timing of the data voltage output from the source drive ICs (SIC # 1 to SIC # 8), the polarity of the data voltage, and the like. The control data may include gate control data for controlling the operation timing of the gate drive IC (GIC). Alternatively, the timing controller TCON generates separate gate control signals for controlling the operation timing of the gate drive ICs (GIC) using the timing signals input from the external Soc, and supplies the gate control signals to the data To the gate drive ICs (GIC) through a separate gate control wiring (not shown) separate from the wiring pair.

The timing controller TCON simultaneously transmits data such as RGB digital video data and control data in series to the source drive ICs SIC # 1 to SIC # 8 through a pair of data lines represented by solid lines. The timing controller TCON generates the external clock signal EXTCLK as a difference signal pair and outputs the external clock signal EXTCLK to one or more of the source drive ICs SIC # 1 to SIC # 8). The external clock signal includes normal clocks generated in a period in which data exists within a frame period and special codes having a longer cycle than a normal clock. The normal clocks and special codes of the external clock signal EXTCLK are transmitted at a transmission frequency lower than the transmission frequency of the RGB digital video data. The special code is generated in the blank period immediately before the start of one frame period. The special code has a different period from the normal clock and then notifies the source drive ICs (SIC # 1 to SIC # 8) that the data is transferred to the source drive ICs (SIC # 1 to SIC # 8) do.

The normal clock frequency of the external clock signal EXTCLK is 1 / N (N is the number of bits of the RGB digital video data) when one sub-pixel data per clock is transmitted as shown in FIG. 11, 1 / (N * 3, 3 is the number of subpixels contained in one pixel) when 1 pixel data per clock is transmitted. For example, 10 bits of subpixel data per clock When transmitted, the normal clock frequency of the external clock signal (EXTCLK) is one tenth of the data transmission frequency. Further, when 30 bits of R, G, and B subpixel data are transmitted per clock, the normal clock frequency of the external clock signal EXTCLK becomes lower by 1/30 of the data transmission frequency.

The source drive ICs (SIC # 1 to SIC # 8) are connected in a point-to-point fashion to the timing controller (TCON) via two pairs of data wires. Each of the source drive ICs SIC # 1 to SIC # 8 may be connected to the data lines of the liquid crystal display panel LCP by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The source driver ICs (SIC # 1 to SIC # 8) and the timing controller (TCON) are connected in a cascade form through a pair of clock signal wires. The source driver ICs (SIC # 1 to SIC # 8) receive RGB digital video data and control data through a data wiring pair and receive an external clock signal pair through a clock signal wiring pair. The source drive ICs (SIC # 1 to SIC # 8) transfer an external clock signal pair input through a clock signal wiring pair to a neighboring source drive IC. The source drive ICs SIC # 1 to SIC # 8 restore the external clock signal EXTCLK from the external clock signal pair and generate a phase locked loop (PLL) or a delay locked loop And multiplies or delays the external clock signal EXTCLK using a locked loop (hereinafter referred to as "DLL") to generate the number of bits of RGB digital video data x 2 internal clock signals. The source drive ICs (SIC # 1 to SIC # 8) sample RGB digital video data and control data using the restored internal clock signals and convert the sampled RGB digital video data into a parallel data system.

The source drive ICs (SIC # 1 to SIC # 8) decode the control data input through the pair of data lines by a code mapping method to recover the source control data and the gate control data. The source drive ICs SIC # 1 to SIC # 8 convert the RGB digital video data converted into the parallel system according to the source control data into the positive / negative analog data voltages and output the data voltages to the data lines of the liquid crystal display panel LCP (DL). The source drive ICs (SIC # 1 to SIC # 8) can transmit gate control data to one or more of the gate drive ICs (GIC).

The gate drive IC (GIC) may be connected to the gate lines of the lower glass substrate of the liquid crystal display panel through the TAP process or directly formed on the lower glass substrate of the liquid crystal display panel (LCP) by a GIP (Gate In Panel) process . The gate drive IC GIC is supplied from the timing controller TCON or sequentially supplies gate pulses to the gate lines GL in accordance with gate control data supplied through the source drive ICs SIC # 1 to SIC # 8 Supply. The gate control data includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) controls the start horizontal line at which the scan starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is a clock signal that is input to a shift register in the gate drive IC (GIC) to sequentially shift the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive IC (GIC).

Each of the source drive ICs SIC # 1 to SIC # 8 includes a data sampling and serial-to-parallel converter 21, a digital to analog converter (DAC) 22, 23). The data sampling and serial-to-parallel converter 21 generates internal clock signals using a PLL or a DLL, samples and latches RGB digital video data serially inputted through a pair of data lines according to the internal clock signals, . In addition, the data sampling and serial / parallel conversion unit 21 restores the control data input through the pair of data lines by a code mapping method to generate source control data. The polarity control signal POL controls the polarity of the positive / negative analog data voltage supplied to the data lines D1 to Dk. The source output enable signal SOE controls the output timing of the source drive ICs SIC # 1 to SIC # 8. When the gate control data is encoded in the control data, the data sampling and serial / parallel conversion unit 21 restores the gate control data from the control data input through the pair of data lines and transmits it to the gate drive IC (GIC). The gate control data includes a gate start pulse, a gate output enable signal, and the like.

The DAC 22 converts the RGB digital video data from the data sampling and serial-to-parallel conversion unit 21 into a positive gamma compensation voltage GH and a negative gamma compensation voltage GL to produce a positive / Generates a voltage. The DAC 22 then inverts the polarity of the positive / negative analog video data voltage in response to the polarity control signal POL.

The output circuit 23 supplies the charge share voltage or the common voltage Vcom to the data lines D1 to Dk through the output buffer during the high logic period of the source output enable signal SOE. The output circuit 23 supplies the positive / negative analog video data voltages to the data lines D1 to Dk through the output buffer during the low logic period of the source output enable signal SOE. The charge sharing voltage is generated when a data line to which a positive voltage is supplied and a data line to which a negative voltage is supplied are short-circuited, and has an average voltage level of the positive voltage and the negative voltage.

The inverter circuit of the present invention includes an interface receiving circuit / transmitting circuit of a timing controller (TCON), a delay cell or a VCO incorporated in a timing controller (TCON), data / external clocks of the source drive ICs SIC # 1 to SIC # A delay cell built in the source drive ICs (SIC # 1 to SIC # 8) or a VCO, and an output buffer of the source drive ICs (SIC # 1 to SIC # 8).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

TCON: Timing controller SIC: Source drive IC
GIC: gate drive IC 21: data sampling and serial /
22: digital-to-analog converter (DAC) 23: output circuit
MP1, MP2, MPR, MPR1 to MPR4: p-type transistors
MN1, MN2, MNR, MNR1 to MNR4: n-type transistors
C _L : load capacitor

Claims (8)

A first p-type transistor for turning on the voltage of the output terminal when the digital input signal input through the input terminal is transitioned from the high logic level to the low logic level;
A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor;
A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal;
A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level;
A second n-type transistor forming a current path between the low potential power source and the first n-type transistor; And
And a third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source,
Wherein a gate electrode of the first p-type transistor and a gate electrode of the third p-type transistor are connected to the input terminal, a first bias voltage is input to a gate electrode of the second p-
Wherein a gate electrode of the first n-type transistor and a gate electrode of the third n-type transistor are connected to the input terminal, and a second bias voltage is inputted to a gate electrode of the second n-type transistor. . delete The method according to claim 1,
The source electrode of the first p-type transistor is connected to the drain electrode of the second p-type transistor, the drain electrode of the first p-type transistor is connected to the output terminal,
A load capacitor is connected to the output terminal,
The high-potential power supply voltage from the high-potential power supply voltage source is supplied to the source electrode of the second p-type transistor,
Type transistor, the high-potential power supply voltage is supplied to the source electrode of the third p-type transistor, and the drain electrode of the third p-type transistor is connected between the source electrode of the first p- Connected to the node,
Wherein a source electrode of the first n-type transistor is connected to a drain electrode of the second n-type transistor, a drain electrode of the first n-type transistor is connected to the output terminal,
A low-potential power supply voltage from the low-potential power supply voltage source is supplied to a source electrode of the second n-type transistor,
Type transistor is supplied with the low potential power supply voltage and the drain electrode of the third n-type transistor is connected to the source electrode of the first n-type transistor and the drain electrode of the second n- And the node is connected to the node. A first p-type transistor for turning on the voltage of the output terminal when the digital input signal input through the input terminal is transitioned from the high logic level to the low logic level;
A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor;
A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal;
A first switch for switching the current path between the first p-type transistor and the third p-type transistor according to the first digital control data;
A fourth p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal;
A second switch for switching a current path between the first p-type transistor and the fourth p-type transistor according to second digital control data;
A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level;
A second n-type transistor forming a current path between the low potential power source and the first n-type transistor;
A third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source;
A third switch for switching a current path between the first n-type transistor and the third n-type transistor according to third digital control data;
A fourth n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source; And
And a fourth switch for switching the current path between the first n-type transistor and the fourth n-type transistor according to the fourth digital control data,
Type transistor, the gate electrode of the first p-type transistor, the gate electrode of the third p-type transistor, and the gate electrode of the fourth p-type transistor are connected to the input terminal, A bias voltage is input,
Type transistor, the gate electrode of the first n-type transistor, the gate electrode of the third n-type transistor, and the gate electrode of the fourth n-type transistor are connected to the input terminal, and the gate electrode of the second n- And a voltage is input to the inverter circuit. A timing controller for outputting data and an external clock signal as differential signal pairs;
One or more source drive ICs for generating internal clock signals having a frequency higher than the external clock signal and sampling the data according to the internal clock signals;
A pair of data lines for serially connecting the timing controller and the source drive ICs and serially transmitting the data to the source drive ICs; And
And a clock signal wiring pair connecting the timing controller and the source drive ICs in a cascade form and transmitting the clock signal to the source drive ICs,
Wherein at least one of the timing controller and the source drive ICs includes an inverter circuit,
The inverter circuit includes:
A first p-type transistor for turning on the voltage of the output terminal when the digital input signal input through the input terminal is transitioned from the high logic level to the low logic level;
A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor;
A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal;
A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level;
A second n-type transistor forming a current path between the low potential power source and the first n-type transistor; And
And a third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source,
Wherein a gate electrode of the first p-type transistor and a gate electrode of the third p-type transistor are connected to the input terminal, a first bias voltage is input to a gate electrode of the second p-
Wherein a gate electrode of the first n-type transistor and a gate electrode of the third n-type transistor are connected to the input terminal, and a second bias voltage is input to a gate electrode of the second n-type transistor. Device. delete 6. The method of claim 5,
The source electrode of the first p-type transistor is connected to the drain electrode of the second p-type transistor, the drain electrode of the first p-type transistor is connected to the output terminal,
A load capacitor is connected to the output terminal,
A source electrode of the second p-type transistor is supplied with a high potential power supply voltage from the high potential power supply voltage source,
Type transistor, the high-potential power supply voltage is supplied to the source electrode of the third p-type transistor, and the drain electrode of the third p-type transistor is connected to the drain electrode of the first p- Connected to the node,
Wherein a source electrode of the first n-type transistor is connected to a drain electrode of the second n-type transistor, a drain electrode of the first n-type transistor is connected to the output terminal,
The source electrode of the second n-type transistor is supplied with a low potential power supply voltage from the low potential power supply voltage source,
Type transistor, the drain electrode of the third n-type transistor is connected to the source electrode of the first n-type transistor and the drain electrode of the second n-type transistor, And a second node connected to the second node. A timing controller for outputting data and an external clock signal as differential signal pairs;
One or more source drive ICs for generating internal clock signals having a frequency higher than the external clock signal and sampling the data according to the internal clock signals;
A pair of data lines for serially connecting the timing controller and the source drive ICs and serially transmitting the data to the source drive ICs; And
And a clock signal wiring pair connecting the timing controller and the source drive ICs in a cascade form and transmitting the clock signal to the source drive ICs,
Wherein at least one of the timing controller and the source drive ICs includes an inverter circuit,
The inverter circuit includes:
A first p-type transistor for turning on the voltage of the output terminal when the digital input signal input through the input terminal is transitioned from the high logic level to the low logic level;
A second p-type transistor forming a current path between the high potential power supply voltage source and the first p-type transistor;
A third p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal;
A first switch for switching the current path between the first p-type transistor and the third p-type transistor according to the first digital control data;
A fourth p-type transistor that is turned on when the digital input signal transitions from a high logic level to a low logic level to cause a current from the high potential power supply voltage source to flow to the output terminal;
A second switch for switching a current path between the first p-type transistor and the fourth p-type transistor according to second digital control data;
A first n-type transistor for turning on the voltage of the output terminal when the digital input signal transitions from a low logic level to a high logic level;
A second n-type transistor forming a current path between the low potential power source and the first n-type transistor;
A third n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source;
A third switch for switching a current path between the first n-type transistor and the third n-type transistor according to third digital control data;
A fourth n-type transistor that is turned on when the digital input signal transitions from a low logic level to a high logic level to cause a current from the output terminal to flow to the low potential power supply voltage source; And
And a fourth switch for switching the current path between the first n-type transistor and the fourth n-type transistor according to the fourth digital control data,
Type transistor, the gate electrode of the first p-type transistor, the gate electrode of the third p-type transistor, and the gate electrode of the fourth p-type transistor are connected to the input terminal, A bias voltage is input,
Type transistor, the gate electrode of the first n-type transistor, the gate electrode of the third n-type transistor, and the gate electrode of the fourth n-type transistor are connected to the input terminal, and the gate electrode of the second n- And a voltage is input to the liquid crystal display device.

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