JP2003249826A - Differential circuit and amplification circuit, and display device using these circuits - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential circuit and an amplification circuit whose variations of amplitude difference is small, full-range driving is possible, and power consumption is low. <P>SOLUTION: This device has a pair of p-type transistors 101 and 102 and a pair of n-type transistors 103 and 104. A current source 105 and a switch 111 are connected in parallel between a source, to which the transistors 101 and 102 are connected in common and a power source VDD. A current source 106 and a switch 120 are connected in parallel between a source, to which the transistors 103 and 104 are connected in common and a power source VSS. This device also has connection switching means (switches 112 to 119), which freely switch the respective transistor pairs to a differential pair, which receive a differential input voltage or a current mirror pair which serves the load of the differential pair. When one of the two pairs of transistors become the differential pair, the other pair become the current mirror pair. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential circuit, an amplifier circuit and a display device using the same.

[0002]

2. Description of the Related Art There is known a drive circuit for switching and driving two amplifiers, a charging amplifier and a discharging amplifier, for full-range driving on a high potential side and a low potential side. However, when this type of drive circuit is used for a drive circuit of a liquid crystal display device, it is not possible to avoid
Output deviation occurs in each of the two amplifiers. For this reason, there is a large variation (amplitude difference deviation) between the outputs of the positive and negative voltage amplitude differences of the same gradation, which may deteriorate the image quality. The amplitude difference deviation is one of the performance indicators of the multi-output liquid crystal drive circuit, and means the deviation between the positive and negative voltage amplitude differences of the same gradation between the respective outputs. The smaller the amplitude difference deviation between the outputs, the higher the image quality. Hereinafter, a conventional drive circuit configured to switch and drive two amplifiers, a charging amplifier and a discharging amplifier, will be described.

FIG. 15 is a diagram showing an example of the configuration of a conventional drive circuit having two amplifiers (amplifying circuits), a charging amplifier and a discharging amplifier. That is, FIG. 15 shows a drive circuit in which the voltage follower circuit 910 and the voltage follower circuit 920 are combined.

The voltage follower circuit 910 has sources commonly connected, and is connected to a low-potential side power supply (ground potential) VSS via a constant current source 915 and a switch 951. Each gate has an input terminal voltage Vin and an output terminal voltage. Vout is differentially input, and n-channel transistors 913 and 914 that form a differential pair and sources are connected to the high-side power supply VDD, gates are commonly connected, and drains of the n-channel transistors 913 and 914 are connected to each other. P-channel transistors 911 and 912 which are respectively connected to the. The drain and source of the p-channel transistor 912 are connected to each other, and the p-channel transistors 911 and 912 form a current mirror circuit and function as an active load of the differential pair. Further, the gate is connected to the connection point (the output end of the differential pair) of the drain of the p-channel transistor 911 and the drain of the n-channel transistor 913, and the source is connected to the high potential side power supply VDD via the switch 952. A transistor 916 is provided. And
A constant current 917 and a switch 953 are connected in series between the connection point between the drain of the p-channel transistor 916 and the output terminal and the lower power supply VSS.

In the voltage follower circuit 920, the sources are connected in common and connected to the high potential side power supply VDD via the constant current source 925 and the switch 961, and the input terminal voltage Vin and the output terminal voltage Vout are differentially input to the respective gates. And p-channel transistors 923 and 92 forming a differential pair.
4 and the source are connected to the low-side power source VSS,
It has n-channel transistors 921 and 922 whose gates are commonly connected and whose drains are connected to the drains of the p-channel transistors 923 and 924, respectively. The drain and source of the n-channel transistor 922 are connected to each other, and the n-channel transistors 921 and 9 are connected.
22 constitutes a current mirror circuit and functions as an active load of the differential pair. Further, the n-channel transistor 92
1 is connected to the drain of the p-channel transistor 923 at its gate, and its source is the switch 96.
2 is provided with an n-channel transistor 926 connected to the lower power supply VSS, and a connection point between the drain of the n-channel transistor 926 and the output terminal and the higher power supply V
A constant current 927 and a switch 963 are connected in series between DD.

In the circuits 910 and 920, the input terminal voltage Vin is the non-inverting input terminal (transistor 9) of the differential circuit.
Input to the output terminal voltage Vo.
ut is the inverting input terminal of the differential circuit (transistor 914,
It is input to the gate 924) and constitutes a voltage follower.

The switches 951, 952 and 953 and the switches 961, 962 and 963 in the voltage follower circuits 910 and 920 are switches for controlling the operation of the voltage follower circuits 910 and 920, respectively.

In the voltage follower circuit 910,
The discharging action of the output terminal Vout has a certain discharging capability by the current source 917, but the charging action of the output terminal Vout can be performed at high speed by the p-channel transistor 916.

On the other hand, in the voltage follower circuit 920, the charging operation of the output terminal Vout has a constant charging capability due to the current source 927.
The discharge action of can be performed at high speed by the n-channel transistor 926.

Therefore, when the load connected to the output terminal of the drive circuit is driven to the high potential level with respect to the reference level, the switches 951, 952 and 953 are turned on to activate the voltage follower circuit 910 ( When driven to a low potential level, the switches 961, 962 and 963 are turned on to activate (operate) the voltage follower circuit 920, whereby high speed driving can be realized.

Further, voltage follower circuits 910, 9
20 does not operate with respect to the input voltage Vin that turns off the transistors 913 and 923, respectively,
Full range driving (driving of the entire area within the power supply voltage range) cannot be performed independently. Therefore, full range driving is possible by switching and driving each of the two voltage follower circuits 910 and 920.

However, the two voltage follower circuits 910 and 920 each generate an output offset due to variations in element characteristics due to the manufacturing process.

The main cause of the output offset is often caused by the deviation of the characteristics of the differential pair of the differential circuit forming the voltage follower circuit and the pair transistors of the current mirror circuit.

Since the characteristic deviation of the transistor occurs arbitrarily, the two voltage follower circuits 910,
The output offset of 920 occurs individually. Therefore, the drive circuit of FIG. 15 has two voltage follower circuits 91.
There is a problem that the offset changes significantly when 0 and 920 are switched and driven.

In particular, for an amplifier for amplifying the gradation voltage of the liquid crystal display device, it is important to maintain the voltage interval of the gradation level provided according to the characteristics of the liquid crystal in order to perform the gradation display. Therefore, such an amplification amplifier (driving circuit)
, The output offset does not change much depending on the gradation,
That is, it is required that the deviation between the gradations of the output offset is sufficiently small.

However, when the drive circuit shown in FIG. 15 is used as an amplifier for amplifying the gradation voltage of the liquid crystal display device, the output offset changes greatly when the two voltage follower circuits 910 and 920 are switched and driven. However, there is a problem that the voltage interval of the gradation level may not be sufficiently maintained.

The above problem will be described in more detail with reference to FIG. FIG. 16 shows a high level VL1 on the high potential side and a low level VL on the low potential side with respect to the reference level.
FIG. 16 is a diagram showing an expected value and an output value including an offset when 2 is driven by the drive circuit of FIG. 15. High level V
L1 is driven by the voltage follower circuit 910, and the low level VL2 is driven by the voltage follower circuit 920, and the offsets are ± ΔVL1, ±.
Let ΔVL2. Then, whether or not the voltage intervals of the gradation levels are maintained can be determined by whether or not the amplitude difference deviation between the two gradation levels is sufficiently small.

From FIG. 16, two voltage levels VL1 and V
As for the amplitude difference deviation of L2, the maximum amplitude difference is {(VL1 + ΔVL1)-(VL2-ΔVL2)} (1), and the minimum amplitude difference is {(VL1-ΔVL1)-(VL2 + ΔVL2)} (2). is there.

Therefore, the maximum value of the amplitude difference deviation is given by the following equation (3) from the difference between them (difference between equations (1) and (2)). {2 x (ΔVL1 + ΔVL2)} (3)

That is, in the drive circuit of FIG.
It is shown that the amplitude difference deviation when the two voltage follower circuits 910 and 920 are switched and driven may take a deviation twice the sum of the absolute values of the offsets of the respective voltage follower circuits.

[0021]

SUMMARY OF THE INVENTION Therefore, the problem to be solved by the present invention is to provide a differential circuit and an amplifier circuit capable of full-range driving while reducing the amplitude difference deviation and reducing power consumption. To provide.

Another object of the present invention is to provide a display device which improves image quality by using the above circuit in a data line driving circuit of the display device.

[0023]

In a differential circuit according to the present invention, which solves at least one of the above problems and other problems, the first transistor pair and the first transistor pair have different conductivity types. A second transistor pair, the output pair of the first transistor pair being respectively connected to the output pair of the second transistor pair, the common tail of the first transistor pair and the first pair of transistors. A current source and a switch are connected in parallel with the power supply, and a current source and a switch are connected in parallel between the common tail of the second transistor pair and the second power supply. , A pair of transistors, a differential pair receiving a differential input voltage from the input pair, and a current mirror circuit in which the input pair is connected to each other and one transistor is diode-connected to serve as a load of the differential pair. Comprising a connection switching means for freely changing the first and one of the transistor pair of the second transistor pair when the differential pair, the other transistor pair is the current mirror circuit.

A differential circuit according to another aspect of the present invention includes a first transistor pair of the first conductivity type and a second transistor pair of the second conductivity type. The drains are respectively connected to the drains of the second transistor pair, and the first current source and the first switch are provided between the commonly connected sources of the first transistor pair and the first power supply. Are connected in parallel, and a second current source and a second switch are connected in parallel between the commonly connected sources of the second transistor pair and the second power supply. , The first transistor pair is a differential pair having sources commonly connected to the first power source via the first current source and having a gate receiving a differential input voltage, and the second pair. The pair of transistors, the gates are connected to each other, And a second transistor pair, which is a current mirror circuit in which a source is connected to the second power source through the second switch, and the gate and drain of one transistor are connected to each other. Is a differential pair whose sources are commonly connected and which is connected to the second power source via the second current source, and whose gate receives a differential input voltage. And a source connected to the first power supply via the second switch, and a gate and drain of one of the transistors are connected to form a current mirror circuit. And a connection switching unit that controls switching from the first connection configuration to the second connection configuration and from the second connection configuration to the first connection configuration.

In the present invention, the first transistor pair is a p-channel transistor pair, the second transistor pair is an n-channel transistor pair, the first power supply is a high-side power supply, and the second power supply is a high-side power supply. Is a low-side power source, and when driving a high-side voltage, n
The channel transistor pair is a differential pair, the p-channel transistor pair is a current mirror circuit, and the p-channel transistor pair is a differential pair and the n-channel transistor pair is a current mirror circuit when driving a low voltage. In addition, the switching of the connection switching means is controlled.

At least one of the above problems and other problems
An amplification circuit according to another aspect of the present invention that solves the above problem is a differential circuit according to the present invention, a charging amplification stage that receives an output signal of the differential circuit and charges an output terminal, and the differential circuit. And a discharge amplification stage that discharges the output terminal by receiving the output signal from the output terminal of the differential circuit. The output terminal is fed back to the inverting input terminal of the differential input terminal of the differential circuit.

An amplifier circuit according to another aspect of the present invention includes the differential circuit according to the present invention, wherein the differential circuit differentially inputs an input terminal voltage and an output terminal voltage, A charging circuit that charges the output terminal based on an output signal, a first bias control unit that receives the input terminal voltage and controls an output bias voltage, the output terminal, and a second low-side power supply. A follower transistor which is connected to a power source and which receives a bias voltage output from the first bias control means as an input, and which follows the voltage difference between the input terminal voltage and the output terminal voltage. A follower discharge circuit that discharges the output terminal by a follower operation, a discharge circuit that discharges the output terminal based on an output signal of the differential circuit, and an output that receives the input terminal voltage. A second bias control means for controlling the bias voltage, and a follower transistor connected between the first power supply forming the high-potential side power supply and the output terminal and receiving the bias voltage of the second bias control means as an input. And a follower type charging circuit for charging the output terminal by a follower operation of an active element according to a voltage difference between the input terminal voltage and the output terminal voltage.

A display device according to another aspect of the present invention which solves at least one of the above problems and other problems is a differential circuit according to the present invention which receives an input terminal voltage and an output terminal voltage as inputs. An amplifier circuit having an amplifier stage for controlling charging and discharging of the output terminal is provided as a data line driving circuit.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described. A differential circuit according to the present invention includes a first transistor pair (101, 102) and a second transistor pair (103, 10) having a conductivity type different from that of the first transistor pair.
4) and including the first transistor pair (101, 10).
The output pair of 2) is the output pair of the second transistor pair (10
3, 104), and a current source (105) and a switch (1) between the common tail of the first transistor pair (101, 102) and the first power supply (VDD).
11) is connected in parallel, and the common tail of the second transistor pair (103, 104) and the second power supply (VS
S) between the current source (106) and the switch (120)
Are connected in parallel, and each transistor pair serves as a load for the differential pair, in which a differential pair receiving a differential input voltage from the input pair and an input pair are connected and one transistor is diode-connected. A current mirror circuit and means (112 to 119) for making it switchable are provided,
When one of the first and second transistor pairs is a differential pair, the other transistor pair is a current mirror circuit.

In addition to the CMOS process, the above circuit structure can be applied to a bipolar transistor. When applied as an amplifier circuit of a drive circuit of a liquid crystal display device, the MOS transistor may be composed of a polycrystalline silicon thin film transistor (poly-SiTFT). The poly-Si TFT has a high field effect mobility and allows peripheral circuits to be integrated on a substrate. In the differential circuit configured as described above, the output pair of transistors corresponds to the pair of drains in the case of MOS transistors and corresponds to the pair of collectors in the case of bipolar transistors. The input pair of the transistor pair is a gate pair in the case of a MOS transistor and a base pair in the case of a bipolar transistor. Furthermore, the common tail of the transistor pair is M
In the case of an OS transistor, it is the commonly connected source of a transistor pair, and in the case of a bipolar transistor, it is the commonly connected emitter of a transistor pair.

In a preferred embodiment thereof, the present invention includes an n-channel transistor pair and a p-channel transistor pair, each pair being switchable between a differential pair and a current mirror pair by connection switching means. Therefore, when one of the pair is a differential pair, the other is a current mirror pair. In the n-channel type and p-channel type conductive type (polarity) transistor pairs, the sources are commonly connected between the transistor pairs having the same polarity, and the current source and the switch are connected between the common connection node (node) and the power supply. Are connected in parallel. In the amplifier circuit using the above differential circuit, the connection switching means is switched so as to be an n-channel differential pair input when driving a high potential side voltage and a p-channel differential pair input when driving a low potential side voltage. Control.

According to the differential circuit of the present invention, even when the differential circuit of the n-channel differential pair and the differential circuit of the p-channel differential pair are switched, due to variations in element characteristics in the stable state, It is possible to make VinP and VinM deviate in the same direction (plus side, minus side). Therefore, in the amplifier circuit using the differential circuit of the present invention, the directions of the output offsets due to variations in element characteristics are the same, and the amplitude difference deviation can be suppressed. In addition, full range output is possible and power consumption is low. The amplitude difference deviation is one of the performance indexes of the multi-output liquid crystal drive circuit, and means the deviation between the positive and negative voltage amplitude differences of the same gradation between the respective outputs. The smaller the amplitude difference deviation between the outputs, the higher the image quality.

In the differential circuit according to the present invention, preferably, the p-type first and second transistors (101, 102) whose sources are commonly connected and the drains of the p-channel type transistor pairs are respectively provided. And n-channel type third and fourth transistors (103, 104) connected in common and having sources commonly connected, and the commonly connected sources of the first and second transistors (101, 102) and the first The first switch (111) and the first current source (105) are connected in parallel between the power source (VDD) and the third and fourth switches.
A second switch (120) and a second switch (120) between the commonly connected sources of the transistors and the second power supply (VSS).
Current source (106) is connected in parallel. First,
The third and fourth switches (112, 113) connected in series are provided between the gates of the second transistors (101, 102), and the third and fourth transistors (103, 104) are provided. ) Between each gate
Fifth and sixth switches (118, 118) connected in series.
119). First transistor (101)
The connection node of the gate of the third switch (112) and the first
7th switch (114) between the input terminal (1) of
Is equipped with. An eighth switch (115) is provided between the connection node between the gate of the second transistor (102) and the fourth switch (113) and the second input terminal (2). The gate of the third transistor (103) and the fifth
A ninth switch (116) is provided between the connection node of the switch (118) and the first input terminal (1). A tenth switch (117) is provided between the connection node of the fourth transistor (104) and the sixth switch (119) and the second input terminal (2). Then, the connection nodes of the third and fourth switches (112, 113) and the connection nodes of the fifth and sixth switches (118, 119) are connected, and these common connection nodes are the second and fourth
Is connected to the connection node of the drains of the transistors (102, 104). The connection node between the drain of the first transistor and the drain of the third transistor (103) is connected to the output terminal.

In the differential circuit according to the present invention, the first, third, fourth, ninth and tenth switches (111, 11).
2, 113, 116, 117) are turned on, and the second, fifth, sixth, seventh, and eighth switches (120, 120,
118, 119, 114, 115) in the non-conducting state and the first, third, fourth, ninth and tenth switches (111, 112, 113, 116, 1).
17) is made non-conductive, and the second, fifth, sixth, seventh and eighth switches (120, 118, 119, 1)
(14, 115) is controlled to be switched to the second connection state in which it is in a conductive state.

In the differential circuit according to the present invention, referring to FIG. 4, first, third and fourth switches (111, 11) are provided.
2, 113) is an inverted signal (S1B) of the first control signal.
Of the first conductivity type transistor which inputs to the gate of the second, fifth and sixth switches (120, 118, 1
19) is a transistor of the first conductivity type having the second control signal (S2) as its input to the gate.
Switches (114, 115) of the second control signal (S
2) and its inverted signal (S2B) are input to the gates of the CMOS transfer gates.
The tenth switch (16, 117) is composed of a CMOS transfer gate whose gate receives the first control signal (S1) and its inverted signal (S1B).

Referring to FIG. 5, the amplifier circuit (driving circuit) according to the present invention includes a charging amplifier stage (510) for charging the output terminal (2) based on the output (3) of the differential circuit,
And a discharge amplification stage (520) for discharging the output terminal (2) based on the output (2) of the differential circuit, wherein the output terminal voltage Vout is fed back to the inverting input terminal of the differential circuit. Is entered.

In a preferred embodiment of the amplifier circuit (drive circuit) according to the present invention, referring to FIG.
The charging amplification stage (210) includes a fifth transistor (211) whose gate receives the output signal (3) of the differential circuit and whose drain is connected to the output terminal (2). A switch (213) is provided between the source and the high-side power supply (VDD), and a fifth transistor (211) is provided.
A switch (214) and a current source (212) connected in series are provided between the drain of the power source and the low-side power source (VSS). The discharge amplification stage (220) includes a sixth transistor (221) whose gate receives the output signal (3) of the differential circuit and whose drain is connected to the output terminal (2).
Source of transistor (221) and low side power supply (VS
A switch (223) is provided between S), and a switch (224) and a current source (222) connected in series are provided between the drain of the sixth transistor (221) and the high potential side power supply VDD. High-side power supply (VDD) and transistor (2
A switch (531) for resetting between the gates of 11)
Are connected. The reset switch (541) is also connected between the low potential power supply (VSS) and the gate of the transistor (221). While the reset switch (531) is turned on, the transistor (211)
Of the gate voltage (output signal of the differential circuit) is reset to the high-side power supply voltage VDD, turning off the transistor (211) and deactivating the charging amplification stage (210) during that time. While the reset switch (541) is turned on, the gate voltage of the transistor (221) (the output signal of the differential circuit) is reset to the lower power supply voltage VSS and the transistor (221) is turned off during the period.
The discharge amplification stage (220) is deactivated.

In a preferred embodiment of the amplifier circuit (driving circuit) according to the present invention, referring to FIG. 10, the differential circuit differentially inputs the input terminal voltage and the output terminal voltage, and the difference between them. A charging circuit (311) for charging the output terminal based on the output of the driving circuit, and a first bias control means (transistor 411, current source 414) for controlling the output bias voltage by receiving the input terminal voltage. A follower transistor (412) connected between the output terminal and a low potential side power supply (VSS) and having a bias voltage output from the first bias control means as an input, and the input terminal voltage and the A follower discharge circuit (410) that discharges the output terminal by a follower operation of an active element according to a voltage difference from the output terminal voltage; A discharge circuit that performs discharging operation of the serial output terminal (321), a second bias control means (421 for controlling the output bias voltage receiving said input terminal voltage,
A current source 424) and a follower transistor (422) connected between the high-potential side power source and the output terminal and receiving the bias voltage of the second bias control means as an input. And a follower type charging circuit (420) for charging the output terminal by the follower operation of the active element according to the voltage difference from the output terminal voltage.

More specifically, the amplifier circuit (driving circuit) according to the present invention is shown in FIG.
Referring to 0, a seventh transistor (31 connected between the high-side power supply VDD and the output terminal (2) and having an output signal (3) of the differential circuit as its input
A charging circuit including 1), an eighth transistor (412) having a follower configuration connected between the output terminal (2) and the lower power supply (VSS), the input terminal (1) and the lower power supply (V
SS), driven by a constant current source (414),
A follower discharge circuit (4) having a ninth diode-connected transistor (411) whose gate is connected to the gate of the follower transistor (412).
10) is provided. Furthermore, a discharge circuit including a tenth transistor (321) connected between a low-side power supply (VSS) and the output terminal (2) and inputting an output signal (3) of the differential circuit to a gate, The eleventh follower configuration connected between the output terminal (2) and the high-side power supply (VDD)
Is inserted between the high-side power source and the input terminal (1) and is driven by the constant current source (424),
An eleventh transistor (4
22) a diode-connected first connected to the gate of
And a follower type charging circuit (420) having two transistors (421). Charging circuit (31
1) and at least one of the discharge circuit (321) are controlled to be inactive, and the follower type discharge circuit (41)
0), and control means for controlling activation and deactivation of the follower type charging circuit (420), respectively.

Further, a switch (532) is provided between the seventh transistor (311) and the high potential side power source (VDD), and a switch (553) is provided between the eighth transistor (412) having a follower configuration and the low potential side power source. A constant current source (41) is provided between the ninth transistor (411) and the lower power source.
4) and a switch (552) connected in series, and a switch (551) and a constant current source (413) between the ninth transistor (411) and the high potential side power supply. Furthermore, the tenth transistor (321) and the low-side power source (V
A switch (542) is provided between the SS and the eleventh transistor (422) in the follower configuration and the high-side power supply (VD).
A switch (563) is provided between D) and a switch (562) connected in series with the constant current source (424) between the twelfth transistor (421) and the high potential side power supply (VDD). Transistor (421) and low side power supply (V
Switch (561) and constant current source (423) between SS)
Is equipped with. Further, a switch (531) for resetting the output signal (3) of the differential circuit is provided between the gate of the seventh transistor (311) and the high potential side power supply (VDD). A switch (542) for resetting the output signal (3) of the differential circuit is also provided between the gate of the tenth transistor (321) and the low potential side power supply (VSS).

Referring to FIG. 14, the display circuit according to the present invention is provided with the above-mentioned amplification circuit having amplification stages for charging and discharging, for example, as an output circuit (100) for driving a data line.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the embodiment of the present invention described above in more detail, an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

Referring to FIG. 1, a differential circuit according to this embodiment includes a p-channel transistor pair 101 and 102.
The n-channel transistor pair 103, 104 is provided, the sources of the p-channel transistor pair 101, 102 are commonly connected, and the switch 111 and the constant current source 105 are connected between the common connection point (node) and the high potential side power supply VDD. Are connected in parallel, and the p-channel transistor pair 101, 1
Switches 112, 1 connected in series between the 02 gates
13 and includes a p-channel transistor pair 101, 102.
Drain and n-channel transistor pair 103, 104
And the drain of is connected to each other.

N-channel transistor pair 103, 104
Sources are commonly connected, and a switch 120 and a constant current source 106 are connected in parallel between the common connection point and the low-potential-side power source VSS, and the n-channel transistor pair 10 is connected.
Switch 11 connected in series between the gates of 3 and 104
8 and 119 are provided. In addition, switch 112 and p
A switch 114 connected in series between a connection point with the gate of the channel transistor 101 and a connection point with the switch 118 and the gate of the n-channel transistor 103.
And 116 are provided. The connection point between the switch 113 and the gate of the p-channel transistor 102, and the switch 11
Switches 115 and 117 connected in series are provided between the node 9 and the gate of the n-channel transistor 104. The connection point between the switches 113 and 112 is connected to the connection point between the switches 118 and 119, and further connected to the connection point between the drain of the p-channel transistor 102 and the drain of the n-channel transistor 104.
A differential input terminal Vi is provided at a connection point between the switch 114 and the switch 116 and a connection point between the switch 115 and the switch 117.
nP and VinM are respectively connected, and the drain of the p-channel transistor 101 and the n-channel transistor 10 are connected.
The connection point of the drains of 3 is connected to the output terminal dfout.

As described above, the differential circuit according to this embodiment includes the p-channel transistor pair 101 and 102, the n-channel transistor pair 103 and 104, and the connection switching means (switches 111 to 120), and one transistor The pair is a differential pair that differentially inputs two input voltages VinP and VinM, and the other transistor pair is a current mirror circuit that forms a load by connecting the input terminal and the output terminal to the output pair of the differential pair. With the configuration, the connection switching means switches the conductivity type of the differential pair and the current mirror circuit. Each of the p-channel type and n-channel type transistor pairs can be switched between the differential pair and the current mirror pair by the connection switching means, and when one becomes a differential pair, the other. Is a current mirror circuit.

FIG. 2 is a diagram for explaining how to control each switch of FIG. 1 which constitutes connection switching means in the differential circuit according to this embodiment. FIG. 2 shows two connection states (connection switching 1, connection switching 2) by the connection switching means.

In connection switching 1, switches 111 and 11
2, 113, 116, 117 are turned on and the switch 11
4, 115, 118, 119 and 120 are turned off.

At this time, the n-channel transistor pair 10
Sources 3 and 104 are connected to a current source 106 and are commonly driven, and are driven by two input voltages VinP and VinP.
The gates of the p-channel transistor pairs 101 and 102 are commonly connected, and the drain and the gate of the transistor 102 are connected (the diode-connected transistor 102 is the current of the current mirror). The input terminal and the output terminal of the differential pair are connected to the input terminal and the output terminal to form a load current mirror circuit, and the current flowing through the differential circuit is controlled by the current source 106.

On the other hand, in connection switching 2, the switches 111,
112, 113, 116, 117 are turned off, and switches 114, 115, 118, 119, 120 are turned on. At this time, the p-channel transistor pair 101, 102
Becomes a differential pair for differentially inputting two input voltages VinP and VinM, and an n-channel transistor pair 103, 1
Reference numeral 04 denotes a current mirror circuit that forms a load by connecting the input end and the output end to the output pair of the differential pair, and the current flowing in the differential circuit is controlled by the current source 105.

The output signal of the differential circuit is taken out from the common connection point of the drain of the transistor 101 and the drain of the transistor 103, and is common to the connection states of connection switching 1 and connection switching 2. Further, since the differential circuit becomes inactive with respect to the differential input voltage at which at least one transistor of the differential pair is turned off, the connection switching 1, 2 is controlled so that the differential circuit in the stable state does not become inactive. Preferably. Specifically, in the connection switching 1, since the n-channel transistor pair 103, 104 is a differential pair, the n-channel transistor pair 103, 10 from the low power supply VSS.
A voltage lower than the threshold voltage of 4 is set as the lower limit, and the differential input voltage (VinP, VinM) on the higher potential side is controlled to operate. In connection switching 2, since the p-channel transistor pair 101 and 102 are a differential pair, the high-potential power supply VDD to the p-channel transistor pair 103 and 1
A voltage lower by the threshold voltage of 04 is set as an upper limit, and the differential input voltage (VinP, VinM) on the lower potential side is controlled to operate. Further, when the connection switching voltage Vm is provided, Vm is set to a voltage between the upper limit and the lower limit, and the connection switching 1 state is set for the differential input voltage on the high potential side of Vm or more, and the low potential of less than Vm. Switching control is performed so that the connection switching 1 state is set for the side differential input voltage.

FIGS. 3A and 3B are equivalent circuits of FIG. 1 (the output terminals of the differential circuit are omitted) in the connection switching 1 and 2 of FIG. The operation of the differential circuit of the present invention will be described. The transistor pairs 101, 102 and 10
3 and 104 have the same polarity and the same transistor characteristics. The input voltage VinP is a predetermined voltage at which the differential pair can operate, and the input voltage VinM is a voltage whose potential can be easily changed. At this time, FIG.
In (B), an equal drain current flows through the differential pair transistor due to the current mirror circuit, and the gate voltage and source voltage of the differential pair transistor are stable in the same state.
In the stable state, VinP = VinM.

Next, in one embodiment of the present invention, the case where the characteristics of the transistor pairs of the same polarity are deviated from each other due to the manufacturing process or the like will be described. Here, a case where the characteristics of the n-channel transistor 103 deviate from the standard characteristics will be described as an example.

FIGS. 3C and 3D show transistors 101 and 10 forming a differential pair and a current mirror circuit.
The drain current characteristics (Ids-V) of the ON operation region with respect to the gate-source voltage of each of 2, 103, and 104.
It is the figure which showed gs characteristic). 3C and 3D
, The solid line indicates the standard characteristic, and the broken line indicates the n-channel transistor 10 whose threshold voltage is deviated from the standard characteristic in the increasing direction.
3 shows characteristics.

In connection switching 1, FIG. 3 (A) and FIG. 3 (C)
With reference to p-channel transistors 101, 102
Is a current mirror circuit, and has a drain voltage Id equal to that of the n-channel transistors 103 and 104 forming a differential pair.
s101, Ids102 (Ids101 = Ids10
2) is supplied.

NMOS differential transistor pair 103, 10
The gate-source voltage of 4 is determined by the drain currents Ids101 and Ids102, respectively. Figure 3
In the example shown in (C), the state in which the gate-source voltage Vgs103 of the transistor 103 is larger than the gate-source voltage Vgs104 of the transistor 104 is applied is the stable state.

At this time, the n-channel transistor 10
The difference between the gate and source voltages of 3, 104 is the input voltage Vi.
It becomes a voltage difference between nP and VinM, and the following relationship is established. VinP-VinM = Vgs103-Vgs104> 0 (4)

On the other hand, in the connection switching 2, FIG.
Referring to (D), the n-channel transistor 103,
Reference numeral 104 denotes a current mirror circuit, and p forming a differential pair.
Different drain currents Ids103 and Ids104 are supplied to the channel transistors 101 and 102, respectively.
Gates of pMOS differential transistor pair 101 and 102
The source-to-source voltage (negative value) is determined by the drain currents Ids103 and Ids104, respectively. Figure 3
In the example shown in (D), a stable state is a state in which the gate-source voltage Vgs102 of the transistor 102 is applied with an input voltage VinM having an absolute value larger than the gate-source voltage Vgs101 of the transistor 101. Become. At this time, the p-channel transistor 101,
The difference between the gate-source voltage of 102 is the input voltage Vin
The voltage difference between P and VinM is established, and the following relationship is established. VinP-VinM = Vgs101-Vgs102> 0 (5)

From the above, the voltage difference between the input voltages VinP and VinM (VinP- in the stable state of the connection switching 1 and 2).
VinM) are both positive.

This shows that the deviation direction of (VinP-VinM) in the connection switching 1 and 2 is equal to the deviation of the transistor characteristic of the n-channel transistor 103, and (VinP-Vin) due to the connection switching.
The deviation of the deviation of M) can be suppressed to be small.

In particular, the transistors 101, 102, 10
By setting the transistor sizes of the respective polarities of 3 and 104 so that the slopes (absolute value of ΔIds / ΔVgs) of the Ids-Vgs characteristic curve with respect to the same drain current are sufficiently equal, that is, the Ids-Vgs characteristic between polarities is set. It is also possible to make the magnitudes of the deviations of (VinP-VinM) of the connection switchings 1 and 2 sufficiently equal by designing to be substantially line-symmetrical.

In the above description, when the threshold voltage of the n-channel transistor 103 deviates in the increasing direction (Vtn + Δ
Vtn) has been described as an example, but the transistor 10
Even if any one of the elements 1, 102, 103 and 104 deviates from the standard characteristics, the directions of deviation of (VinP-VinM) in the connection switching 1 and 2 become equal, and even if the connection switching is performed, The deviation of the deviation of (VinP-VinM) can be suppressed to be small.

That is, in the differential circuit of the present invention, even when any one of the four transistors forming the differential pair and the current mirror circuit deviates from the standard characteristics, the (VinP-VinM) connection switching 1 and 2 is performed. The deviation directions are the same, and even if the connection is switched (VinP-Vin
The deviation of the deviation of M) can be suppressed to be small.

It should be noted that, instead of the connection switching as described above,
Two differential circuits having the same configuration as those in FIGS. 3A and 3B are prepared separately, and when switching between them, eight transistors are included in the differential pair and the current mirror circuit. (See the conventional circuit in FIG. 15). In such a configuration, the deviation direction of (VinP-VinM) of the two differential circuits with respect to the deviation of the transistor characteristic may be different, and the deviation of the deviation of (VinP-VinM) due to the switching of the two differential circuits is small. I can't hold back.

FIG. 4 is a diagram showing a configuration of the second embodiment of the present invention, and is a diagram showing an example in which each switch of the differential circuit of FIG. 1 is configured by a MOS transistor. In FIG. 4, the switch control signals S1 and S2 are low level (L).
Alternatively, it is controlled at a high level (H).

When (S1, S2) = (H, L) is controlled, the state of connection switching 1 is established, and (S1, S2) =
When it is controlled to (L, H), the state of connection switching 2 is set. Note that S1B and S2B are inverted signals of S1 and S2, respectively.

Each switch may be any switch as long as it can control connection and disconnection. FIG. 4 shows a configuration in which the number of transistors is small (the number of elements is reduced) and the area can be saved. First, the switch 111 and the switch 120, one ends of which are connected to the high-potential power supply VDD and the low-potential power supply VSS, can be configured by a single p-channel transistor and an n-channel transistor, respectively.

Also, the switches 112 and 113 are p
Each may be configured with a channel transistor. The reason is that the switches 112 and 113 are turned on in the connection switching 1 state and the p-channel transistors 101 and 102 form a current mirror circuit. P-channel transistors 101 and 10 at that time
This is because the gate potential of 2 is a constant potential that is relatively close to the higher power supply voltage VDD. For example, the potential difference between the gates of the p-channel transistors 101 and 102 and the high-potential-side power supply terminal VDD in the connection switching 1 state when the current value of the current source 106 is set small is considerably large as the threshold voltage of the p-channel transistors 101 and 102. Since the voltages are close to each other, the gate potentials of the p-channel transistors 101 and 102 can be said to be sufficiently close to the power supply voltage VDD which is sufficiently high with respect to the power supply voltage range. Therefore, the switches 112, 113
Is composed of a single p-channel transistor, and each gate is supplied with the low-potential power supply voltage VSS to be turned on, and is supplied with the high-potential power supply voltage VDD to be turned off to sufficiently function as a switch.

Similarly, the switches 118 and 119 may each be composed of a single n-channel transistor. The switches 118 and 119 are turned on in the connection switching 2 state in the n-channel transistors 103 and 10.
This is because when 4 constitutes a current mirror circuit, the gate potentials of the n-channel transistors 103 and 104 at that time are constant potentials relatively close to the lower power supply voltage VSS.

The switches 114, 115 and 1 shown in FIG.
When the input voltages VinP and VinM are given as arbitrary voltages, the reference numerals 16 and 117 are CMOS switches each having one end connected to the input terminal 1 or 2.

In FIG. 4, the source of the current source 105 is connected to the high potential side power source VDD, and the bias voltage B is applied to the gate.
IASP is input and the drain is the transistor 101.
And 102 connected to a common source, the current source 106 has a source connected to the lower power source VSS and a gate connected to a bias voltage BIASN.
Is input to the drains of the transistors 103 and 104.
Of n-channel transistors connected to a common source of. The bias levels of the bias voltages BIASP and BIASN may be changed as needed. For example, when stopping the differential circuit, (S1, S2) = (L,
As L), the transistors 111 and 120 are turned off, the bias voltage BIASP is switched to the high-side power supply VDD, the current source transistor 105 is deactivated, the bias voltage BIASN is switched to the low-side power supply voltage VSS, and the current source transistor 106 is deactivated. It is also possible to suppress the current inside the differential circuit completely to suppress the power consumption.

Next, another embodiment of the present invention will be described. FIG. 5 is a diagram showing the configuration of the third exemplary embodiment of the present invention. FIG. 5 shows the configuration of a drive circuit configured by using the differential circuit of FIG. That is, in FIG. 5, the differential circuit including the transistors 101, 102, 103 and 104, the switches 111 to 120, and the current sources 105 and 106 is the same as that shown in FIG. 6 is a diagram showing an example of how to control the drive circuit in FIG.

Referring to FIG. 5, this driving circuit is shown in FIG.
It is a feedback type amplifier circuit including two amplifier stages 510 and 520 which operate by receiving the output of the differential circuit shown in FIG. In FIG. 5, an input voltage Vin (input voltage VinP in FIG. 1) and an output voltage Vout (input voltage VinM in FIG. 1) are input to two input terminals (differential input terminals) of the differential circuit.

The amplifying stage 510 is a charging amplifying stage for quickly charging the output terminal 2, and the amplifying stage 520 is a discharging amplifying stage for quickly discharging the output terminal 2. In addition,
The configurations of the charging amplification stage 510 and the discharging amplification stage 520 will be described later with reference to FIG. The operation of the drive circuit shown in FIG. 5 will be described with reference to FIG.

In FIG. 6, in the state of connection switching 1, the switches 111, 112, 113, 116, 11 of the differential circuit are shown.
7 is turned on, and switches 114, 115, 118, 11
9, 120 are turned off, the amplification stage 510 is activated (operable), and the amplification stage 520 is deactivated (stopped).

When the output terminal voltage Vout is lower than the desired voltage, the output is generated by the operation of the differential circuit and the charging action of the amplification stage 510 according to the voltage difference between the input terminal voltage Vin and the output terminal voltage Vout. The terminal voltage Vout can be raised to a desired voltage.

On the other hand, in the state of connection switching 2, the switches 111, 112, 113, 116 and 117 of the differential circuit are turned off and the switches 114, 115, 118, 119 and 1 are turned off.
20 is turned on, the amplification stage 510 is deactivated (stopped), and the amplification stage 520 is activated (enabled).

When the output terminal voltage Vout has a higher potential than the desired voltage, the operation of the differential circuit according to the voltage difference between the input terminal voltage Vin and the output terminal voltage Vout and the discharging action of the amplification stage 520 cause the output terminal voltage to rise. The voltage Vout can be reduced to a desired voltage.

The outputs of the differential circuit are the amplification stages 210, 2
Since it is common to 20 amplifier stages 210, 2
If the optimum output voltage of the differential circuit is different at the start of each operation of 20, the output voltage of the differential circuit is set to the optimum voltage at the start of each state of connection switching 1 and connection switching 2. A reset circuit for resetting may be provided.

Further, FIG. 6 shows the case of driving in either the connection switching 1 or the connection switching 2 in one output period in which a desired voltage is driven, but in this case, the high voltage side and the low voltage side are driven. It is suitable for use in applications in which voltages are alternately driven. In the case of driving arbitrary voltages in an arbitrary order, the connection switching 1 and the connection switching 2 are performed within one output period.
May be switched and driven. In this case, the connection switching 1 is controlled at least when the high voltage is stably driven, and the connection switching 2 is controlled when the low voltage is stably driven.

In the drive circuit shown in FIG. 5, the p-channel transistor pair 101 and 102 and the n-channel transistor pair 103 and 104 of the differential circuit have the same polarity and have the same transistor characteristics, and the connection switching states 1 and 2 are the same. Then, a voltage equal to the input voltage Vin is applied to the output terminal 2 by V
If it is configured so that it can be output as out,
At this time, the input terminal voltage Vin (the input voltage VinP in FIG. 1) and the output terminal voltage V are applied to the two input terminals of the differential circuit.
out (input voltage VinM in FIG. 1) is input, and Vi
n = Vout becomes stable.

Therefore, in this case, the matters described with reference to FIG. 3 also apply to the drive circuit shown in FIG. 5 as they are, and even when the characteristics of the pair of transistors of the same polarity in the differential circuit are deviated due to the manufacturing process or the like. , The direction of deviation of (Vin-Vout) is the same in connection switching 1 and 2, and even if connection switching is performed, the deviation of deviation of (Vin-Vout) can be suppressed to a small value.

The transistor characteristic shift may occur also in the amplification stages 510 and 520. However, the influence thereof is sufficiently small. Therefore, considering the case where the transistor pair characteristic of the differential circuit shifts, the operation Is sufficient for explanation.

On the other hand, the drive circuit shown in FIG. 15 is also a voltage follower circuit capable of outputting a voltage equal to the input voltage Vin as Vout to the output terminal 2.
Since each of the voltage follower circuits 901 and 902 is configured to include a differential circuit individually, when the voltage follower circuits 901 and 902 are switched and driven,
Deviation of transistor characteristics (Vin-Vout)
The deviation direction is arbitrary, and the deviation cannot be suppressed small.

That is, the drive circuit of FIG. 5 is more sensitive to the deviation of the transistor characteristics than the drive circuit of FIG.
The deviation of the deviation of −Vout) can be suppressed to be small. In particular, for an amplifier for amplifying the gradation voltage of a liquid crystal display device, it is important to maintain the voltage interval of the gradation level provided according to the characteristics of the liquid crystal for performing the gradation display. Therefore, such an amplifier for amplification (driving circuit) is required to have an output offset that does not change much depending on the gradation, that is, a deviation between the gradations of the output offset is sufficiently small.

In that respect, the drive circuit shown in FIG. 5 can suppress the deviation of the deviation of (Vin-Vout) with respect to the deviation of the transistor characteristics to be small, and an amplifier for amplifying the gradation voltage of the liquid crystal display device or the like. Suitable for

FIG. 7 is a diagram for explaining the operation of the drive circuit of FIG. 5, in which the high level VL1 on the high potential side and the low level VL2 on the low potential side with respect to the reference level are set to the drive circuit of FIG. It is a figure showing an output value including an expected value and an offset when driven by. The deviation of the deviation of (Vin-Vout) with respect to the deviation of the transistor characteristics of the drive circuit of FIG. 5 will be described in detail with reference to FIG.

In FIG. 7, the expected value is Vout = Vin when there is no shift in the transistor characteristics, and the output value including the offset is Vout when there is a shift in the transistor characteristics.

In order to evaluate the deviation between the connection switchings 1 and 2, the high level VL1 drives the drive circuit of FIG. 5 in the connection switching 1 state, and the low level VL2 drives in the connection switching 2 state. The respective offsets are ± ΔVL1 and ± ΔVL2.

Whether the voltage interval of the gradation level is maintained is 2
It can be determined by whether the amplitude difference deviation between two gradation levels is sufficiently small.

In the drive circuit of FIG. 5, since the directions of deviation of (Vin-Vout) in connection switching 1 and 2 are the same, the amplitude difference deviation between the two voltage levels VL1 and VL2 in FIG. 7 is {(VL1 + ΔVL1). -(VL2 + ΔVL2)} (6) or {(VL1-ΔVL1)-(VL2-ΔVL2)} (7).

Therefore, the maximum value of the amplitude difference deviation is obtained by taking the absolute value of the difference between them and is given by the following equation (8). ｜ 2 × (ΔVL1−ΔVL2) ｜… (8)

That is, in the drive circuit shown in FIG. 5, the amplitude difference deviation when the connection switching 1 and the connection switching 2 are switched and driven is the difference between the absolute values of the offsets occurring in the respective states of the connection switching 1 and 2. It shows that there is a case where the deviation can be doubled.

In comparison with the maximum value {2 × (ΔVL1 + ΔVL2)} of the amplitude difference deviation of the drive circuit of FIG. 15 in the explanation of FIG. 16, the following relation is clear.

[0094]     │2 × (ΔVL1−ΔVL2) ｜ ≦ {2 × (ΔVL1 + ΔVL2)}                                                                 … (9)

Therefore, the drive circuit shown in FIG. 5 is better than the drive circuit shown in FIG.
It can be seen that the deviation of the deviation of (in-Vout) can be suppressed to be small.

Further, in order to make the offsets ΔVL1 and ΔVL2 in each state of the connection switching 1 and 2 as equal as possible, P
If the Ids-Vgs (drain current and gate-source voltage) characteristics between the polarities of the MOS transistors 101 and 102 and the NMOS transistors 103 and 104 are designed to be substantially line symmetric, the drive circuit of FIG. It is possible to make the difference deviation sufficiently small.

Further, another embodiment of the present invention will be described. FIG. 8 is a diagram showing the configuration of the fourth exemplary embodiment of the present invention. FIG. 8 shows the configuration of a drive circuit configured by using the differential circuit of FIG. That is, in FIG. 8, the differential circuit including the transistors 101, 102, 103 and 104, the switches 111 to 120, and the current sources 105 and 106 is the same as that shown in FIG.

The amplification stage 210 for charging is a p-channel transistor whose gate receives the output signal 3 of the differential circuit (voltage at the node between the drains of the transistors 101 and 103) and whose drain is connected to the output terminal 2. 211,
The switch 213 inserted between the source of the transistor 211 and the high-potential side power supply VDD, and the transistor 2
11, a switch 214 and a current source 212 connected in series between the drain of 11 and the lower power supply VSS.
And are equipped with. A capacitor C1 is feedback-connected between the output terminal 2 (drain output of the transistor 211) and the gate of the transistor 211, and the rising voltage waveform of the output terminal 2 is shaped. And the high-side power supply V
A reset circuit 530 having a switch 531 inserted between DD and the gate of the transistor 211 is provided.

The discharging amplification stage 220 receives the output signal of the differential circuit at its gate, and connects between the n-channel transistor 221 whose drain is connected to the output terminal 2, the source of the transistor 221, and the low potential side power supply VSS. A switch 224 and a current source 222, which are connected in series, are provided between the inserted switch 223, the drain of the transistor 221, and the high potential side power supply VDD.
A capacitor C2 is feedback-connected between the output terminal 2 (drain output of the transistor 221) and the gate of the transistor 221, and the falling voltage waveform of the output terminal 2 is shaped. The reset circuit 540 having the switch 541 inserted between the low-potential-side power supply VSS and the gate of the transistor 21 is provided.

In FIG. 8, the output terminal 3 of the differential circuit is connected to the amplification stages 210 and 220, the amplification stages 210 and 220 operate according to the output of the differential circuit, and the input terminal voltage Vin
Can be output from the output terminal 2 as the output voltage (output terminal voltage) Vout. The input terminal voltage Vin (the input voltage VinP in FIG. 1) and the output terminal voltage Vout (the input voltage VinM in FIG. 1) are input to the two input terminals of the differential circuit, thus forming a feedback amplifier circuit.

The output of the differential circuit (transistor 101
And the drains of 103) are connected to amplifier stages 210 and 22.
It is common to 0 and. And the amplification stage 21
Reset circuits 530 and 540 are provided for resetting the output signal 3 of the differential circuit before operating 0 and 220.

FIG. 9 shows an embodiment of each switch control in the output period of connection switching 1 and the output period of connection switching 2 in the drive circuit of the fourth embodiment shown in FIG. The operation of the drive circuit shown in FIG. 8 will be described below with reference to FIG.

In the output period of the connection switching 1, the switches 111, 112, 113, 116 and 117 of the differential circuit are turned on and the switches 114, 115, 118, 119 and 120 are turned on.
To turn off. At the beginning of the output period, the reset circuit 5
The switch 531 of 30 is turned on to output 3 of the differential circuit.
Is precharged to the high power supply voltage VDD for a sufficiently short time (referred to as "reset period"). In Figure 9, * 1)
As shown by, during the reset period, the output 3 of the differential circuit is
It is enough time to reset. During this time, amplification stage 2
10 is deactivated.

Then, the switch 531 is turned off to end the reset period, and then the switches 213 and 214 are turned on to activate (operate) the amplification stage 210. At this time, the drive circuit in FIG. 8 is equivalent to the voltage follower circuit 910 in FIG. 16 (states in which the switches 951, 952, and 953 are turned on). Therefore, in the drive circuit in the output period of the connection switching 1, the input terminal voltage Vin is Vi
When n> Vout, the output signal voltage of the differential circuit decreases, the p-channel transistor 211 is turned on, and the output terminal voltage Vout can be quickly raised to Vin with high charging capability.

Further, the input terminal voltage Vin is Vin <Vo
When it becomes ut, the output signal voltage of the differential circuit rises and p
The channel transistor 211 is turned off and the current source 21
The discharge action of 2 lowers the output terminal voltage Vout to Vin.

The reset circuit 530 of this embodiment has an effect of preventing the generation of output noise before and after the switching of the connection states of the connection switching 1 and the connection switching 2. For example, when the output voltage of the differential circuit has a low potential immediately before switching the connection, immediately after switching the connection, the amplifier stage 21 is irrespective of the input terminal voltage Vin.
Since the 0 p-channel transistor 211 is momentarily turned on, the output terminal voltage Vout may change and output noise may occur.

However, in this embodiment, by resetting the output 3 of the differential circuit by the reset circuit 530 so that the p-channel transistor 211 is turned off, such output noise can be prevented. . In FIG. 8, an example in which the switch 531 is used for resetting is shown, but it goes without saying that other configurations may be used. Switches 111, 112, 113, 116, 1 of the differential circuit
The switch 17 may be turned on in synchronization with the switches 213 and 214.

On the other hand, in the output period of the connection switching 2, the switches 111, 112, 113, 116, 117 of the differential circuit.
Off, switches 114, 115, 118, 119, 1
Turn on 20. At the beginning of the output period, the switch 541 of the reset circuit 540 is turned on to discharge the output 3 of the differential circuit to the low power supply voltage VSS for a sufficiently short reset period. As shown by * 1) in Figure 9,
This reset period may be a time that allows the output of the differential stage to be reset. During this time, the amplification stage 220 is inactive.

Then, the switch 541 is turned off to end the reset period, and then the switches 223 and 224 are turned on to activate (operate) the amplification stage 220. At this time, the drive circuit of FIG. 8 is equivalent to the voltage follower circuit 920 of FIG. 15 (states in which the switches 951, 952, and 953 are turned on).

Therefore, the connection switching 2 output period shown in FIG.
In the driving circuit of, the input terminal voltage Vin is Vin <V
When it becomes out, the output signal voltage of the differential circuit rises,
Since the n-channel transistor 221 is turned on, Vout can be quickly reduced to Vin with high discharge capability.

Further, the input terminal voltage Vin is Vin> Vo
When it becomes ut, the output signal voltage of the differential circuit decreases, the n-channel transistor 221 turns off, and the current source 222
The output terminal voltage Vout is raised to the input terminal voltage Vin by the charging action of.

The reset circuit 540 of this embodiment has an effect of preventing output noise before and after connection switching. For example,
If the output voltage of the differential circuit is at a high potential immediately before the connection is switched, the n-channel transistor 221 of the amplification stage 220 is momentarily turned on immediately after the connection is switched, regardless of the input terminal voltage Vin. May change and output noise may occur.

However, in the present embodiment, such output noise can be prevented by resetting the output 3 of the differential circuit by the reset circuit 540 so that the n-channel transistor 211 is turned off. Although FIG. 8 shows an example in which the switch 541 is used for resetting, it goes without saying that another configuration may be used. Differential circuit switches 114, 115, 118, 119, 12
0 may be turned on in synchronization with the switches 223 and 224.

The drive circuit shown in FIG. 8 has the same output characteristics as the drive circuit shown in FIG. 5, and is connected even if the characteristics of the transistor pair of the differential circuit deviate from the standard characteristics due to the manufacturing process or the like. (Vin-Vout) in switching 1 and 2
The direction of deviation is the same, and even if the connection is switched (Vin-
It is possible to reduce the deviation of the deviation of (Vout). Therefore, this drive circuit is suitable for an amplifier for amplifying a gradation voltage of a liquid crystal display device or the like.

Next, a fifth embodiment of the present invention will be described. FIG. 10 is a diagram showing the configuration of the fifth embodiment of the present invention, and is a diagram showing another circuit configuration of the drive circuit of FIG. In FIG. 10, the amplification stage 310 is the amplification stage 2 of FIG.
The current source 212 and the switch 214 of FIG. 10 are replaced with the circuit 410, and the amplification stage 320 is configured by replacing the current source 222 and the switch 224 of the amplification stage 220 of FIG. 8 with the circuit 420. Other configurations are as follows. , The same as in FIG.

Referring to FIG. 10, the differential circuit differentially inputs the voltage of the input terminal 1 (input terminal voltage) Vin and the voltage of the output terminal 2 (output terminal voltage) Vout.

The amplification stage 310 is connected between the high-potential side power supply VDD and the output terminal 2, and has a p-channel transistor 311 (charging circuit) whose gate receives the output signal of the differential circuit, and the output terminal 2. And a p-channel transistor 41 of follower configuration connected between the low-side power supply VSS and
2, and a diode-connected p-channel transistor 411 that is inserted between the input terminal 1 and the low-potential-side power supply VSS, is driven by a constant current source 414, and has a gate connected to the gate of a transistor 412 having a follower configuration. And a follower discharge circuit 410. Further, the amplification stage 310 includes a transistor 412 and a low-side power source VSS.
Switch 553 inserted between and and transistor 4
11 and the low-side power supply VSS, a switch 552 connected in series with the constant current source 414 and a transistor 411.
A switch 441 and a constant current source 413, which are connected in series, are provided between the high-side power supply VDD and the high-potential power supply VDD.

The amplification stage 320 is connected between the low potential side power supply VSS and the output terminal 2, and an n-channel transistor 321 (discharge circuit) for inputting the output signal of the differential circuit to its gate.
And an n-channel transistor 422 having a follower configuration connected between the output terminal 2 and the high-potential side power supply VDD, and inserted between the high-potential side power supply VDD and the input terminal 1, driven by the constant current source 424, and having a gate of the follower configuration. Transistor 423
And a follower type charging circuit 420 including a diode-connected n-channel transistor 421 connected to the gate of the. The amplification stage 320 includes a switch 563 that is inserted between the transistor 422 and the high power supply VDD, and a switch 56 that is connected in series with the constant current source 424 between the transistor 421 and the high power supply VDD.
2, a switch 561 and a constant current source 423 connected in series between the transistor 421 and the low potential side power supply VSS. 10, a configuration other than the differential circuit, that is, a transistor 311 forming a feedback type charging circuit together with the differential circuit, a transistor 321 forming a feedback type discharging circuit together with the differential circuit, a source follower discharging circuit 410, a source follower charging circuit. Details of 420 are described in a document (Japanese Patent Application No. 2000-402079, Japanese Patent Application No. 2001-373302, which has not been published at the time of filing this application).

Also in FIG. 10, the output terminal 3 of the differential circuit is used.
Are connected to the amplification stages 310 and 320, the amplification stages 310 and 320 operate according to the output of the differential circuit, and a voltage equal to the input voltage Vin can be output as Vout to the output terminal 2. .

An input terminal voltage Vin (input voltage VinP in FIG. 1) and an output terminal voltage Vout (input voltage VinM in FIG. 1) are input to the two input terminals of the differential circuit,
It has a configuration of a feedback type amplifier circuit. The output of the differential circuit is common to the amplification stages 310 and 320,
Reset circuits 530 and 540 are provided to reset the outputs of the differential circuits before operating the amplification stages 310 and 320.

The source follower discharge circuit 410 includes a p-channel transistor 411 which is diode-connected and receives the input terminal voltage Vin at the source, a source connected to the output terminal 2, a gate connected to the gate of the p-channel transistor 411, and a drain connected to the drain. P-channel transistor 412 connected to low power supply VSS via switch 553
And a current source 413 and a switch 551 connected in series between the source of the p-channel transistor 411 and the high-potential power supply VDD, and between the drain of the p-channel transistor 411 and the low-potential power supply VSS. Current source 414 and switch 552 connected in series
And are provided and configured.

The operation of the source follower discharge circuit 410 will be briefly described below. Note that the details thereof are referred to the above-mentioned document (Japanese Patent Application No. 2000-403079, Japanese Patent Application No. 2001-373302).

The operation of the source follower discharge circuit 410 is as follows.
It is controlled by the switches 551, 552, and 553, and becomes operable when each switch is on, and stops operating when each switch is off.

When the source follower discharge circuit 410 is operable, the p-channel transistors 411 and 41 are
2 have the same transistor characteristics, and current sources 413, 414
, The transistors 411,
The gate voltage of 412 is a voltage deviated from the input terminal voltage Vin by the gate-source voltage. At this time, Vi
If n <Vout, the p-channel transistor 412
The gate-source voltage of the p-channel transistor 412 is larger than the threshold voltage,
The output terminal voltage Vout is lowered by the discharging action of.

When the output terminal voltage Vout decreases, the gate-source voltage of the p-channel transistor 412 decreases, and the discharge action is stopped when the voltage approaches the threshold voltage. Here, when the current controlled by the current sources 413 and 414 is sufficiently small, the p-channel transistor 4
Since the gate-source voltage of 11 is also near the threshold voltage, the output terminal voltage Vout is changed to the input terminal voltage Vin by the source follower operation of the p-channel transistor 412.
It is lowered to the vicinity.

When Vin> Vout, the gate-source voltage of the p-channel transistor 412 becomes a value at which the transistor is turned off, so that the output terminal voltage Vo
It does not contribute to the fluctuation of ut.

On the other hand, the source follower charging circuit 420 is
An n-channel transistor 421 that is diode-connected and receives the input terminal voltage Vin at the source, and an n-channel transistor 42 that is connected at the source to the output terminal 2 and at the gate
An n-channel transistor 422 connected to the gate of 1 and having a drain connected to the high-potential power supply VDD via the switch 563, and further connected in series between the source of the n-channel transistor 421 and the low-potential power supply VSS. Current source 423 and switch 561, and current source 424 and switch 5 connected in series between the drain of the n-channel transistor 421 and the high potential power supply VDD.
It is configured to include 62.

The operation of the source follower charging circuit 420 will be briefly described below. Source follower charging circuit 4
The operation of 20 is controlled by the switches 561, 562, 563. When each switch is on, it becomes operable, and when each switch is off, the operation is stopped.

When the source follower charging circuit 420 is operable, the n-channel transistors 421, 42 are
2 have the same transistor characteristics, and current sources 423, 424
, The transistors 421,
The gate voltage of 422 is gated from the input terminal voltage Vin.
The voltage is shifted by the voltage between the sources. At this time, Vin
When> Vout, the gate-source voltage of the n-channel transistor 422 is larger than the threshold voltage, and the output terminal voltage Vout is raised by the charging action of the n-channel transistor 422 by the source follower operation.

Then, as the output terminal voltage Vout rises, the gate-source voltage of the n-channel transistor 422 decreases, and when the voltage becomes close to the threshold voltage,
Charging stops. Here, when the currents controlled by the current sources 423 and 424 are sufficiently small, the gate-source voltage of the n-channel transistor 421 also becomes close to the threshold voltage, so that the output follower operation of the n-channel transistor 422 causes the output terminal voltage Vout. Is pulled up to near the input terminal voltage Vin.

Further, when Vin <Vout, the gate-source voltage of the n-channel transistor 422 becomes a value at which the transistor is turned off, so that the output terminal voltage Vo
It does not contribute to the fluctuation of ut.

FIG. 11 shows an example of each switch control in the output period of connection switching 1 and the output period of connection switching 2 in the drive circuit shown in FIG. The operation of the drive circuit of FIG. 10 will be described below with reference to FIG.

First, in the output period of the connection switching 1, the switches 111, 112, 113, 116, 117 of the differential circuit are turned on, and the switches 114, 115, 118, 119 ,.
Turn off 120.

At the beginning of the output period, the reset circuit 53
Switch 531 of 0 is turned on, and output 3 of the differential circuit
Are precharged during a reset period that is sufficiently short to the high power supply voltage VDD.

Then, the switch 531 is turned off to end the reset period, and then the switches 532, 55
1, 552 and 553 are turned on to operate the amplification stage 310. Here, the input terminal voltage Vin is Vin> Vo
When it is ut, the output of the differential circuit is lowered, the p-channel transistor 311 is turned on, and the output terminal voltage Vout can be quickly raised to the input terminal voltage Vin with high charging capability.

Further, when the input terminal voltage Vin is Vin <Vo
If it is ut, the voltage of the output 3 of the differential circuit rises and p
The channel transistor 311 is turned off and the circuit 410
The output terminal voltage Vout is lowered to the input terminal voltage Vin due to the discharging action of.

Since the source follower discharge circuit 410 performs a source follower discharge action, the larger the voltage difference between the input terminal voltage Vin and the output terminal voltage Vout, the higher the discharge capability, and the output terminal voltage Vout becomes the input terminal voltage Vin.
The discharge capability decreases as the temperature approaches.

The source follower discharging operation of the source follower discharging circuit 410 instantly operates without delay according to the voltage difference between Vin and Vout. Therefore, even when the high-speed charging action of the p-channel transistor 311 causes an overshoot due to the response delay of the feedback configuration, the source follower discharge circuit 410 quickly suppresses the overshoot and stabilizes the output terminal voltage Vout at Vin. Has the effect of causing.

Therefore, the drive circuit shown in FIG.
It is also possible to realize the output stabilization by not requiring the phase compensation capacity for stabilizing the output, or by providing the phase compensation capacity which is sufficiently small.

On the other hand, in the output period of the connection switching 2, the switches 111, 112, 113, 116, 117 of the differential circuit are provided.
Off, switches 114, 115, 118, 119, 1
Turn on 20. At the beginning of the output period, the switch 541 of the reset circuit 540 is turned on to discharge the output 3 of the differential circuit to the low power supply voltage VSS for a sufficiently short reset period.

Then, the switch 541 is turned off to end the reset period, after which the switches 542, 561,
The amplification stage 320 is operated by turning on 562 and 563.

Here, the input terminal voltage Vin is Vin <V
When it is out, the output of the differential circuit rises and the n-channel transistor 321 is turned on, and the output terminal voltage Vout can be quickly lowered to the input terminal voltage Vin with high discharge capability.

Further, the input terminal voltage Vin is Vin> Vou
At t, the output of the differential circuit decreases and the n-channel transistor 321 is turned off, and the output terminal voltage Vout is raised to the input terminal voltage Vin by the charging action of the source follower charging circuit 420.

Since the source follower charging circuit 420 performs the source follower charging operation, the charging capability is higher as the voltage difference between Vin and Vout is larger, and the charging capability is reduced as Vout approaches Vin. In addition, the source follower charging operation of the source follower charging circuit 420 operates instantly without delay according to the voltage difference between Vin and Vout. Therefore, even if the high-speed discharging action of the n-channel transistor 321 causes undershoot due to the response delay of the feedback configuration, the source follower charging circuit 420 quickly suppresses the undershoot and changes the output terminal voltage Vout to the input terminal voltage Vin. It has a stabilizing effect on.

Therefore, the drive circuit shown in FIG.
It is also possible to realize output stabilization by not requiring a phase compensation capacitor for stabilizing the output or by providing a sufficiently small phase compensation capacitor.

As described above, in the voltage follower configuration, the phase compensation capacitance for stabilizing the output is not required, which is one of the main features of the present invention. The sufficiently small phase compensation capacitance is exclusively used for waveform shaping.

The reset circuits 530 and 540 have an effect of preventing output noise before and after connection switching on the same principle as the drive circuit of FIG. In addition, the switch 111 of the differential circuit,
112, 113, 116, 117 are switches 532, 5
It may be turned on in synchronization with 51, 552 and 553. Similarly, switches 114, 115, 11 of the differential circuit
8, 119 and 120 are switches 542, 561 and 56.
It may be turned on in synchronization with 2,563.

The drive circuit shown in FIG. 10 has the same output characteristics as the drive circuit shown in FIG. 5, and even if the characteristics of the transistor pair of the differential circuit deviate from the standard characteristics due to the manufacturing process or the like, the connection is made. (Vin-Vo in switching 1 and 2
ut) is in the same direction, and even if the connection is switched,
It is possible to suppress the deviation of the deviation of (Vin-Vout) to be small. Therefore, the drive circuit shown in FIG.
It is suitable for an amplifier for amplifying gradation voltage of a liquid crystal display device.

FIG. 12 is a diagram showing a modification of the drive circuit shown in FIG. In FIG. 12, regarding the configuration other than the differential circuit, reference is made to a document (Japanese Patent Application No. 2000-402079, Japanese Patent Application No. 2001-373302).
The details are described. 12 has a smaller number of elements than the configuration shown in FIG. 10. The circuit 410 of FIG. 10 is replaced with a circuit 430, and a circuit 420 of FIG.
Is replaced with a circuit 440, and other configurations are the same as those in FIG.

In FIG. 12, elements having the same functions as those of the element shown in FIG. 10 have the same reference numerals. 12
Then, the transistor 419 in which the drain and the source are connected to the drain and the source of the transistor 421, respectively.
429 in which the source and the drain are connected to the source and the drain of the transistor 411, respectively, and predetermined bias voltages BN and BP are applied to the gates of the transistors 419 and 429, respectively.

FIG. 13 shows an example of each switch control in the output period of connection switching 1 and the output period of connection switching 2 in the drive circuit of FIG. Reset circuits 530, 5
Since the control and operation of 40 are the same as those in FIGS. 10 and 11, the description thereof will be omitted, and description will be made after the reset period is completed. In the output period of the connection switching 1, the switch 5 is set after the reset period ends.
32 and 553 are turned on to turn the p-channel transistor 31
1 and the circuit 430 are operated. At this time, the bias voltage B
N controls the transistor 419 to turn off, and the bias voltage BP controls so that the current controlled by the current source 425 flows between the high potential power supply VDD and the input terminal 1. This makes circuit 430 equivalent to circuit 410 of FIG. On the other hand, in the output period of the connection switching 2, after the reset period ends, the switches 542 and 563 are turned on to operate the n-channel transistor 321 and the circuit 440. At this time, the bias voltage BP is controlled so that the transistor 429 is turned off, and the bias voltage BN is controlled so that the current controlled by the current source 415 flows between the low potential power supply VSS and the input terminal 1. This causes circuit 440 to move to circuit 42 of FIG.
It is equivalent to 0. Therefore, the drive circuit of FIG. 12 has the same performance as the drive circuit of FIG.

The reset circuits 530 and 540 shown in FIGS. 8, 10, and 12 will be additionally described below. Reset circuit 53 for resetting the output 3 of the differential circuit
0 and 540 may have a configuration other than the switches 531 and 541 shown in FIGS. 8, 10, and 12. Figure 17
FIG. 9 is a diagram showing a modification in which the reset circuits 530 and 540 are different from each other in the amplifier circuit according to the fourth embodiment shown in FIG. 8. The circuit configuration shown in FIG. 17 is the same as that shown in FIG. 8 except for the reset circuits 530 and 540.

Referring to FIG. 17, reset circuit 530
Is a high-side power supply VDD, a switch 531 inserted between the gate of the transistor 211 and one end of the capacitor C1, a connection point between the gate of the transistor 211 and one end of the capacitor C1, and a differential circuit. Switch 533 inserted between the output terminal 3 and the output terminal 3. On the other hand, the reset circuit 540 includes a switch 541 inserted between the low-potential-side power supply VSS, a connection point between the gate of the transistor 221 and one end of the capacitor C2, and the transistor 221.
And a switch 543 inserted between the connection point between the gate of the capacitor and one end of the capacitor C1 and the output terminal 3 of the differential circuit. The switches 533 and 543 are the switches 5
The output 3 of the differential circuit is reset at the time of switching between charging and discharging by switching ON and OFF of 31, 31 and 541, and has an action of preventing unnecessary voltage fluctuation of the output terminal voltage Vout at switching between charging and discharging.

FIG. 18 is a timing chart for explaining the operation and action of the reset circuit. The switches 111 to 120, 213 to 214, 531 and 53 of FIG.
The operation timing of on / off control of 3, 541 and 543 is shown. Of these, the switch 111 of the differential circuit
Since the same control as that shown in FIG. 9 is performed for steps 120 to 120, the description thereof will be omitted.

Referring to FIG. 18, in the state of connection switching 1, the switches 213, 214, 533 and 541 are turned on and the switches 223, 224, 531 and 543 are turned off. This enables the charging operation by the amplification stage 210. At this time, the amplification stage 220 is in the inactive state, and the gate of the transistor 221 and the capacitor C2 are discharged to the lower power supply VSS.

On the other hand, in the state of connection switching 2, switch 2
13, 214, 533, 541 are turned off, and switch 2
23, 224, 531, and 543 are turned on. This enables the discharging operation by the amplification stage 220. At this time, the amplification stage 210 is in the inactive state, and the gate of the transistor 211 and the capacitor C1 are at the high-side power supply VDD.
Will be charged.

When the state of connection switching 1 is switched to the state of connection switching 2 (switch 543 is turned on, switch 5
41 is turned off), and the output terminal 3 of the differential circuit and the gate of the transistor 221 have the low-side power supply V
The capacitor C2 discharged to SS temporarily lowers the voltage to the vicinity of the low-potential side power supply voltage VSS, and then starts the discharging operation according to the input terminal voltage Vin. Therefore, the operation of the amplification stage 220 is not affected by the potential of the output terminal 3 of the differential circuit before switching to the state of the connection switching 2 and immediately starts its operation from the inactive state to generate noise. There is no such thing.

When the connection switching 2 state is switched to the connection switching 1 state (the switch 533 is turned on and the switch 531 is turned off), the output terminal 3 of the differential circuit and the gate of the transistor 211 are connected and switched. At the time of 2, the capacitor C1 charged in the high-potential power supply VDD raises the voltage to near the high-potential power supply voltage VDD, and then starts the charging operation according to the input terminal voltage Vin.
Therefore, the operation of the amplification stage 210 is not affected by the potential of the output terminal 3 of the differential circuit before the switching to the connection switching 1, the operation is quickly started from the inactive state, and no noise is generated. .

In addition, the reset circuits 530 and 54 of FIG.
As shown in FIG. 18, 0 can control the switches of the reset circuit in synchronization with the control of the switches of the differential circuit. As a result, the number of control signals can be reduced.

Incidentally, the switch 213 and the switch 531
Since they both operate to inactivate the transistor 211, the switch 213 may be removed and the source of the transistor 211 may be directly connected to the high potential side power supply VDD. Similarly, switch 223 and switch 5
Since both 41 act to deactivate the transistor 221, the switch 223 may be removed and the source of the transistor 221 may be directly connected to the low potential side power supply VSS.

As described above, the reset circuit 53 of FIG.
The capacitors 0 and 540 use the capacitors C1 and C2 to prevent the output noise from occurring before and after the switching of the connection state. The reset circuit similar to the circuit shown in FIG. 17 can be applied to the drive circuits shown in FIGS. 10 and 12 as well, for example, when optimal capacitors are connected to the gates of the transistors 311 and 321. . Alternatively, even when the capacitance for waveform shaping is not provided, the reset circuit similar to that in FIG. 17 can be applied even when the sizes of the transistors 211 and 221 are large and the gate capacitance is large to some extent.

FIG. 14 is a diagram for explaining the sixth embodiment of the present invention, and is a diagram showing an example in which a multi-output drive circuit is configured by the drive circuit of the present invention. This embodiment can be used as a drive circuit of a liquid crystal display device. As the output circuit 100, the drive circuit of each of the embodiments described with reference to FIGS. 5, 8, 10 and 12 can be used. The control signal controls the switch of each drive circuit. The analog gradation voltage is output from the tap of the voltage dividing resistor provided between the reference voltages VH and VL, and the decoder 300 and the output terminal group 400 are output.
And an output stage 100. From the plurality of grayscale voltages generated from each terminal (tap) of the resistor string 200, the grayscale voltage is selected by the decoder 300 according to the video digital signal for each output, and the output circuit 100
Then, the data line connected to the output terminal 400 is driven. In the output circuit 100, even when the differential circuit of the n-channel differential pair and the differential circuit of the p-channel differential pair are switched, in the stable state, the direction of the deviation of the differential input voltage due to the dispersion of the element characteristics is detected. They can be made the same, the directions of output offsets due to variations in element characteristics can be made the same, and the amplitude difference deviation can be suppressed, thereby improving the display image quality.

The differential circuit and amplifier circuit (driving circuit) described in the above embodiments are composed of MOS transistors. In the driving circuit of the liquid crystal display device, for example, a MOS transistor (TFT) made of polycrystalline silicon. You may comprise. Further, it goes without saying that the differential circuit described in the above embodiment can be applied to a bipolar transistor. In this case, the p-channel transistors 101 and 102 on the higher power supply side are pnp transistors, and the n-channel transistors 103 and 104 on the lower power supply side are
It is composed of an npn transistor. In the above embodiment, the example applied to the integrated circuit is shown, but two transistor pairs are
Of course, the circuit configuration for switching between the differential pair and the current mirror can be applied to the discrete element configuration.

The present invention has been described above with reference to the above embodiments, but the present invention is not limited to the above embodiments, and the present invention is applicable within the scope of the invention of each claim of the claims of the present application. Of course, it includes various variations and modifications that can be made by those skilled in the art.

[0165]

As described above, according to the present invention,
Even when the differential circuits having different polarities are switched, in the stable state, the deviation directions (plus side and minus side) of the differential input voltages VinP and VinM can be made the same due to variations in element characteristics. Therefore, the directions of the output offsets due to the variations in the element characteristics are the same, and it is possible to suppress the amplitude difference deviation.

According to the present invention, the n-channel transistor pair is a differential pair when the high-side voltage is driven, the p-channel transistor pair is a current mirror circuit, and the p-channel transistor pair is the low-side voltage when driven. By performing switching control so that a differential pair and an n-channel transistor pair become a current mirror circuit, there is an effect that full range output is possible.

Further according to the present invention, one of the two transistor pairs is a differential pair or a current mirror,
Since the other pair is switched to the differential pair or the other of the current mirrors, the circuit scale can be reduced, and the power consumption can be reduced.

Further, according to the present invention, the maximum value of the amplitude difference deviation of the amplifier circuit is suppressed to about twice the absolute value of the difference between the output offsets during the high potential side driving and the low potential side driving. By using such an amplifier circuit in a data line driver circuit of a display device, display image quality can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing control of connection switching according to the first embodiment of this invention.

FIG. 3 Connection switching 1, 2 in the first embodiment of the present invention
3 is a diagram for explaining circuit connection and operation in FIG.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 6 is a diagram showing control of connection switching according to the third embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the third exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 9 is a timing chart showing switch control according to the fourth embodiment of the present invention.

FIG. 10 is a diagram showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 11 is a timing chart showing switch control according to the fifth embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a fifth exemplary embodiment of the present invention.

FIG. 13 is a timing chart showing switch control according to the sixth embodiment of the present invention.

FIG. 14 is a diagram showing a configuration of a sixth exemplary embodiment of the present invention.

FIG. 15 is a diagram showing a configuration of a conventional differential circuit.

FIG. 16 is a diagram for explaining an amplitude difference deviation in a conventional differential circuit.

FIG. 17 is a diagram showing a modification of the fourth embodiment of the present invention.

FIG. 18 is a timing chart showing switch control according to a modification of the fourth embodiment of the present invention.

[Description of Reference Signs] 1 input terminal 2 output terminal 3 output of differential circuit 100 output circuit 101, 102, 211, 311, 411, 412, 4
29, 911, 912, 923, 924 p-channel transistors 103, 104, 221, 321, 421, 422, 4
19, 913, 914, 921, 922 n-channel transistors 105, 106, 212, 222, 413, 414, 4
23, 424, 915, 917, 925, 927 constant current sources 111 to 120, 213, 214, 223, 224, 5
31, 532, 543, 541, 542, 543, 55
1, 552, 553, 561, 562, 563, 95
1, 952, 953, 961, 962, 963 switch 200 resistor 210 amplification stage (for charging) 220 amplification stage (for discharging) 300 switch 310 amplification stage (for charging) 320 amplification stage (for discharging) 400 output terminal group 410, 430 Source follower charging circuit 420, 440 Source follower discharging circuit 510 Amplifying stage (for charging) 520 Amplifying stage (for discharging) 530, 540 Reset circuit 910, 920 Voltage follower circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/36 G09G 3/36 F term (reference) 5C006 BC11 BF25 FA20 FA47 5C080 AA10 DD26 JJ03 JJ04 5J066 AA01 AA12 AA51 CA00 CA34 CA36 FA18 HA09 HA17 HA25 HA29 HA38 HA39 KA02 KA05 KA09 MA21 ND01 ND12 ND22 ND23 PD02 SA00 TA01 TA02 TA06 5J500 AA01 AA12 AA51 AC00 AC34 AC36 AF18 AH09 AH17 AH25 AH29 AH38 AH39 AK02 AK05 AK09 AM21 AS00 AT01 AT02 AT06 DN01 DN12 DN22 DN23 DP02

Claims (31)

[Claims] 1. A first transistor pair of a first conductivity type and a second transistor pair of a second conductivity type, wherein an output pair of the first transistor pair is of the second transistor pair. A current source and a switch connected in parallel between the common tail of the first transistor pair and the first power supply, the common tail of the second transistor pair being connected to the output pair; A current source and a switch are connected in parallel between the tail and the second power supply, and each transistor pair is connected to a differential pair driven by the current source and receiving a differential input voltage from the input pair. , A pair of input transistors are connected to each other, one of the transistors is diode-connected, and a current mirror circuit serving as a load of the differential pair, and a connection switching unit that is switchable between the pair of the first and second transistor pairs. One side The differential circuit, wherein the other transistor pair is a current mirror circuit when the other transistor pair is a differential pair. 2. A first transistor pair of a first conductivity type and a second transistor pair of a second conductivity type, wherein the drain of the first transistor pair is the drain of the second transistor pair. A first current source and a first switch are connected in parallel between a commonly connected source of the first transistor pair and a first power supply, and the first current source and the first switch are connected in parallel. A second current source and a second switch are connected in parallel between the commonly connected sources of the second transistor pair and the second power source, and the first transistor pair is commonly connected. A source connected to the first power supply via the first current source,
A differential pair that receives a differential input voltage at its gate, wherein the second transistor pair has their gates connected to each other,
A first connection configuration in which a commonly connected source is connected to the second power source through the second switch, and a gate and a drain of one transistor are connected to each other to form a current mirror circuit; A second transistor pair, the commonly connected sources of which are connected to the second power source via the second current source;
A differential pair that receives a differential input voltage at its gates, wherein the first transistor pair has gates connected to each other,
A second connection configuration in which a source connected in common is connected to the first power supply through the first switch, and a gate and a drain of one transistor are connected to each other to form a current mirror circuit; And a connection switching unit that controls switching from the first connection configuration to the second connection configuration and from the second connection configuration to the first connection configuration. Characteristic differential circuit. 3. The first transistor pair is a p-channel transistor pair, the second transistor pair is an n-channel transistor pair, the first power supply is a high-side power supply, and the second power supply is Is a low-side power supply, and when driving a high-side voltage, the n-channel transistor pair is a differential pair and the p-channel transistor pair is a current mirror circuit, and when driving a low-side voltage, the p-channel transistor pair is a differential pair. 3. The differential circuit according to claim 1, wherein the switching of the connection switching means is controlled so that the n-channel transistor pair is a current mirror circuit. 4. The first and second transistors of the first conductivity type, the sources of which are commonly connected, the drains of which are respectively connected to the drains of the pair of transistors of the first conductivity type, and the sources of which are commonly connected. Are connected in parallel between the third and fourth transistors of the second conductivity type, the common connection node of the sources of the first and second transistors, and the first power supply. A first switch and a first current source, a common connection node of the sources of the third and fourth transistors, and a second power supply, which are connected in parallel. A switch and a second current source, and third and fourth switches connected in series between the gates of the first and second transistors, respectively, and the third and fourth Of each gate of the transistor Is inserted between the fifth and sixth switches connected in series, the connection node between the gate of the first transistor and the third switch, and the first input terminal. A seventh switch, an eighth switch inserted between a connection node between the gate of the second transistor and the fourth switch, and a second input terminal, and the third transistor Connection node between the gate of the fifth switch and the fifth switch, a ninth switch inserted between the first input terminals, a connection node between the gate of the fourth transistor and the sixth switch And a tenth switch inserted between the second input terminal and the second input terminal, a connection node between the third switch and the fourth switch, the fifth switch and the 6 and the connection node with the switch Connected to a connection node between the drain of the second transistor and the drain of the fourth transistor, the common connection node of which is connected to the drain of the first transistor and the drain of the third transistor. A differential circuit characterized in that a connection node with a drain is connected to an output terminal. 5. The first, third, fourth, ninth, and tenth
Switch is turned on and the second, fifth, sixth, seventh and eighth switches are turned off, or the first, third, fourth and ninth switches are turned on. , And the tenth switch are turned off, and the second, fifth, sixth, seventh, and
The differential circuit according to claim 4, wherein the eighth switch is turned on. 6. The first, third, and fourth switches are
It is composed of a transistor of a first conductivity type whose gate is an inverted signal of the first control signal, and turns on when the first control signal has a first logical value, and the second, fifth, and The sixth switch is formed of a second conductivity type transistor having a gate that receives the second control signal, and is turned on when the second control signal has a first logical value. The eighth switch is a CMOS whose gate receives the second control signal and its inverted signal, respectively.
A transfer gate, which is turned on when the second control signal has a first logical value, and the ninth and tenth switches respectively have the first control signal and an inverted signal thereof as gates. CM to be input
The differential circuit according to claim 4, comprising an OS transfer gate, which is turned on when the first control signal has a first logical value. 7. The first and second transistors are p-channel transistor pairs, the third and fourth transistors are n-channel transistor pairs, and the first power source is a high-side power source, The second power source is a low-potential side power source, and when the high-side voltage is stably driven, the n-channel transistor pair is a differential pair, the p-channel transistor pair is a current mirror circuit, and when the low-side voltage is stably driven, The p-channel transistor pair is a differential pair, and the first, third, fourth, ninth and tenth switches and the second and fifth switches are arranged so that the n-channel transistor pair becomes a current mirror circuit. ,
The differential circuit according to claim 4, wherein switching is controlled by conduction states of the sixth, seventh, and eighth switches. 8. The differential circuit according to claim 1, a charging amplification stage for charging an output terminal by receiving an output signal of the differential circuit, and an output signal of the differential circuit. An amplifying circuit for discharging, which receives the output terminal and discharges the output terminal, wherein the output terminal is fed back to an inverting input terminal of a differential input terminal of the differential circuit. 9. A first reset circuit for controlling the output signal of the differential circuit to deactivate the charging amplification stage for a predetermined period. The amplifier circuit according to claim 8. 10. A second reset circuit for controlling the output signal of the differential circuit to deactivate the discharge amplification stage for a predetermined period. The amplifier circuit according to claim 8. 11. A fifth transistor of the first conductivity type, wherein the charging amplification stage receives the output signal of the differential circuit at its gate, and its drain is connected to the output terminal, Between the source and the first power source forming the high-potential side power supply, the drain of the fifth transistor, and the second power source forming the low-potential side power supply, The amplifier circuit according to claim 8, further comprising: a twelfth switch and a third current source connected in series. 12. A sixth transistor of the second conductivity type, wherein the discharge amplification stage receives the output signal of the differential circuit at its gate and its drain is connected to the output terminal, and the sixth transistor. , A thirteenth switch inserted between the second power source that forms the low-side power source, the drain of the sixth transistor, and the first power source that forms the high-side power source, 9. The amplifier circuit according to claim 8, further comprising a fourteenth switch and a fourth current source connected in series. 13. The apparatus according to claim 11, further comprising a first reset circuit having a fifteenth switch inserted between the first power supply and the gate of the fifth transistor. The described amplifier circuit. 14. The apparatus according to claim 12, further comprising a second reset circuit having a sixteenth switch inserted between the second power supply and the gate of the sixth transistor. The described amplifier circuit. 15. The differential circuit according to claim 1, wherein the differential circuit differentially inputs an input terminal voltage and an output terminal voltage, and an output signal of the differential circuit. A charging circuit for charging the output terminal based on the above; a first bias control means for controlling the output bias voltage by receiving the input terminal voltage; the output terminal; and a second power supply which is a low-side power supply. And a follower transistor that receives the bias voltage output from the first bias control means as an input, and the follower operation of the active element according to the voltage difference between the input terminal voltage and the output terminal voltage. A follower discharge circuit that discharges the output terminal by a discharge circuit that discharges the output terminal based on the output signal of the differential circuit; and an output bias voltage that receives the input terminal voltage. A second bias control means for controlling; a follower transistor, which is connected between the first power supply which is a high-side power supply and the output terminal, and which receives the bias voltage of the second bias control means as an input. A follower type charging circuit for charging the output terminal by a follower operation of an active element according to a voltage difference between the input terminal voltage and the output terminal voltage. 16. A differential circuit according to claim 4, wherein the differential circuit differentially inputs an input terminal voltage and an output terminal voltage to form a high-potential-side power supply. Charging circuit including a seventh transistor of the first conductivity type, which is connected between the power supply and the output terminal and receives the output signal of the differential circuit at its gate, the output terminal, and a low-side power supply. An eighth transistor of the first conductivity type having a follower structure connected between the second power source and the second power source, which is inserted between the input terminal and the lower power source, and is driven by a fifth constant current source, A follower discharge circuit having a diode-connected first conductivity type ninth transistor whose gate is connected to the gate of the follower-structured eighth transistor; and a low-side power supply and the output terminal. Connected between the outputs of the differential circuit A discharge circuit including a second conductivity type tenth transistor for inputting a signal to a gate; a second conductivity type eleventh transistor having a follower configuration connected between the output terminal and a high potential side power supply; and the high potential side. It is inserted between a power source and the input terminal, is driven by a sixth constant current source, and has a gate having the eleventh follower configuration.
And a follower-type charging circuit having a diode-connected twelfth transistor of the second conductivity type that is connected to the gate of the transistor. 17. A seventeenth switch inserted between the eighth transistor of the follower configuration and the low-potential side power supply, and the fifth switch between the ninth transistor and the low-potential side power supply. An eighteenth switch connected in series with a constant current source, a nineteenth switch and a seventh constant current source connected in series between the ninth transistor and the high-potential-side power supply, And a twentieth switch inserted between the eleventh transistor of the follower configuration and the high-potential power supply, and between the twelfth transistor and the high-potential power supply,
A twenty-first switch connected in series with the sixth constant current source, and between the twelfth transistor and the low-potential-side power supply,
The 22nd switch and the 8th constant current source connected in series form are provided, The amplifier circuit of Claim 16 characterized by the above-mentioned. 18. A thirteenth transistor of the first conductivity type, wherein a source and a drain are connected to a source and a drain of the ninth transistor, respectively, and a predetermined bias voltage is input to a gate, and a twelfth transistor of the twelfth transistor. The source and the drain are respectively connected to the source and the drain, and the fourteenth transistor of the second conductivity type for inputting a predetermined bias voltage to the gate is provided, and the amplification according to claim 16. circuit. 19. The method according to claim 16, further comprising a first reset circuit having a twenty-third switch inserted between the high-potential side power supply and the gate of the seventh transistor. The amplifier circuit described in Kaichi. 20. A second reset circuit having a twenty-fourth switch inserted between the low-potential-side power supply and the gate of the tenth transistor, wherein the second reset circuit is provided. The amplifier circuit described in Kaichi. 21. A twenty-fifth aspect in which the first reset circuit is inserted between a connection point between the gate of the fifth transistor and the fifteenth switch and an output terminal of the differential circuit. The amplifier circuit according to claim 13, further comprising a switch. 22. A twenty-sixth aspect in which the second reset circuit is inserted between a connection point between the gate of the sixth transistor and the sixteenth switch and an output terminal of the differential circuit. The amplifier circuit according to claim 14, further comprising a switch. 23. The amplifier according to claim 13, wherein the first reset circuit includes a capacitor connected between the drain and the gate of the fifth transistor. circuit. 24. The amplifier according to claim 14, wherein the second reset circuit has a capacitance connected between the drain and the gate of the sixth transistor. circuit. 25. The first, third, fourth, ninth, and tenth switches are turned on, and the second, fifth, sixth, seventh, and eighth switches are turned off. During the predetermined reset period at the beginning of the first connection state, the fifteenth switch is turned on, then the fifteenth switch is turned off, the eleventh and twelfth switches are turned on, and the charging amplification is performed. 14. Amplifier circuit according to claim 13, characterized in that the stage is activated. 26. The first, third, fourth, ninth and first
0 switch is turned off, and the second, fifth,
The predetermined reset period at the beginning of the second connection state in which the sixth, seventh, and eighth switches are turned on, and the first
15. The switch of No. 6 is turned on, then the sixteenth switch is turned off, the thirteenth and fourteenth switches are turned on, and the discharge amplification stage is activated. Amplifier circuit. 27. The first, third, fourth, ninth, and tenth switches are turned on, and the second, fifth, sixth, seventh, and eighth switches are turned off. In the first connection state, the eleventh and twelfth switches are turned on, the fifteenth switch is turned off, and the twenty-fifth switch is turned on.
Switch is turned on, the first, third, fourth, ninth, and tenth switches are turned off, and the second, fifth, sixth, seventh, and eighth switches are turned on. In the second connection state where the switch is turned on, the eleventh and twelfth switches are turned off,
22. The amplifier circuit according to claim 21, wherein the fifteenth switch is turned on and the twenty-fifth switch is turned off. 28. The first, third, fourth, ninth and tenth switches are made conductive, and the second, fifth, sixth, seventh and eighth switches are made non-conductive. In the first connection state, the thirteenth and fourteenth switches are turned off, the sixteenth switch is turned on, and the second switch is turned on.
The sixth switch is turned off, the first, third, fourth, ninth, and tenth switches are turned off, and the second, fifth, sixth, seventh,
And a second connection state in which the eighth switch is turned on, the thirteenth and fourteenth switches are turned on,
23. The amplifier circuit according to claim 22, wherein the 16th switch is turned off and the 26th switch is turned on. 29. The eleventh switch is deleted, and the source of the fifth transistor is directly connected to the first power supply which constitutes a high-side power supply. The amplifier circuit described in. 30. The sixteenth switch is deleted, and the source of the sixth transistor is directly connected to the second power supply which is a low-side power supply. The amplifier circuit described in. 31. A display device comprising the amplifier circuit according to claim 8 as a drive circuit for driving a data line.