KR20180032740A - Method for transmitting signal - Google Patents

Abstract

The present invention relates to a signal transmission method for a display device which comprises: a timing control unit; and a data operating unit which includes a clock data recovery circuit for clock data recovery (CDR) of a differential signal that is transmitted from the timing control unit. The signal transmission method comprises: a step of checking lock or lock fail for CDR; a step of calculating an optimum resistance value where a lock fail rate, that is, a lock fail generation rate per unit time, becomes a minimum while changing a resistance register value of a terminating resistor at a receiving terminal of the data operating unit; a step where the data operating unit sets the resistance register value to the calculated optimum resistance value; a step of calculating an optimum differential swing level where the lock fail rate becomes a minimum while changing a differential swing level register value of a differential signal; a step where the timing control unit sets the differential swing level register value to the calculated optimum differential swing level; a step of calculating an optimum pre-emphasis value where the lock fail rate becomes a minimum while changing a pre-emphasis register value of the differential signal; and a step where the timing control unit sets the pre-emphasis register value to the calculated optimum pre-emphasis value. Therefore, the signal transmission method can secure stability when transmitting data at a high speed.

Description

{METHOD FOR TRANSMITTING SIGNAL}

The present invention relates to a signal transmission method.

A liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting display and organic light emission display (OLED) have been actively researched and developed. Such a display device is provided with various components, and wirings for transmitting signals between the components are formed.

In recent years, due to the development of electronic circuit technology and manufacturing processes, high-speed signal transmission becomes possible through the wirings, and the driving speed of the components becomes very fast enough to cope with high-speed signal transmission. Various methods for high-speed signal transmission have been proposed. For example, a signal transmission method for transmitting a differential signal such as a low voltage differential signaling (LVDS) method or a reduced swing differential signaling (RSDS) method has been adopted .

However, even if the differential signal transmission method is employed, if the data transmission speed is further increased, the signal characteristic becomes sensitive. Therefore, when a little impedance mismatching occurs, an error may occur in the transmitted signal or the signal may be distorted . Therefore, there is a demand for a signal transmission method capable of securing stability in high-speed data transmission.

An object of the present invention is to provide a signal transmission method capable of securing stability in high-speed data transmission.

A signal transmission method according to an embodiment of the present invention includes a timing controller and a data driver having a clock data recovery circuit for clock data recovery (CDR) of a differential signal transmitted from the timing controller, The method of claim 1, further comprising: checking whether a lock or a lock fail for restoring the clock data occurs; Calculating an optimal resistance value that minimizes a lock fail rate which is a rate of generation of the lock fail per unit time while varying a resistance register value of a terminating resistor of a receiving end of the data driver; The data driver setting the resistance register value to the calculated optimum resistance value; Calculating an optimal differential swing level at which the lock fail rate is minimized while varying the differential swing level register value of the differential signal; The timing control unit setting the differential swing level register value to the calculated optimum differential swing level; Calculating an optimum preamplification value that minimizes the lock fail rate while varying a pre-emphasis register value of the differential signal; And the timing controller includes setting the preamplifier register value to the calculated optimum preamplitude value.

In one embodiment, the step of calculating the optimum resistance value may further include: calculating the lock fail rate corresponding to each of the variable resistor resistors as a whole, and setting any one of the resistor resistor values having the minimum lock fail rate as the It can be determined as the optimum resistance value.

In one embodiment, the step of calculating the optimal differential swing level may include calculating the lock fail rate corresponding to each of the variable swing level register values of the entire variable range, The level register value may be determined as the optimum differential swing level.

In one embodiment, the data driver may transmit to the timing controller through the feedback line any one of the differential lock swing level register values corresponding to each of the differential swing level register values, or the lock fail rate, .

In one embodiment, the step of calculating the optimal preamplitude value may include calculating the lock fail rate corresponding to each of all the variable preamplifier register values that can be varied, The amphisys register value can be determined as the optimum preamplification value.

In one embodiment, the data driver transmits, to the timing controller through the feedback line, either one of the lock fail rate corresponding to each of the preamplifier register values or the minimum preamplifier register value having the minimum lock fail rate .

In one embodiment, all of the steps may be performed in an initial setup mode or a standby mode.

A signal transmission method according to another embodiment of the present invention is a signal transmission method of a display device including a timing controller and a data driver having a clock data recovery circuit for recovering clock data of a differential signal transmitted from the timing controller A differential swing level register having a differential swing level register value of the differential signal, a normal range value of the differential swing level at which the lock for restoring the clock data is activated, Calculating a center range value; Setting the differential swing level register value of the differential signal within the calculated center range value of the differential swing level; The data driver may include: monitoring a differential swing level of the differential signal transmitted from the timing controller; The differential swing level register value is varied while the monitored differential swing level deviates from the center range value of the previously stored differential swing level so that the monitored differential swing level is adjusted to be within the center range value of the differential swing level Calculating a differential swing level; And the timing controller includes setting the differential swing level register value to the adjusted differential swing level calculated.

In one embodiment, the step of monitoring the differential swing level of the differential signal may be performed on a frame-by-frame basis.

In one embodiment, the step of setting the differential swing level register value may be performed during a blank period.

In one embodiment, the method may further include storing at least one of a normal range value and a center range value of the differential swing level in a memory.

In one embodiment, a preamplifier register value of the differential signal is varied, a normal range value of a jitter parameter regarding a data packet of the differential signal in which a lock for recovering the clock data is activated, Calculating a center range value of the jitter parameter at a predetermined ratio with respect to a normal range value of the jitter parameter; And the timing controller may further comprise setting a preamplification register value of the differential signal so as to correspond to the calculated center range value of the jitter parameter.

In one embodiment, the data driver monitors the jitter parameter calculated from the differential signal transmitted from the timing controller. Wherein the preamplifier value is changed when the monitored jitter parameter is out of the center range value of the jitter parameter, and the adjusted preamplitude value is adjusted so that the monitored jitter parameter is within the center range value of the jitter parameter, ; And the timing controller may further comprise setting the preamplifier register value to the adjusted preamplitude value.

In one embodiment, the jitter parameter may be a ratio of a first period included in the data period to a data period corresponding to one data packet, or a ratio of a second period included in the data period to the data period.

In one embodiment, the data period may include the first period and the second period that are separated by a center.

In one embodiment, the length of the data period, the first period, and the second period may be calculated by counting a second clock signal having a frequency higher than the frequency of the first clock signal included in the differential signal.

In one embodiment, the data period may be a 1H time.

In one embodiment, the step of monitoring the jitter parameter may be performed on a frame-by-frame basis.

In one embodiment, the step of setting the preamplifier register value may be performed in a blank period.

In one embodiment, the method may further comprise storing at least one of a normal range value and a center range value of the jitter parameter in a memory.

According to the present invention, optimal signal transmission conditions are set so that the lock fail occurrence rate is minimized, or the signal transmission conditions are adjusted in advance before the lock fail occurs, have.

1 is a block diagram schematically illustrating a display device according to an embodiment of the present invention.
2 is a block diagram schematically showing the signal transmission system between the timing controller and the data driver of FIG.
3 is a flowchart illustrating a signal transmission method according to an embodiment of the present invention.
4 is a schematic view showing a display device according to another embodiment of the present invention.
5 is a flowchart illustrating a signal transmission method according to another embodiment of the present invention.
6 is a diagram for explaining the normal range value and the center range value of the differential swing level.
7 is a diagram for explaining jitter parameters.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are shown enlarged from the actual for the sake of clarity of the present invention. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, where a portion such as a layer, film, region, plate, or the like is referred to as being "on" another portion, this includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. In the present specification, when a part of a layer, a film, an area, a plate, or the like is formed on another part image on, the forming direction is not limited to an upper part but includes a part formed in a side or a lower direction . On the contrary, where a section such as a layer, a film, an area, a plate, etc. is referred to as being "under" another section, this includes not only the case where the section is "directly underneath"

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a display device according to an embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention may include a timing controller 110, a data driver 120, a scan driver 130, and a pixel unit 140.

The timing controller 110 receives synchronous signals and clock signals for controlling image data and its display. The timing controller 110 corrects the input image data to fit the image display of the pixel unit 140 and supplies the corrected data signal to the data driver 120. [ The timing controller 110 outputs a data control signal DCS for controlling the operation timing of the data driver 120 and a scan control signal SCS for controlling the operation timing of the scan driver 130 do.

The data driver 120 is connected to the data lines D1 to Dm and supplies a data signal to the pixel unit 140 through the data lines D1 to Dm. The data driver 120 converts the digital data signal data supplied from the timing controller 110 into an analog data signal (or voltage). Specifically, the data driver 120 samples and latches the data signal (data) in response to the data control signal DCS of the timing controller 110, converts the data signal to a gamma reference voltage, and outputs the gamma reference voltage.

The scan driver 130 is connected to the scan lines S1 to Sn and supplies a scan signal to the pixel unit 140 through the scan lines S1 to Sn. In detail, the scan driver 130 outputs the scan signal while shifting the level of the gate voltage in response to the scan control signal SCS of the timing controller 110. In one embodiment, the scan driver 130 may include a plurality of stage circuits, and may sequentially supply the scan signals to the scan lines S1 to Sn.

The pixel unit 140 displays an image corresponding to the data signal supplied from the data driver 120 and the scan signal supplied from the scan driver 130. The pixel unit 140 includes a plurality of pixels Px connected to the scan lines S1 to Sn and the data lines D1 to Dm and arranged in a matrix. Specifically, the pixels Px are selected in units of horizontal lines corresponding to scan signals supplied to any one of the scan lines S1 to Sn. At this time, each of the pixels Px selected by the scanning signal receives a data signal from the data line (any one of D1 to Dm) connected thereto. Each of the pixels Px supplied with the data signal generates light of a predetermined luminance corresponding to the data signal.

2 is a block diagram schematically showing the signal transmission system between the timing controller and the data driver of FIG.

Referring to FIG. 2, the timing controller 110 and the data driver 120 constitute a signal transmission system for transmitting a data signal (data). In the present embodiment, the timing controller 110 and the data driver 120 transmit a clock signal and a data signal by a low voltage differential signaling (LVDS) transmission method for transmitting a high-speed signal do.

Specifically, the timing controller 110 is electrically connected to the data driver 120 through the first transmission line TL1 and the second transmission line TL2. The data driver 120 receives a clock signal and a data signal from the timing controller 110 through the first and second transmission lines TL1 and TL2. The timing controller 110 and the data driver 120 may transmit and receive various control signals and data through a separate feedback line FL. In FIG. 2, one data driver 120 is shown for convenience of explanation. However, in practice, a plurality of pairs of the first and second transmission lines TL1 and TL2 are connected to a plurality of data driver circuits .

In one embodiment, the timing controller 110 may include a transmitter TX, a differential swing level setter 111, a preamplifier setter 113, and a transmission controller 115, 120 may include a receiving end RX, a clock data restoration circuit 121, and a reception control unit 125. [

The transmitting terminal Tx of the timing controller 110 and the receiving terminal Rx of the data driver 120 are connected to an EPI (Embedded Clock Point Interface) for transmitting / receiving data in a differential swing level voltage form Respectively. A pair of output terminals of the transmission terminal Tx of the timing control unit 110 and a pair of input terminals of the reception terminal Rx of the data driver 120 are connected to the first and second transmission lines TL1 and TL2, And differential signals of different voltages are transmitted to the first and second transmission lines TL1 and TL2. The differential signal may include a positive differential signal and a negative differential signal.

The differential signal of the positive polarity and the differential signal of the negative polarity are signals having the same polarity and opposite polarity (or phase), and the receiving end Rx is a signal obtained from the difference between the positive differential signal and the negative differential signal Various control signals and image data with minimized noise can be calculated.

The timing controller 110 may check whether a lock or a lock fail for clock data recovery (CDR) of the data driver 120 is performed. The timing controller 110 may receive data on the lock or lock fail from the data driver 120 through the feedback line FL. When the lock fail occurs, the timing controller 110 can calculate a lock fail rate, which is a rate of occurrence of the lock fail per unit time. The timing controller 110 calculates the lock fail rate, A differential swing level, and a pre-emphasis value of the differential signal. Here, the unit time of the lock fail rate may be determined by counting the internal clock signal of the timing control unit 110 a predetermined number of times.

The differential swing level setting unit 111 may adjust the differential swing level of the differential signal output through the transmitting terminal Tx under the control of the transmission control unit 115. [ The differential swing level setting unit 111 sets the differential swing level register value under the control of the transmission control unit 115 and outputs a differential signal corresponding to the predetermined differential swing level register value to the transmitting terminal TX . The differential swing level register value is data matched to the entire voltage range of the variable swing level that is variable.

The preamplifier setting unit 113 may adjust the preamplification value output through the transmitting terminal Tx under the control of the transmission control unit 115. [ The preamplifier setting unit 113 sets the preamplifier register value under the control of the transmission control unit 115 and outputs a differential signal corresponding to the preset preamplifier register value to the transmitting terminal TX . The preamplifier register value is data matched to the total voltage range of the variable preamplification value.

The transmission control unit 115 may calculate the lock fail rate based on the data on the lock or lock fail provided from the data driver 120 and may set the differential swing level setting (111) and the preamplifier setting unit (113).

Specifically, the transmission control unit 115 can calculate the optimum differential swing level at which the lock fail rate becomes minimum while varying the differential swing level register value.

In one embodiment, the transmission control unit 115 calculates the lock fail rate corresponding to each of the variable swing level register values of all the variable lengths, and sets the value of any one of the differential swing level registers having the minimum lock fail rate as The optimum differential swing level can be determined.

The transmission control unit 115 may control the differential swing level setting unit 111 to set the differential swing level register value to the calculated optimum differential swing level.

In addition, the transmission controller 115 may calculate an optimum preamplification value that minimizes the lock fail rate while varying the preamplifier register value.

In one embodiment, the transmission control unit 115 calculates the lock fail rate corresponding to each of all the variable preamplifier register values, and sets the value of any one of the preamplifier registers having the minimum lock fail rate as The optimal preamplification value can be determined.

The transmission controller 115 may control the preamplifier setting unit 113 to set the preamplifier register value to the calculated optimum preamplitude value.

An end resistor (Zt) for impedance matching is provided at an end of the receiving end (Rx). The first and second transmission lines TL1 and TL2 are electrically connected by the terminating resistor Zt to constitute a closed circuit. The resistance value of the terminating resistor Zt may be adjusted by the receiving controller 125. [

The clock data restoration circuit 121 is a circuit for restoring clock data of a differential signal and can determine whether the lock or lock fails in order to restore stable clock data. For example, when the phase and the frequency of the differential signal are fixed, the clock data recovery circuit 121 outputs a high level lock signal (LOCK) indicating the output stable state to the timing controller 110 ). The lock signal may be provided through the feedback line FL.

When the high-level lock signal is input, the data driver 120 forms a data link with the timing controller 110. The timing controller 110 starts transmitting various control signals and image data to the data driver 120 in response to the high-level lock signal.

When the phase and frequency of the differential signal are unlocked, the clock data recovery circuit 121 inverts the lock signal to a low level and transmits the inverted lock signal to the timing controller 110 do. In this case, the timing controller 110 transmits a clock training pattern signal to the data driver 120 to resume clock training for the differential signal.

The reception control unit 125 may calculate the lock fail rate based on the data on the lock or lock fail provided from the clock data recovery circuit 121, (Zt) can be adjusted.

More specifically, the reception controller 125 may calculate the optimum resistance value that minimizes the lock fail rate while varying the resistance value of the resistor of the terminating resistor Zt.

In one embodiment, the reception controller 125 may calculate the lock fail rate corresponding to each of the variable resistor resistors, and may set any one of the resistor resistor values having the minimum lock fail rate as the optimum resistance value .

Then, the reception controller 125 sets the resistance register value to the calculated optimum resistance value, and the resistance value of the terminating resistor Zt is fixed to a value corresponding to the resistance register value.

Meanwhile, the reception controller 125 can exchange data on the lock fail rate with the transmission controller 115 via the feedback line FL. Specifically, the reception control unit 125 outputs one of the differential swing level register values having the minimum lock fail rate or the lock fail rate corresponding to each of the differential swing level register values through the feedback line (FL) To the transmission control unit 115. Also, the reception controller 125 may control the preamplifier register value of the preamplifier register, which is the minimum of the lock fail rate or the lock fail rate, corresponding to each of the preamplifier register values through the feedback line (FL) It is possible to feed back to the transmission control section 115.

3 is a flowchart illustrating a signal transmission method according to an embodiment of the present invention.

Referring to FIG. 3, a signal transmission method according to an embodiment of the present invention first checks whether a lock or a lock fails to recover the clock data (S10). The timing controller 110 may check whether a lock or a lock fails to restore clock data of the data driver 120. [ The timing controller 110 may receive data on the lock or lock fail from the data driver 120 through the feedback line FL.

If it is determined that the lock is performed in step S10, the signal transmission condition is not adjusted and data transmission is started. The data driver 120 forms a data link with the timing controller 110. The timing controller 110 starts transmitting various control signals and image data to the data driver 120 in response to the high-level lock signal.

If it is determined in step S10 that the lock fails, the optimum resistance value that minimizes the lock fail rate is calculated while varying the resistance register value of the terminating resistor Zt (S11, S12). The reception control unit 125 may calculate the lock fail rate based on the data on the lock or lock fail provided from the clock data recovery circuit 121, (Zt) can be adjusted.

In one embodiment, the reception controller 125 may calculate the lock fail rate corresponding to each of the variable resistor resistors, and may set any one of the resistor resistor values having the minimum lock fail rate as the optimum resistance value .

Then, the resistance register value is set to the calculated optimum resistance value (S13). For example, if the lock fail rate in the entire range of the resistance register value has a value of 20 to 30, any one of the resistance register values corresponding to the lock fail rate 20 is selected as the optimum resistance value. Then, the resistance value of the terminating resistor (Zt) is fixed to a value corresponding to the resistance value of the resistor.

Next, the optimal differential swing level at which the lock fail rate is minimized while varying the differential swing level register value is calculated (S14, S15). The transmission control unit 115 can calculate the optimum differential swing level at which the lock fail rate becomes minimum while varying the differential swing level register value.

In one embodiment, the transmission control unit 115 calculates the lock fail rate corresponding to each of the variable swing level register values of all the variable lengths, and sets the value of any one of the differential swing level registers having the minimum lock fail rate as The optimum differential swing level can be determined.

At this time, the reception controller 125 outputs one of the differential swing level register values having the minimum lock fail rate or the lock fail rate corresponding to each of the differential swing level register values through the feedback line (FL) To the transmission control section 115.

Then, the differential swing level register value is set to the calculated optimum swing level (S16). For example, if the lock fail rate is 10 to 20 in the entire range of the differential swing level register value, any one of the differential swing level register values corresponding to the lock fail rate 10 may be selected as the optimum differential swing level do. Then, the differential swing level register value of the differential swing level setting unit 111 is fixed to the selected optimum swing level.

Next, the optimum preamplification value at which the lock fail rate is minimized while varying the value of the preamplifier register is calculated (S17, S18). The transmission controller 115 may calculate an optimal preamplification value that minimizes the lock fail rate while varying the preamplifier register value.

In one embodiment, the transmission control unit 115 calculates the lock fail rate corresponding to each of all the variable preamplifier register values, and sets the value of any one of the preamplifier registers having the minimum lock fail rate as The optimal preamplification value can be determined.

At this time, the reception controller 125 outputs any one of the preamplifier register values having the minimum lock fail rate or the lock fail rate corresponding to each of the preamplifier register values through the feedback line (FL) It is possible to feed back to the transmission control section 115.

Then, the preamplifier register value is set to the calculated optimum preamplitude value (S19). For example, if the lock fail rate has a value in the range of 0 to 10 in the entire range of the preamplifier register value, any one of the preamplifier register values corresponding to the lock fail rate 0 may be the optimal preamplification value Is selected. The preamplifier register value of the preamplifier setting unit 113 is fixed to the selected optimum preamplitude value.

All of the above steps may be performed in the initial setup mode or the standby mode. The initial setup mode is a mode in which the differential swing level set value of the differential swing level setting unit 111, the preamplifier register value of the preamplifier setting unit 113, and the resistance register value of the terminating resistor Zt (default) value. The standby mode is a state in which the power applied to the pixel unit 140 of the display device is off.

According to the present invention, it is possible to secure stability in high-speed data transmission by setting optimum signal transmission conditions so that the lock fail occurrence rate is minimized.

4 is a schematic view showing a display device according to another embodiment of the present invention. Hereinafter, a description of the substantially same components as those of the above-described embodiment will be omitted.

Referring to FIG. 4, the display device according to another exemplary embodiment of the present invention includes a timing controller 110 'and a data driver 120', and the timing controller 110 'and the data driver 120' And constitutes a signal transmission system for transmitting the data signal (data).

The timing controller 110 'may include a transmitter TX, a differential swing level setter 111, a preamplifier setter 113, and a transmission controller 115'. The data driver 120 ' The receiver RX, the clock data restoration circuit 121, the reception controller 125 ', and the memory 127, as shown in FIG.

The transmission control unit 115 'varies the differential swing level register value of the differential signal and changes the value of the differential swing level register to a value of a normal range of the differential swing level at which the lock for restoring the clock data is activated, The center range value of the differential swing level is calculated.

The transmission control unit 115 'may set the differential swing level register value of the differential signal within the calculated center range value of the differential swing level. In order to prevent abrupt change of the display image, the step of setting the differential swing level register value may be performed in the blank period.

When the differential swing level monitored by the reception controller 125 'is out of the center range value of the previously stored differential swing level, the transmission control unit 115' varies the differential swing level register value, And the adjusted differential swing level is calculated so that the differential swing level is within the center range value of the differential swing level.

The transmission control unit 115 'may control the differential swing level setting unit 111 to set the differential swing level register value to the calculated adjusted differential swing level.

Meanwhile, the reception controller 125 'may monitor the differential swing level of the differential signal transmitted from the timing controller 110', and may feedback the monitoring result to the timing controller 110 '. The step of monitoring the differential swing level of the differential signal may be performed on a frame-by-frame basis. Also, the reception controller 125 'may store at least one of the normal range value and the center range value of the differential swing level in the memory 127.

The transmission control unit 115 'changes the preamplifier register value of the differential signal and changes the value of the normal range value of the jitter parameter for the data packet of the differential signal for which the lock for restoring the clock data is activated And a center range value of the jitter parameter which is a predetermined ratio with respect to a normal range value of the jitter parameter.

Here, the jitter parameter may be a ratio of a first period included in the data period to a data period corresponding to one data packet, or a ratio of a second period included in the data period to the data period. The data period includes the first period and the second period that are separated by a center. The length of the data period, the first period, and the second period may be calculated by counting a second clock signal having a frequency higher than the frequency of the first clock signal included in the differential signal. The data period may be a 1H time.

The transmission controller 115 'may set the preamplification register value of the differential signal to correspond to the calculated center range value of the jitter parameter. In order to prevent abrupt change of the display image, the step of setting the preamplification register value may be performed in the blank period.

When the jitter parameter monitored by the reception controller 125 'is out of the center range value of the jitter parameter previously stored, the transmission controller 115' varies the preamplifier register value, The adjusted preamplification value can be calculated so that the parameter is within the center range value of the jitter parameter.

The transmission control unit 115 'may control the preamplifier setting unit 113 to set the preamplification register value to the calculated adjusted preamplification value.

Meanwhile, the reception controller 125 'may monitor the jitter parameter calculated from the differential signal transmitted from the timing controller 110', and may feedback the monitoring result to the timing controller 110 '. The step of monitoring the jitter parameter may be performed on a frame-by-frame basis. Also, the reception controller 125 'may store at least one of the normal range value and the center range value of the jitter parameter in the memory 127. [

5 is a flowchart illustrating a signal transmission method according to another embodiment of the present invention.

Referring to FIG. 5, the signal transmission method according to another embodiment of the present invention can be divided into an initial setup mode and a normal mode. The initial setup mode is a mode in which the differential swing level set value of the differential swing level setting unit 111, the preamplifier register value of the preamplifier setting unit 113, and the resistance register value of the terminating resistor Zt (default) value. The normal mode is a general drive mode in which the display device is driven based on the default value. The initial setup mode includes steps S21 to S28, and the normal mode includes steps S31 to S45.

First, the transmission control unit 115 'varies the differential swing level register value of the differential signal, changes the value of the normal range value of the differential swing level at which the lock for restoring the clock data is activated and the normal range value of the differential swing level The central range value of the differential swing level at a predetermined ratio is calculated (S21, S22).

At this time, the reception controller 125 'may store at least one of the normal range value and the center range value of the differential swing level in the memory 127 (S23).

The transmission control unit 115 'may set the differential swing level register value of the differential signal within the calculated center range value of the calculated differential swing level (S24). In order to prevent abrupt change of the display image, the step of setting the differential swing level register value may be performed in the blank period.

Next, the transmission control unit 115 'varies the preamplifier register value of the differential signal, and determines a normal range of a jitter parameter for the data packet of the differential signal, in which the lock for recovering the clock data is activated, And a center range value of the jitter parameter which is a predetermined ratio with respect to the normal range value of the jitter parameter can be calculated (S25, S26).

At this time, the reception controller 125 'may store at least one of the normal range value and the center range value of the jitter parameter in the memory 127 (S27).

The transmission controller 115 'may set the preamplification register value of the differential signal to correspond to the calculated center range value of the jitter parameter. In order to prevent abrupt change of the display image, the step of setting the preamplification register value may be performed in the blank period (S28).

Next, the reception controller 125 'monitors the differential swing level of the differential signal transmitted from the timing controller 110', and may feedback the monitoring result to the timing controller 110 '(S31 ). The step of monitoring the differential swing level of the differential signal may be performed on a frame-by-frame basis.

When the differential swing level monitored by the reception controller 125 'is out of the center range value of the previously stored differential swing level, the transmission control unit 115' varies the differential swing level register value, The adjusted differential swing level is calculated so that the differential swing level is within the center range value of the differential swing level (S32, S33, S34).

The transmission control unit 115 'may control the differential swing level setting unit 111 to set the differential swing level register value to the calculated adjusted differential swing level (S35).

Next, the transmission control unit 115 'may set the preamplification register value of the differential signal to correspond to the calculated center range value of the jitter parameter (S41). In order to prevent abrupt change of the display image, the step of setting the preamplification register value may be performed in the blank period.

When the jitter parameter monitored by the reception controller 125 'is out of the center range value of the jitter parameter previously stored, the transmission controller 115' varies the preamplifier register value, The adjusted preamplification value can be calculated so that the parameter is within the center range value of the jitter parameter (S42, S43, S44).

The transmission controller 115 'may control the preamplifier setting unit 113 to set the preamplifier register value to the calculated adjusted preamplitude value at step S45.

6 is a diagram for explaining the normal range value and the center range value of the differential swing level.

Referring to FIG. 6, the normal range value VNR of the differential swing level includes a high value (+ Vn) and a low value (-Vn) of the differential swing level at which the lock for restoring the clock data is activated. That is, if the differential swing level deviates from the normal range value VNR, the lock fail occurs.

The center range value VSR of the differential swing level includes a high value (+ Vs) and a low value (-Vs) which are a predetermined ratio to the normal range value of the differential swing level. That is, if the differential swing level is within the center range value VSR, the probability of occurrence of the lock failure is greatly reduced. If the differential swing level is outside the center range value VSR, the probability of occurrence of the lock failure increases . The center range value (VSR) may be determined to be within a certain range centered on the center value (0V) of the normal range value (VNR).

For example, when at least one of the high value Vd2 or the low value Vd1 of the monitored differential swing level Vm is out of the center range value VSR, the reception control unit 125 ' To the timing control unit 110 '. The timing controller 110 'sets the differential swing level register value of the differential signal so that the differential swing level Vm moves within the center range value VSR.

7 is a diagram for explaining jitter parameters.

7, the jitter parameter is a ratio of a first period t1 included in the data period td to a data period td corresponding to one data packet, or a ratio of the data period td to the data period td, And the ratio of the second period t2 included in the period td. Here, the data period td includes the first period t1 and the second period t2, which are divided based on the center. The length of the data period td, the first period t1 and the second period t2 may be a second clock signal having a frequency higher than the frequency of the first clock signal CLK1 included in the differential signal CLK2. ≪ / RTI > The second clock signal CLK2 may be an internal clock signal of the timing controller 110. [ The data period td may be a 1H time.

For example, when the number of clocks of the second clock signal CLK2 corresponding to the data period td is 10, the number of clocks of the second clock signal CLK2 corresponding to the first period t1 is 5, If the number of clocks of the second clock signal CLK2 corresponding to the second period t2 is 5, the jitter parameter has a value of 0.5, which indicates that the transmitted signal is in a stable state, and whether the jitter parameter is abnormal It becomes a reference value for judgment.

According to the present invention, the signal transmission conditions are adjusted in advance before the lock fail, so that stability can be secured in high-speed data transmission.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications may be made without departing from the scope of the present invention.

110: timing control unit 120:
130: scan driver 140:
TX: Transmitter RX: Receiver
TL1: first transmission line TL2: second transmission line
FL: feedback line 111: differential swing level setting unit
113: preamplifier setting unit 115: transmission control unit
121: clock data restoration circuit 125:

Claims (20)

And a data driving unit having a timing control unit and a clock data recovery circuit for clock data recovery (CDR) of a differential signal transmitted from the timing control unit, the method comprising:
Checking whether there is a lock or a lock fail for restoring the clock data;
Calculating an optimal resistance value that minimizes a lock fail rate which is a rate of generation of the lock fail per unit time while varying a resistance register value of a terminating resistor of a receiving end of the data driver;
The data driver setting the resistance register value to the calculated optimum resistance value;
Calculating an optimal differential swing level at which the lock fail rate is minimized while varying the differential swing level register value of the differential signal;
The timing control unit setting the differential swing level register value to the calculated optimum differential swing level;
Calculating an optimum preamplification value that minimizes the lock fail rate while varying a pre-emphasis register value of the differential signal; And
And the timing controller sets the preamplifier register value to the calculated optimum preamplifier value. The method according to claim 1,
Wherein the step of calculating the optimum resistance value comprises:
Calculating the lock fail rate corresponding to each of the variable resistor resistances as a whole, and determining any one of the resistance register values having the minimum lock fail rate as the optimum resistance value. The method according to claim 1,
Wherein calculating the optimal differential swing level comprises:
Calculates the lock fail rate corresponding to each of the variable swing level register values as a whole and determines the one of the differential swing level register values having the minimum lock fail rate as the optimum differential swing level Signal transmission method. The method according to claim 1,
Wherein the data driver transmits either the lock fail rate corresponding to each of the differential swing level register values or one of the differential swing level register values having the minimum lock fail rate to the timing controller through the feedback line Signal transmission method. The method according to claim 1,
Wherein the step of calculating the optimal preamplitude value comprises:
Calculates the lock fail rate corresponding to each of all the variable preamplifier register values and determines the value of any one preamplifier register having the minimum lock fail rate as the optimum preamplifier value / RTI > The method according to claim 1,
Wherein the data driver transmits any one of the preamplifier register values having the minimum lock fail rate or the lock fail rate corresponding to each of the preamplifier register values to the timing controller through the feedback line Signal transmission method. The method according to claim 1,
Wherein all of the steps are performed in an initial setup mode or a standby mode. A signal transmission method of a display apparatus including a timing controller and a data driver having a clock data recovery circuit for recovering clock data of a differential signal transmitted from the timing controller,
Wherein the differential swing level register value of the differential signal is varied while a difference between a normal range value of the differential swing level at which the lock for restoring the clock data is activated and a normal range value of the differential swing level at a center of the differential swing level Calculating a range value;
Setting the differential swing level register value of the differential signal within the calculated center range value of the differential swing level;
The data driver may include: monitoring a differential swing level of the differential signal transmitted from the timing controller;
The differential swing level register value is varied while the monitored differential swing level deviates from the center range value of the previously stored differential swing level so that the monitored differential swing level is adjusted to be within the center range value of the differential swing level Calculating a differential swing level; And
And the timing control section includes setting the differential swing level register value to the calculated adjusted differential swing level. 9. The method of claim 8,
Wherein the step of monitoring the differential swing level of the differential signal is performed on a frame-by-frame basis. 9. The method of claim 8,
Wherein setting the differential swing level register value is performed in a blank period. 9. The method of claim 8,
And storing at least one of a normal range value and a center range value of the differential swing level in a memory. 9. The method of claim 8,
A normal range value of a jitter parameter related to a data packet of the differential signal in which a lock for restoring the clock data is activated while varying a preamplifier register value of the differential signal and a normal range value of a jitter parameter of the jitter parameter Calculating a center range value of the jitter parameter at a predetermined ratio; And
Wherein the timing controller further comprises setting a preamplifier register value of the differential signal to correspond to a calculated center range value of the jitter parameter. 13. The method of claim 12,
Wherein the data driver includes: monitoring the jitter parameter calculated from the differential signal transmitted from the timing controller;
Wherein the preamplifier value is changed when the monitored jitter parameter is out of the center range value of the jitter parameter, and the adjusted preamplitude value is adjusted so that the monitored jitter parameter is within the center range value of the jitter parameter, ; And
Wherein the timing controller further comprises setting the preamplifier register value to the adjusted preamplitude value. 14. The method of claim 13,
Wherein the jitter parameter is a ratio of a first period included in the data period to a data period corresponding to one data packet or a second period included in the data period with respect to the data period. 15. The method of claim 14,
Wherein the data period includes the first period and the second period that are separated by a center. 16. The method of claim 15,
Wherein the length of the data period, the first period, and the second period is calculated by counting a second clock signal having a frequency higher than a frequency of the first clock signal included in the differential signal. 17. The method of claim 16,
Wherein the data period is a 1H time. 14. The method of claim 13,
Wherein the step of monitoring the jitter parameter is performed on a frame-by-frame basis. 14. The method of claim 13,
Wherein setting the preamplifier register value is performed in a blank period. 13. The method of claim 12,
And storing at least one of a normal range value and a center range value of the jitter parameter in a memory.

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