KR20140055700A

KR20140055700A - Printed circuit board and manufacturing method thereof

Info

Publication number: KR20140055700A
Application number: KR1020120122909A
Authority: KR
Inventors: 고영관; 정혜원; 박용진; 김준성
Original assignee: 삼성전기주식회사
Priority date: 2012-11-01
Filing date: 2012-11-01
Publication date: 2014-05-09

Abstract

The present invention relates to a printed circuit board and a manufacturing method thereof.
A printed circuit board according to the present invention includes: a base layer constituting a base of a substrate; An insulating layer formed on the upper surface of the base layer and for forming a circuit and a via hole; A first seed layer formed on an upper surface of the insulating layer to smoothly form a laminate of a conductive material; A second seed layer formed over the upper surface of the first seed layer and the inner surface of the via hole formed in the insulating layer, for smoothly forming a stack of conductive materials; And a conductive layer formed on the upper surface of the second seed layer for conducting the circuit configuration and the upper layer.
According to the present invention, selective etching with the copper seed layer is performed by using a dissimilar metal different from copper (Cu) as the first seed layer, whereby the undercut at the bottom of the circuit can be minimized. Further, since the first seed layer is not formed in the via hole, it is possible to suppress the increase of the via conduction resistance and obtain a high adhesion force with the seed layer without forming the roughness of the surface of the insulating layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method of manufacturing the same, and more particularly, to a printed circuit board and a method of manufacturing the same, which can minimize the undercut at the lower end of the circuit and improve the adhesion to the insulating layer.

BACKGROUND ART [0002] In recent years, miniaturization of electronic devices has led to rapid progress in high integration of electronic devices. These trends also require various changes in printed circuit boards (PCBs). In other words, the line / space in the PCB has become finer, and the conventional semi-additive method can cover the line / space up to about 10 μm / 10 μm. In recent years, however, the line / space is required to be less than 10 탆, and the semi-permanent method has a certain limit with respect to this design value. 1, a copper (Cu) layer, which is a seed layer 113 formed on an insulating layer 112 of a PCB substrate, is etched in order to complete a circuit pattern in a PCB manufacturing process At this time, there is a problem that an undercut occurs at the lower end of the circuit pattern. Such undercuts may adversely affect the characteristics of the circuit or, if serious, cause problems such as disconnection, resulting in defective PCB products. Therefore, in the semi-permanent method, it is impossible to form a circuit of less than 10 mu m. In Fig. 1, reference numeral 111 denotes a metal pad, and 114 denotes a circuit layer.

Korean Patent Publication No. 10-2011-0038520 Japanese Patent Application Laid-Open No. 2009-049116

The present invention has been made in view of the above problems, and it is an object of the present invention to selectively etch a copper seed layer using copper (Cu) and another dissimilar metal as a first seed layer to minimize undercuts at the circuit bottom, And a method for manufacturing the printed circuit board.

According to an aspect of the present invention, there is provided a printed circuit board comprising:

A base layer constituting a base of the substrate;

An insulating layer formed on an upper surface of the base layer and for forming a circuit and a via hole;

A first seed layer formed on an upper surface of the insulating layer to smoothly form a laminate of a conductive material;

A second seed layer formed on an upper surface of the first seed layer and an inner surface of the via hole formed in the insulating layer, for smoothly forming a laminate of a conductive material; And

And a conductive layer formed on the upper surface of the second seed layer and electrically connected to the upper layer.

As the material of the insulating layer, a thermosetting resin or a thermoplastic resin may be used.

Also, the first seed layer may be composed of any one of Ti, Ni, Fe, and Zn, or may be composed of an alloy thereof.

In addition, the thickness of the first seed layer is preferably 0.05 to 0.5 mu m.

Also, the second seed layer may be made of a Cu material.

The thickness of the second seed layer is preferably 0.05 to 2 占 퐉.

According to another aspect of the present invention, there is provided a method of manufacturing a printed circuit board,

a) forming an insulating layer for forming a circuit and a via hole on an upper surface of the base layer;

b) forming a first seed layer on the upper surface of the insulating layer so that formation of a conductive material is smoothly formed;

c) forming a via hole for interlayer conducting across the first seed layer and the insulating layer;

d) forming a second seed layer on the upper surface of the first seed layer and the inner surface of the via hole formed in the insulating layer so that the formation of the conductive material is smoothly formed;

e) forming a plating resist on a top surface of the second seed layer in a predetermined pattern;

f) forming a copper plating layer as a conductive layer for conducting a circuit configuration and an upper layer over the via hole and a space between plating resists formed on the upper surface of the second seed layer;

g) selectively removing the plating resist and the second seed layer below the plating resist; And

and h) removing the first seed layer exposed by the removal of the second seed layer to complete the circuit.

In the step a), the insulating layer may be formed of a thermosetting resin or a thermoplastic resin.

In addition, in the step b), the first seed layer may be formed using any one of electroless plating, PVD (Physical Vapor Deposition), and CVD (Chemical Vapor Deposition).

Further, the via hole in the step c) may be formed by wet etching or dry etching.

Preferably, after the formation of the via hole, a step of removing a remnant of the insulating material remaining on the bottom surface of the via hole may be further included.

In addition, in the step d), the second seed layer may be formed using any one of electroless plating, PVD, and CVD.

Also, the second seed layer may be made of a Cu material.

The thickness of the second seed layer is preferably 0.05 to 2 占 퐉.

According to the present invention, selective etching with the copper seed layer is performed by using a dissimilar metal different from copper (Cu) as the first seed layer, whereby the undercut at the bottom of the circuit can be minimized.

Further, since the first seed layer is not formed in the via hole, it is possible to suppress the increase of the via conduction resistance and obtain a high adhesion force with the seed layer without forming the roughness of the surface of the insulating layer.

FIG. 1 is a view showing an undercut occurring at a lower end of a circuit pattern in etching a seed layer in a conventional process for manufacturing a printed circuit board. FIG.
2 is a view illustrating a structure of a printed circuit board according to an embodiment of the present invention.
3 is a flow chart illustrating the process of implementing a method of manufacturing a printed circuit board according to an embodiment of the present invention.
4A to 4H are views sequentially illustrating a process of manufacturing a printed circuit board according to a method of manufacturing a printed circuit board according to the present invention.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms and the inventor can properly define the concept of the term to describe its invention in the best way Should be construed in accordance with the principles and meanings and concepts consistent with the technical idea of the present invention.

Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise. Also, the terms " part, "" module, "and" device " Lt; / RTI >

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a view illustrating a structure of a printed circuit board according to an embodiment of the present invention.

2, the printed circuit board according to the present invention includes a base layer 410, an insulating layer 420, a first seed layer 430, a second seed layer 450, and a conductive layer 470 .

The base layer 410 forms the base of the printed circuit board. The base layer 410 may be a metal pad.

The insulating layer 420 is formed on the upper surface of the base layer 410 and is for forming a circuit and a via hole. Here, as the material of the insulating layer 420, a thermosetting resin or a thermoplastic resin may be used.

The first seed layer 430 is formed on the upper surface of the insulating layer 420 and the first seed layer 430 is formed to facilitate the formation of a conductive material such as copper. Here, the first seed layer 430 may be composed of any one of Ti, Ni, Fe, and Zn, or may be made of an alloy thereof. At this time, the thickness of the first seed layer 430 is preferably 0.05 to 0.5 mu m.

The second seed layer 450 is formed on the upper surface of the first seed layer 430 and the inner surface of the via hole 440 (see FIG. 4D) formed in the insulating layer 420, The layer 450 is also intended to facilitate the formation of a stack of conductive materials. Here, the second seed layer 450 may be made of a Cu material. The thickness of the second seed layer 450 is preferably 0.05 to 2 占 퐉.

The conductive layer 470 is formed on the upper surface of the second seed layer 450 and is for the circuit configuration and the connection with the upper layer. Such a conductive layer 470 may be formed by copper plating.

Hereinafter, a manufacturing process of the printed circuit board according to the present invention having the above-described structure will be described.

FIG. 3 is a flowchart illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention. FIGS. 4A to 4H illustrate a process of manufacturing a printed circuit board according to an embodiment of the present invention. Fig.

Referring to FIGS. 3 and 4A to 4H, an insulating layer 420 for forming circuits and via holes is formed on the upper surface of the base layer 410 according to a method of manufacturing a printed circuit board according to the present invention Step S301). Here, as the material of the insulating layer 420, a thermosetting resin or a thermoplastic resin may be used.

When the formation of the insulating layer 420 is completed, a first seed layer 430 is formed on the upper surface of the insulating layer 420 to smoothly form a lamination of a conductive material (e.g., copper) (Step S302 ). Here, the first seed layer 430 may be formed using any one of electroless plating, PVD (Physical Vapor Deposition), and CVD (Chemical Vapor Deposition).

The first seed layer 430 may be made of any one of Ti, Ni, Fe, and Zn, or may be made of an alloy thereof.

The thickness of the first seed layer 430 is preferably 0.05 to 0.5 占 퐉.

After the formation of the first seed layer 430 is completed, a via hole 440 for interlayer connection is formed over the first seed layer 430 and the insulating layer 420 (step S303). Here, such a via hole 440 may be formed by wet etching or dry etching. At this time, laser etching is preferably used as the dry etching.

After the formation of the via hole 440, the remaining portion of the insulating material remaining on the bottom surface of the via hole 440, that is, the base layer (metal pad) 410 exposed by the formation of the via hole 440 The method may further comprise the step of:

When the formation of the via hole 440 is completed as described above, stacking of the conductive material is smoothly performed over the upper surface of the first seed layer 430 and the inner surface of the via hole 440 formed in the insulating layer 420 (Step S304). The second seed layer 450 is formed on the second seed layer 450 to be formed. Here, the second seed layer 450 may be formed using any one of electroless plating, PVD, and CVD.

In addition, the second seed layer 450 may be made of a Cu material.

In addition, the thickness of the second seed layer 450 is preferably 0.05 to 2 탆.

After the formation of the second seed layer 450 is completed, a plating resist 460 is formed on the upper surface of the second seed layer 450 in a predetermined pattern (step S305). At this time, as the plating resist, a photoresist or a solder resist can be used. Photolithography may also be used to form the plating resist in a predetermined pattern.

After the formation of the plating resist 460, a space between the plating resist 460 formed on the upper surface of the second seed layer 450 and the space between the via holes 440, A copper plating layer 470 is formed as a conductive layer (step S306).

Then, the plating resist 460 and the second seed layer 450 under the plating resist 460 are selectively removed (step S307). Here, wet etching may be used for selective removal of the plating resist 460 and the second seed layer 450.

After the selective removal of the second seed layer 450 is completed in this manner, the first seed layer 430 exposed due to the removal of the second seed layer 450 is removed to finally complete the circuit S308).

As described above, the printed circuit board and the method of manufacturing the same according to the present invention can perform selective etching with the copper seed layer by using a dissimilar metal different from copper (Cu) as the first seed layer, It is possible to minimize the undercut at the bottom of the circuit that occurs during the etching of the seed layer.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but many variations and modifications may be made without departing from the spirit and scope of the invention. Be clear to the technician. Accordingly, the true scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of the same should be construed as being included in the scope of the present invention.

111 ... metal pad 112 ... insulating layer
113 ... Seed layer 114 ... Circuit layer
410 ... base layer 420 ... insulating layer
430 ... first seed layer 440 ... via hole
450 ... second seed layer 460 ... plating resist
Conductive layer (copper plating layer)

Claims

A base layer constituting a base of the substrate;
An insulating layer formed on an upper surface of the base layer and for forming a circuit and a via hole;
A first seed layer formed on an upper surface of the insulating layer to smoothly form a laminate of a conductive material;
A second seed layer formed on an upper surface of the first seed layer and an inner surface of the via hole formed in the insulating layer, for smoothly forming a laminate of a conductive material; And
And a conductive layer formed on an upper surface of the second seed layer, the conductive layer for conducting a circuit configuration and an upper layer.

The method according to claim 1,
Wherein the insulating layer is made of a thermosetting resin or a thermoplastic resin.

The method according to claim 1,
Wherein the first seed layer is composed of any one of Ti, Ni, Fe, and Zn, or an alloy thereof.

The method according to claim 1,
Wherein the thickness of the first seed layer is 0.05 to 0.5 mu m.

The method according to claim 1,
And the second seed layer is made of a Cu material.

The method according to claim 1,
And the thickness of the second seed layer is 0.05 to 2 占 퐉.

a) forming an insulating layer for forming a circuit and a via hole on an upper surface of the base layer;
b) forming a first seed layer on the upper surface of the insulating layer so that formation of a conductive material is smoothly formed;
c) forming a via hole for interlayer conducting across the first seed layer and the insulating layer;
d) forming a second seed layer on the upper surface of the first seed layer and the inner surface of the via hole formed in the insulating layer so that the formation of the conductive material is smoothly formed;
e) forming a plating resist on a top surface of the second seed layer in a predetermined pattern;
f) forming a copper plating layer as a conductive layer for conducting a circuit configuration and an upper layer over the via hole and a space between plating resists formed on the upper surface of the second seed layer;
g) selectively removing the plating resist and the second seed layer below the plating resist; And
h) removing the first seed layer exposed by the removal of the second seed layer to complete the circuit.

8. The method of claim 7,
Wherein the insulation layer is made of a thermosetting resin or a thermoplastic resin in the step a).

8. The method of claim 7,
Wherein the first seed layer is formed using any one of electroless plating, PVD (Physical Vapor Deposition), and CVD (Chemical Vapor Deposition) in the step b).

8. The method of claim 7,
Wherein the first seed layer is made of one of a metal selected from the group consisting of Ti, Ni, Fe, and Zn, or an alloy thereof.

8. The method of claim 7,
Wherein the thickness of the first seed layer is 0.05 to 0.5 占 퐉.

8. The method of claim 7,
Wherein the via hole in step (c) is formed by wet etching or dry etching.

8. The method of claim 7,
Further comprising the step of removing a remnant of insulating material remaining on the bottom surface of the via hole after the formation of the via hole in the step c).

8. The method of claim 7,
Wherein the second seed layer is formed using any one of electroless plating, PVD, and CVD in step d).

8. The method of claim 7,
Wherein the second seed layer is made of a Cu material.

8. The method of claim 7,
And the thickness of the second seed layer is 0.05 to 2 占 퐉.