KR20140045303A - Semiconductor substrate, semiconductor device, and method for producing semiconductor substrate - Google Patents

Abstract

GaN semiconductors are epitaxially grown on a silicon substrate having a plane orientation of (111). Since the difference between the lattice constant of GaN and the lattice constant of the silicon (111) plane is about 17%, a potential exceeding 10 ¹⁰ cm ⁻² is introduced into the grown GaN. By the potential, the leakage current of the transistor using GaN increases. In addition, the mobility of the transistor decreases. A semiconductor substrate having a nitride semiconductor layer epitaxially grown on a silicon substrate and a (150) surface of the silicon substrate is provided.

Description

A semiconductor substrate, a semiconductor device, and a manufacturing method of a semiconductor substrate {SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE}

The present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor substrate.

Since nitride compound semiconductors have a larger band gap energy and greater dielectric breakdown voltage than silicon semiconductors, they are expected as materials for high breakdown voltage devices. As a device using a nitride compound semiconductor, an AlGaN / GaN-HFET in which carbon is added to a nitride compound semiconductor to increase its breakdown voltage is known (see Patent Document 1, for example).

Related prior art documents include the following documents.

Japanese Patent Publication No. 2007-251144

J. E. Northrup, "Screw dislocations in GaN: The Ga-filled core model", Appl. Phys. Lett., American Institute of Physics, 2001, Vol. 78, Issue 16, p. 2288 Debdeep Jana, et. al., "Effect of scattering by strain fields surrounding edge dislocations on electron transport in two-dimensional electron gases", Appl. Phys. Lett., American Institute of Physics, 2002, Vol. 80, Issue 1, p. 64

A gallium nitride (GaN) -based semiconductor can be epitaxially grown on a silicon substrate in a plane orientation 111, but is grown because the difference between the lattice constant of GaN and the lattice constant of the silicon (111) plane is about 17%. The dislocation density of GaN exceeds 10 ¹⁰ cm ⁻² . As a potential introduced into GaN, there are a spiral potential and a blade potential. As the density of the spiral potential increases, the leakage current of the transistor using GaN increases (for example, see Non-Patent Document 1). If the leakage current increases, the withstand voltage of the transistor cannot be increased. In addition, when the density of the blade dislocations increases, the mobility of the transistor using GaN decreases (see Non-Patent Document 2, for example).

Even when carbon is added to the nitride compound semiconductor and the internal pressure is increased, the leakage current due to the spiral potential cannot be reduced. In addition, the decrease in mobility due to the blade dislocation cannot be eliminated.

Here, one aspect of this invention aims at providing the semiconductor substrate, the semiconductor device, and the manufacturing method of a semiconductor substrate which can solve the said subject. This object is achieved by a combination of the features described in the independent claims in the claims. The dependent claims also define further advantageous specific examples of the invention.

According to the first aspect of the present invention, there is provided a semiconductor substrate comprising a nitride semiconductor layer epitaxially grown on a silicon substrate and a (150) surface of the silicon substrate.

In a second aspect of the present invention, there is provided a semiconductor substrate manufacturing method comprising a nitride semiconductor layer forming step of epitaxially growing a nitride semiconductor layer made of a nitride semiconductor on a (150) surface of a silicon substrate.

In addition, the outline | summary of said invention does not enumerate all the required characteristics of this invention, and the subcombination of such a characteristic group can also become invention.

1 is a schematic diagram showing the relationship between the crystal axes of the Si (1k0) plane and the nitride semiconductor (0001) plane.
2 is a graph showing the relationship between the orientation of the crystal plane and lattice matching.
3 is a cross-sectional view of a semiconductor substrate having a silicon substrate, an AlN buffer layer, an intermediate buffer layer, a GaN buffer layer, an electron traveling layer, and an electron supply layer.
4 is a graph showing the relationship between the number of repetitions of the stacking of the intermediate buffer layer and the half width of X-ray diffraction (symmetry diffraction) of the nitride semiconductor layer.
Fig. 5 is a graph showing the relationship between the number of repetitions of lamination of the intermediate buffer layer and the half width of X-ray diffraction (asymmetric diffraction) of the nitride semiconductor layer.
6 is a cross-sectional view of a semiconductor substrate including a silicon substrate, an SiN layer, an AlN buffer layer, an intermediate buffer layer, a GaN buffer layer, an electron traveling layer, and an electron supply layer.
7 is a graph showing the relationship between nitriding time and half width.
8 is a schematic diagram showing the warpage of a semiconductor substrate.
9 is a sectional view of an HFET according to a first embodiment of the present invention.
10 is a sectional view of an HFET according to a second embodiment of the present invention.
11 is a sectional view of a Schottky barrier diode according to a third embodiment of the present invention.
12 is a graph showing the characteristics of a Schottky barrier diode.
13 is a sectional view of a MOSFET according to a fourth embodiment of the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, although one side of this invention is described through embodiment of this invention, the following embodiment does not limit the invention based on a claim, and all the combination of the characteristics demonstrated in embodiment are the solving means of this invention. It is not necessary to.

1 shows the relationship between the crystal axes of the Si (1k0) plane and the nitride semiconductor (0001) plane. k is an integer of 1 or more. The thick dotted line represents the crystal axis of the Si (1k0) plane. The thin solid line represents the crystal axis of the (0001) plane of the nitride semiconductor. When the nitride semiconductor (0001) surface is laminated on the Si (1k0) surface, the <k-10> axis of Si and the a axis of the nitride semiconductor match. In addition, the <001> axis of Si matches the m axis of the nitride semiconductor. The nitride semiconductor may be, for example, GaN, AlN or AlGaN.

The difference between the gap between the Si (001) planes and the m plane of the nitride semiconductor is 1.7%. The gap between the Si (k-10) plane and the a plane of the nitride semiconductor is generally large. However, when the (1k0) surface of Si and the nitride semiconductor (0001) surface are matched, matching at a long period is allowed. This is because the Si (1k0) plane has symmetry twice.

2 shows the result of calculating how much the distance between lattice matches when the Si (1k0) plane and the GaN (0001) plane are matched. As a comparison, the case where the Si (111) plane and the GaN (0001) plane are matched is also shown. In FIG. 2, the horizontal axis represents the plane orientation of Si. The black circle | round | yen of FIG. 2 shows the value when the difference of the space | interval of the a surface of GaN and the space | interval of the Si (k-10) surface becomes minimum corresponding to the left axis | shaft. The white circle represents the number of cycles of Si when the spacing between the a side of GaN and the spacing between the Si (k-10) surfaces becomes the minimum, corresponding to the right axis.

As shown in FIG. 2, the gap between the a plane of GaN and the Si (k− 10) When the surfaces are matched, it can be seen that the lattice constant difference becomes small in a long period. In addition, when Si (1k0) planes other than k = 1-6 are used, the matching period becomes too large (12 or more), and good GaN crystals cannot grow.

As shown in FIG. 2, when the GaN (0001) plane is formed on the Si (150) plane among the Si (1k0) planes, the gap between the a plane of the GaN plane and the Si (5-10) plane in 6 cycles. Is the minimum. The difference in the lattice spacing at that time is 0.19%. Since the difference in lattice spacing is small, the epitaxial growth of the GaN (0001) plane on the Si (150) plane results in a spiral dislocation and a blade dislocation (collectively referred to as "potential"). Less GaN layer is formed. Since the epitaxially grown GaN has a crystal structure, the dislocation becomes small as the difference in the distance between the lattice is small.

Similar results can be obtained for AlN and AlGaN. That is, when the AlN (0001) surface or the AlGaN (0001) surface is epitaxially grown on the Si (150) surface, an AlN layer or AlGaN layer having a small dislocation is formed.

3 is a schematic cross-sectional view of the semiconductor substrate 100. The semiconductor substrate 100 includes a silicon substrate 102, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116.

The AlN buffer layer 106 is epitaxially grown on the (150) surface of the silicon substrate 102. The intermediate buffer layer 108 is epitaxially grown on the AlN buffer layer 106. The intermediate buffer layer 108 may be epitaxially grown by alternately stacking a layer made of GaN and a layer made of AlN from the silicon substrate 102 side.

The GaN buffer layer 110 is epitaxially grown on the intermediate buffer layer 108. The GaN buffer layer 110 is made of GaN. The electron traveling layer 112 is epitaxially grown on the GaN buffer layer 110. The electron traveling layer 112 is made of GaN. The electron supply layer 116 is epitaxially grown on the electron traveling layer 112. The electron supply layer 116 is made of AlGaN.

Since the nitride semiconductor layer formed on the semiconductor substrate 100 is epitaxially grown, it has a crystal structure. In FIG. 3, the nitride semiconductor layer refers to an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116. As shown in Fig. 2, since the nitride semiconductor layer has good lattice matching with the Si (150) plane, the dislocation density of the nitride semiconductor layer is low.

The silicon substrate 102 may be a silicon substrate having a thickness of 1 mm, grown by the CZ (Czochralski) method. The silicon substrate grown by the CZ method has a higher residual oxygen concentration than the silicon substrate grown by the FZ method. In addition, with this, mechanical properties differ. In the silicon substrate 102 grown by the CZ method, cracks are less likely to enter the nitride semiconductor layer when the nitride semiconductor layer is formed than the silicon substrate 102 grown by the FZ method. For example, when the total thickness of the GaN buffer layer 110 and the electron traveling layer 112 is formed over 500 nm on the silicon substrate 102 grown by the FZ method, cracks occur in the nitride semiconductor layer. In some cases, the total thickness is preferably 500 nm or less.

The surface orientation of the silicon substrate 102 may shift from the (150) surface to a predetermined deviation or less. This is because if the amount of deviation is small, the dislocation density of the nitride semiconductor formed on the silicon substrate 102 becomes low. The amount of deviation may be an error that is usually included when cutting the substrate from the silicon ingot. For example, it is ± 2 degrees or less.

The AlN buffer layer 106 may be formed of AlN having a thickness of 40 nm. AlN has a low dislocation density because of good lattice matching with the Si (150) plane. The AlN buffer layer 106 is provided with the silicon substrate 102 in the MOCVD apparatus, and then trimethylluminium (TMAl) and NH ₃ are respectively supplied to the chamber of the MOCVD apparatus at a flow rate of 175 μmol / min and 35 L / min. You may introduce and epitaxially grow. Growth temperature is 1000 degreeC, for example.

The intermediate buffer layer 108 may be formed by repeatedly laminating a layer made of GaN and a layer made of AlN four to 12 times from the silicon substrate 102 side. Since AlN and GaN have good lattice matching with the Si (150) plane, the dislocation density is low. The intermediate buffer layer 108 can suppress cracks in the epitaxial film and control the amount of warpage of the semiconductor substrate 100.

The layer made of GaN of the intermediate buffer layer 108 may be 180 nm in thickness. The layer made of AlN of the intermediate buffer layer 108 may have a thickness of 20 nm. In FIG. 3, the thickness of the layer made of GaN is thicker than the thickness of the layer made of AlN of the AlN buffer layer 106 and the intermediate buffer layer 108. Therefore, the lattice matching of silicon and the layer made of GaN of the intermediate buffer layer 108 has a greater influence on the dislocation density than the lattice matching of silicon and the layer made of AlN of the AlN buffer layer 106 and the intermediate buffer layer 108. Since the lattice match between the GaN (0001) plane and the Si (150) plane is good, the intermediate buffer layer 108 has a low dislocation density.

The GaN layer of the intermediate buffer layer 108 may be epitaxially grown by introducing TMGa and NH ₃ at a flow rate of 58 μmol / min and 12 L / min, respectively. The layer made of AlN of the intermediate buffer layer 108 may be epitaxially grown by introducing TMAl and NH ₃ at a flow rate of 195 μmol / min and 12 L / min, respectively.

The GaN buffer layer 110 may be formed of GaN having a thickness of 600 nm. GaN has low dislocation density because of good lattice matching with the Si (150) plane. The GaN buffer layer 110 may introduce TMGa and NH ₃ at a flow rate of 58 μmol / min and 12 L / min, respectively, and epitaxially grow at a growth temperature of 1050 ° C. and a pressure of 50 Torr.

The electron traveling layer 112 may be formed of GaN having a thickness of 100 nm. GaN has low dislocation density because of good lattice matching with the Si (150) plane. The electron running layer 112 may introduce TMGa and NH ₃ at a flow rate of 19 μmol / min and 12 L / min, respectively, and epitaxially grow at a growth temperature of 1050 ° C. and a pressure of 200 Torr.

The electron supply layer 116 may be formed of AlGaN having a thickness of 30 nm. AlGaN has a low dislocation density because of good lattice matching with the Si (150) plane. The electron supply layer 116 may introduce TMAl, TMGa, and NH ₃ at a flow rate of 100 μmol / min, 19 μmol / min, and 12 L / min, respectively, and may be epitaxially grown at a growth temperature of 1050 ° C. . AlGaN of the electron supply layer 116 was evaluated by X-ray diffraction, and the composition ratio of Al was 0.22.

The semiconductor substrate 100 may be a wafer substrate. A silicon wafer may be used as the silicon substrate 102 and may be a wafer-shaped semiconductor substrate 100. In addition, the semiconductor substrate 100 may be a chip-shaped substrate. A silicon chip may be used as the silicon substrate 102 to form a chip-shaped semiconductor substrate 100.

4 shows the relationship between the number of repetitions of stacking of the intermediate buffer layer 108 and the full width at half maximum (FWHM) of X-ray diffraction of the nitride semiconductor layer. The triangle represents the half width of the nitride semiconductor layer of the semiconductor substrate 100 shown in FIG. 3. That is, the half width of the X-ray diffraction of the nitride semiconductor layer epitaxially grown on the (150) surface of the silicon substrate 102. As for the graph of FIG. 4, a nitride semiconductor layer means what laminated | stacked the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron traveling layer 112, and the electron supply layer 116. FIG. The horizontal axis is the number of times the lamination of the layer made of GaN and the layer made of AlN of the intermediate buffer layer 108 is repeated (referred to as "the number of repetitions"). The vertical axis is the half width of the peak (half width of the symmetrical diffraction (0002)) with the (0002) plane as the diffraction plane.

In FIG. 4, the half width of the X-ray diffraction of the nitride semiconductor layer formed on the (110) surface of the silicon substrate 102 is shown by a rectangle. The half width of the X-ray diffraction of the nitride semiconductor layer formed on the Si (111) surface of the silicon substrate 102 is indicated by circles.

The nitride semiconductor layer epitaxially grown on the Si (150) plane has a smaller half width of the symmetrical diffraction (0002) than the nitride semiconductor layer epitaxially grown on the Si (111) plane or the Si (110) plane. Also, increasing the number of repetitions of the intermediate buffer layer 108 reduces the half width of the symmetrical diffraction (0002).

The half width of the symmetrical diffraction (0002) is correlated with the spiral dislocation density. The spiral dislocation density correlates with the leakage current. Therefore, the nitride semiconductor layer epitaxially grown on the Si (150) surface has a smaller spiral dislocation density and a smaller leakage current than the nitride semiconductor layer epitaxially grown on the Si (111) surface or Si (110) surface. Can be formed. In addition, when the number of repetitions of the intermediate buffer layer 108 is increased, the spiral dislocation density becomes small, and a semiconductor device with a small leakage current can be formed.

When the number of repetitions of stacking of the intermediate buffer layer 108 is 12, the half width of the symmetrical diffraction (0002) of the nitride semiconductor layer formed on the Si (150) surface is reduced to 500 seconds. When the number of repetitions is eight, it is 700 seconds, and when it is four times, it is 740 seconds. When the nitride semiconductor layer is epitaxially grown on the (150) surface of the silicon substrate 102, the half width of the symmetrical diffraction (0002) is reduced by 20% or more as compared to the silicon 111 surface.

5 shows the relationship between the number of repetitions of the stacking of the intermediate buffer layer 108 and the full width at half maximum (FWHM) of X-ray diffraction of the nitride semiconductor layer. The triangle shows the half width of the nitride semiconductor layer of the semiconductor substrate 100. The horizontal axis is the number of times the lamination of the layer made of GaN and the layer made of AlN of the intermediate buffer layer 108 is repeated. The vertical axis is the half width of the peak (half width of the asymmetrical diffraction (30-32)) having the (30-32) plane as the diffraction plane. The half width of the X-ray diffraction of the nitride semiconductor layer formed on the (110) plane of the silicon substrate 102 is indicated by a rectangle. The half width of the X-ray diffraction of the nitride semiconductor layer formed on the Si (111) surface of the silicon substrate 102 is indicated by circles.

The nitride semiconductor layer epitaxially grown on the Si (150) plane has a smaller half width of the asymmetric diffraction (30-32) than the nitride semiconductor layer epitaxially grown on the Si (111) plane or the Si (110) plane. In addition, when the number of repetitions of the stacking of the intermediate buffer layer 108 is increased, the half width of the asymmetric diffraction 30-32 is reduced.

The half width of the asymmetric diffraction (30-32) is correlated with the blade dislocation density. The blade dislocation density correlates with mobility. Therefore, the nitride semiconductor layer epitaxially grown on the Si (150) plane has a smaller blade dislocation density and a higher mobility than the nitride semiconductor layer epitaxially grown on the Si (111) plane or the Si (110) plane. A semiconductor device can be formed. In addition, when the number of repetitions of the intermediate buffer layer 108 is increased, the blade dislocation density becomes small, and a semiconductor device with high mobility can be formed.

When the number of repetitions of stacking of the intermediate buffer layer 108 is 12, the half width of the asymmetric diffraction 30-32 of the nitride semiconductor layer formed on the Si (150) surface is reduced to 2550 seconds. When the number of repetitions is eight, it is 3300 seconds, and when it is four times, it is 3400 seconds. When the nitride semiconductor layer is epitaxially grown on the (150) surface of the silicon substrate 102, the half width of the asymmetric diffraction (30-32) is reduced by 20% or more as compared to the (111) surface of the silicon.

6 is a schematic cross-sectional view of the semiconductor substrate 130. In FIG. 6, the elements denoted by the same reference numerals as those in FIG. 3 may have the same functions and configurations as those described in FIG. 3. The semiconductor substrate 130 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116. It is provided. Except having the SiN layer 104, it has the same structure as the semiconductor substrate 100 of FIG.

SiN layer 104 is formed on silicon substrate 102. Since N atoms exist on the surface, epitaxial growth of the nitride semiconductor is facilitated. The SiN layer 104 preferably has a thickness of two atomic layers or less. The SiN layer 104 may have a thickness of one atomic layer or less. The SiN layer 104 thinner than one atomic layer means that the entire surface of the silicon substrate 102 is not covered by the SiN layer 104 for one atomic layer.

The SiN layer 104 may be formed by nitriding the surface of the (150) surface of the silicon substrate 102. For example, after the silicon substrate 102 is installed in the MOCVD apparatus, NH ₃ is introduced into the chamber of the MOCVD apparatus at a flow rate of 35 L / min, and the SiN layer 104 is formed. The SiN layer 104 may be formed by the CVD method.

FIG. 7 shows the half width of the X-ray diffraction of the nitride semiconductor layer of the semiconductor substrate 130 shown in FIG. 6. In the graph of FIG. 7, the nitride semiconductor layer refers to a laminate of an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116. The number of repetitions of the stacking of the intermediate buffer layer 108 is eight times. The abscissa indicates the time when the NH ₃ is nitrided by flowing the MOCVD apparatus provided with the silicon substrate 102. The left vertical axis is the half width of the peak (half width of the symmetrical diffraction (0002)) with the (0002) plane as the diffraction plane. The black circle corresponds to the longitudinal axis on the left. The vertical axis on the right is the half width of the peak (half width of the asymmetrical diffraction (30-32)) which makes the (30-32) plane the diffraction surface. White squares correspond to the longitudinal axis on the right.

At 0.25 minutes of the abscissa, the half width of symmetrical diffraction (0002) and half width of asymmetrical diffraction (30-32) are minimum. 0.25 minutes of the abscissa corresponds to the nitride of the silicon substrate 102 by NH ₃ for 0.25 minutes. At this time, the thickness of the SiN layer 104 is the thickness of 1 atomic layer-2 atomic layers. Even if the thickness of the SiN layer 104 is thinner than one atomic layer to two atomic layers, the half width is smaller than when the SiN layer 104 is not formed. Therefore, by forming the SiN layer 104 on the surface of the Si (150) surface, the semiconductor substrate 130 in which the semiconductor device with small leakage current is formed can be obtained. In addition, by forming the SiN layer 104 on the surface of the Si (150) surface, the semiconductor substrate 130 in which the semiconductor device with high mobility is formed can be obtained.

When the value of the half width of FIG. 7 is compared with the half width of the nitride semiconductor layer formed on the Si (111) plane of FIGS. 4 and 5, the SiN layer 104 is formed to have a thickness between one atomic layer and two atomic layers. The half width narrows by more than 30%. If the nitriding time exceeds 1.5 minutes, the effect of reducing the half width is small. In the example shown in FIG. 7, the half width of the symmetrical diffraction (0002) becomes large, so that the semiconductor substrate on which the spiral dislocation density increases and a semiconductor device with a small leakage current cannot be obtained.

8 illustrates a state in which warpage of the semiconductor substrate 130 is measured. The semiconductor substrate 130 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116. It is provided. The semiconductor substrate 130 has the structure shown in FIG. The amount of warpage h is the height of the end portion of the semiconductor substrate 130 from the horizontal plane including the center portion of the substrate. The radius of curvature r is the radius of the circle passing through the bottom of the substrate.

The nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102. The silicon substrate 102 may be a substrate having a diameter of 4 inches and a thickness of 1 mm, grown by the CZ method. The SiN layer 104 may be formed at 1000 ° C by introducing NH ₃ at a flow rate of 35 L / min into the MOCVD apparatus provided with the silicon substrate 102. The AlN buffer layer 106 may be formed of AlN having a thickness of 40 nm.

The intermediate buffer layer 108 may be formed by alternately stacking a layer made of GaN and a layer made of AlN six times from the silicon substrate 102 side. The thickness from the layer made of GaN formed on the AlN buffer layer 106 to the layer made of AlN formed under the GaN buffer layer 110 may be as follows in order from the bottom. 290 nm (GaN), 50 nm (AlN), 330 nm (GaN), 50 nm (AlN), 390 nm (GaN), 50 nm (AlN), 470 nm (GaN), 50 nm (AlN), 580 nm (GaN), 50 nm (AlN), 740 nm (GaN), 50 nm (AlN).

The thickness of the layer made of GaN included in the intermediate buffer layer 108 may be thickened from the side closer to the silicon substrate 102 toward the far side. Thereby, the suppression effect of a crack and the suppression effect of a curvature amount increase, and an epitaxial film can be laminated more thickly.

The GaN buffer layer 110 may be formed of GaN having a thickness of 100 nm. The GaN buffer layer 110 may be formed like the semiconductor substrate 100 of FIG. 3. The electron traveling layer 112 may be made of GaN having a thickness of 100 nm. The electron supply layer 116 may be formed of AlGaN having a thickness of 30 nm. As a result of evaluation by X-ray diffraction, the composition ratio of Al was 0.23. The AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron traveling layer 112, and the electron supply layer 116 may be formed like the semiconductor substrate 100 of FIG. 3.

Table 1 shows the amount of warpage h and the radius of curvature r of the semiconductor substrate 130. As a comparative example, the curvature amount h and curvature radius r of the semiconductor substrate 130 in which the nitride semiconductor layer was formed on the (111) surface of silicon were shown. The nitride semiconductor layer formed on the (111) surface of silicon is the same as the nitride semiconductor layer formed on the (150) surface of the silicon substrate 102. In the semiconductor substrate 130, the nitride semiconductor layer is composed of an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116.

Radius of curvature r (m) Warp amount h (㎛) Comparative Example 15.8 19.7 Semiconductor substrate 130 65.7 4.8

The semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102 has a warpage amount h than the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (111) surface of the silicon substrate 102. Is small and the radius of curvature is large. Therefore, the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102 has a lower warpage than the semiconductor substrate 130 in which the nitride semiconductor layer is formed on the (111) surface of silicon. have.

The semiconductor substrate 130 in which the nitride semiconductor layer was formed on the (150) surface of the silicon substrate 102 had a curvature amount of 15 m or less and a radius of curvature of 20 m or more. It is preferable that the warpage is reduced because the distortion of the crystal is connected to a small one. As a result, when the film formation, etching, or the like is performed on the semiconductor substrate 130, the substrate is uniformly processed.

9 is a schematic cross-sectional view of the HFET 140 according to the first embodiment of the present invention. In FIG. 9, elements denoted by the same reference numerals as those in FIG. 6 may have the same functions and configurations as those described in FIG. 6. The HFET 140 includes the silicon substrate 102, the SiN layer 104, the AlN buffer layer 106, the intermediate buffer layer 108, the GaN buffer layer 110, the electron traveling layer 112, and the alloy scattering suppression layer 114. And an electron supply layer 116, a source electrode 118, a drain electrode 120, and a gate electrode 122.

The silicon substrate 102 is a substrate made of silicon in the plane orientation 150. Except having the alloy scattering suppression layer 114, the source electrode 118, the drain electrode 120 and the gate electrode 122 has the same configuration as the semiconductor substrate 130 of FIG.

The alloy scattering suppression layer 114 is epitaxially grown on the electron traveling layer 112. The electron supply layer 116 is epitaxially grown on the alloy scattering suppression layer 114. By forming the alloy scattering suppression layer 114 between the electron traveling layer 112 and the electron supply layer 116, the alloy scattering of the two-dimensional electron gas is suppressed and the mobility in the HFET 140 is improved. .

The electron running layer 112 may be formed of GaN. The alloy scattering suppression layer 114 may be formed of AlN. The alloy scattering suppression layer 114 may be 1 nm thick. The electron supply layer 116 may be formed of AlGaN.

The source electrode 118, the drain electrode 120, and the gate electrode 122 are formed on the electron supply layer 116. The source electrode 118 and the drain electrode 120 may be ohmic-joined to the electron supply layer 116. The gate electrode 122 may be Schottky bonded to the electron supply layer 116. Since the nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layer in the HFET 140 is an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, an alloy scattering suppression layer 114, and an electron supply layer 116. )to be.

The SiN layer 104 may be formed by nitriding the surface of the (150) surface of the silicon substrate 102. After the silicon substrate 102 is installed in the MOCVD apparatus, NH ₃ may be introduced into the chamber of the MOCVD apparatus for 0.3 minutes at a flow rate of 35 L / min, and the SiN layer 104 may be formed at a temperature of 1000 ° C. .

The AlN buffer layer 106 may be formed of AlN having a thickness of 40 nm. The AlN buffer layer 106 may introduce TMAl and NH ₃ at a flow rate of 175 μmol / min and 35 L / min, respectively, for epitaxial growth. Growth temperature is 1000 degreeC, for example.

The intermediate buffer layer 108 may be formed by repeatedly laminating a layer made of GaN and a layer made of AlN from the silicon substrate 102 side 12 times. The layer made of GaN of the intermediate buffer layer 108 may be 180 μm in thickness. The layer made of AlN of the intermediate buffer layer 108 may be 20 nm thick. The GaN layer of the intermediate buffer layer 108 may be epitaxially grown by introducing TMGa and NH ₃ at a flow rate of 58 μmol / min and 12 L / min, respectively. The layer made of AlN of the intermediate buffer layer 108 may be epitaxially grown by introducing TMAl and NH ₃ at a flow rate of 195 μmol / min and 12 L / min, respectively. All of growth temperature may be 1050 degreeC. All of the pressures may be 50 Torr.

The GaN buffer layer 110 may be formed of GaN. The GaN buffer layer 110 may introduce TMGa and NH ₃ at a flow rate of 58 μmol / min and 12 L / min, respectively, and may be epitaxially grown under a growth temperature of 1050 ° C. and a pressure of 50 Torr.

The electron traveling layer 112 may be formed of GaN having a thickness of 100 nm. The electron traveling layer 112 functions as an electron traveling layer of the HFET 140. The electron traveling layer 112 may introduce TMGa and NH ₃ at a flow rate of 19 μmol / min and 12 L / min, respectively, and may be epitaxially grown under a growth temperature of 1050 ° C. and a pressure of 200 Torr.

The electron supply layer 116 may be formed of AlGaN. The electron supply layer 116 may be 32 nm thick. The electron supply layer 116 functions as an electron supply layer of the HFET 140. The electron supply layer 116 may introduce TMAl, TMGa, and NH ₃ at a flow rate of 100 μmol / min, 19 μmol / min, and 12 L / min, respectively, and may be epitaxially grown at a growth temperature of 1050 ° C. AlGaN of the electron supply layer 116 was evaluated by X-ray diffraction, and the composition ratio of Al was 0.24.

The source electrode 118 and the drain electrode 120 may be formed of a layer made of Ti. The source electrode 118 and the drain electrode 120 may have a layer made of Al on the layer made of Ti. The layer made of Ti is in ohmic bonding by being in contact with the electron supply layer 116. After the source electrode 118 and the drain electrode 120 are formed, heat treatment may be performed. The heat treatment improves the ohmic characteristics. The heat treatment may be performed at 700 ° C. for 30 minutes. The source electrode 118 and the drain electrode 120 may be formed by sputtering or vapor deposition.

The gate electrode 122 may be formed of a layer made of Ni. The gate electrode 122 may have a layer made of Au on the layer made of Ni. The layer made of Ni is in contact with the electron supply layer 116 to be schottky bonded. The gate electrode 122 may be formed by sputtering or vapor deposition.

Table 2 shows the characteristics of the HFET 140 shown in FIG. As a comparative example, the characteristics of the HFET 140 formed on the (111) surface of the silicon substrate 102 are shown. The gate length of the HFET 140 was 2 μm, the gate width was 200 μm, and the source-drain distance was 15 μm. The gate length is the length of the gate electrode 122 in a direction parallel to the current flowing through the electron traveling layer 112. The gate width is the width of the gate electrode 122. The source-drain distance is a distance between the edge part of the gate electrode 122 side of the source electrode 118, and the edge part of the gate electrode 122 side of the drain electrode 120. The leakage current is a value when the voltage between the source electrode 118 and the drain electrode 120 is 200V.

Mobility
(cm ² / Vs) Carrier concentration
(cm ^-3 ) Leakage current
(A / mm) Breaking voltage
(V) HFET (140) 1450 8.1 × 10 ¹² 3.5 × 10 ^-8 1020 Comparative Example 1390 8.1 × 10 ¹² 5.0 × 10 ^-8 850

Since the HFET 140 has good lattice matching between the (150) surface of silicon and the nitride semiconductor layer, the dislocation density of epitaxially grown crystals is low. Since the HFET 140 has a lower spiral potential density than the comparative example, the HFET 140 has a low leakage current and a high breakdown voltage. The HFET 140 has higher mobility because the blade dislocation density is lower than that of the comparative example. The HFET 140 has a mobility of 1400 cm ² / Vs or more. The HFET 140 has a leakage current of 4.0 × 10 ^-8 A / mm or less. The HFET 140 has a breakdown voltage of 900 V or more.

10 is a schematic cross-sectional view of the HFET 150 according to the second embodiment of the present invention. In FIG. 10, elements denoted by the same reference numerals as those in FIG. 9 may have the same functions and configurations as those described in FIG. 9. The HFET 140 includes a silicon substrate 102, an SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, an electron supply layer 116, The source electrode 118, the drain electrode 120, and the gate electrode 122 are provided. The HFET 150 is the same as the HFET 140 shown in FIG. 9 except that the alloy scattering suppression layer 114 is not provided. Since the alloy scattering suppression layer 114 is not provided, the electron supply layer 116 is formed on the electron traveling layer 112.

In the HFET 150, since the nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layer in FIG. 10 is an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 112, and an electron supply layer 116. Since the HFET 150 has good lattice matching between the (150) surface of silicon and the nitride semiconductor layer, the dislocation density of epitaxially grown crystals is low. Since the HFET 150 has a lower spiral potential density than the HFET formed on the silicon 111 surface, the HFET 150 has a low leakage current and a high breakdown voltage. Since the HFET 150 has a lower blade dislocation density than the HFET formed on the silicon 111 surface, the HFET 150 has high mobility.

11 is a schematic cross-sectional view of the Schottky barrier diode 160 according to the third embodiment of the present invention. In FIG. 11, elements denoted by the same reference numerals as those in FIG. 6 may have the same functions and configurations as those described in FIG. 6. The Schottky barrier diode 160 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an electron traveling layer 162, and an ohmic electrode 164. ) And a Schottky electrode 166.

The silicon substrate 102 shown in FIG. 11 is a substrate made of silicon having a plane orientation 150. The SiN layer 104, the AlN buffer layer 106, the intermediate buffer layer 108, and the GaN buffer layer 110 have the same configuration as the HFET 140 of FIG. 9. On the GaN buffer layer 110, the electron traveling layer 162 is formed. The ohmic electrode 164 and the schottky electrode 166 are formed on the electron traveling layer 162. The ohmic electrode 164 is ohmic-bonded to the electron traveling layer 162. The schottky electrode 166 is schottky bonded to the electron traveling layer 162.

In the Schottky barrier diode 160, since the nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layer in FIG. 11 is an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, and an electron traveling layer 162.

The electron running layer 162 may be formed of n-GaN. The electron traveling layer 162 may be n-GaN doped with silicon. The carrier concentration of the electron traveling layer 162 may be 2 x 10 ¹⁶ cm ^-3 .

The electron traveling layer 162 may be n-GaN having a thickness of 500 nm. The electron running layer 162 introduces TMGa, NH ₃ and SH ₄ at 19 μmol / min, 12 L / min and a predetermined flow rate, respectively, and epitaxially, under a growth temperature of 1050 ° C. and a pressure of 200 Torr. You may grow.

The ohmic electrode 164 may be formed with the layer which consists of Ti. The ohmic electrode 164 may have a layer made of Al on the layer made of Ti. The layer made of Ti is in ohmic bonding by contacting the electron traveling layer 162. After the ohmic electrode 164 is formed, heat treatment may be performed. By the heat treatment, the resistance characteristics are improved. The heat treatment may be performed at 700 ° C. for 30 minutes. The ohmic electrode 164 may be formed by sputtering or vapor deposition.

The schottky electrode 166 may be formed of a layer made of Ni. The electron supply layer 116 may have a layer made of Au on the layer made of Ni. The layer made of Ni is in contact with the electron traveling layer 162 to be schottky bonded. The schottky electrode 166 may be formed by sputtering or vapor deposition.

FIG. 12 shows the characteristics of the Schottky barrier diode 160 shown in FIG. The solid line corresponds to the Schottky barrier diode 160 shown in FIG. The Schottky electrode 166 was made into the circular shape of 160 micrometers in diameter. The distance between the electrodes of the ohmic electrode 164 and the schottky electrode 166 was 10 μm, and the ohmic electrode 164 was formed concentrically with the schottky electrode 166. As a comparative example, the characteristics of the Schottky barrier diode 160 formed in the same manner on the silicon (111) plane are indicated by broken lines.

The Schottky barrier diode 160 shown in FIG. 11 has a 1.5-fold mobility compared with the Schottky barrier diode 160 formed in the same manner on the silicon 111 surface. The Schottky barrier diode 160 has a nitride semiconductor layer formed on the (150) surface of the silicon substrate 102 because the dislocation density is low. In particular, the effect of the lower blade dislocation density. The Schottky barrier diode 160 has a current of 1 mA and a current of 15 mA.

FIG. 13: is a schematic cross section of the MOSFET 170 which concerns on 4th Embodiment of this invention. In FIG. 13, elements denoted by the same reference numerals as those in FIG. 6 may have the same functions and configurations as those described in FIG. 6. The MOSFET 170 includes a silicon substrate 102, a SiN layer 104, an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, an inversion layer 172, a gate oxide film 176, a source electrode. 178, a gate electrode 180, and a drain electrode 182. The inversion layer 172 consists of p-GaN. The inversion layer 172 is in contact with the source electrode 178 and the drain electrode 182, and has a contact region 174. As a result, the source electrode 178 and the drain electrode 182 are ohmicly connected to the inversion layer 172.

The silicon substrate 102 shown in FIG. 13 is a substrate made of silicon having a plane orientation 150. The SiN layer 104, the AlN buffer layer 106, the intermediate buffer layer 108, and the GaN buffer layer 110 have the same configuration as the HFET 140 of FIG. 9. On the GaN buffer layer 110, an inversion layer 172 is formed. The gate oxide film 176 is formed on the inversion layer 172. The gate electrode 180 is formed on the gate oxide film 176.

In the MOSFET 170, since the nitride semiconductor layer is formed on the (150) surface of the silicon substrate 102, the dislocation density of the nitride semiconductor layer is low. The nitride semiconductor layer shown in FIG. 13 is an AlN buffer layer 106, an intermediate buffer layer 108, a GaN buffer layer 110, and an inversion layer 172. The MOSFET 170 formed on the (150) surface of the silicon substrate 102 shown in FIG. 13 has a lower interface level, lower on-resistance, and mobility than the MOSFET 170 formed on the Si (111) surface as well. On the other hand, the internal pressure is high. This is because the dislocation density of the nitride semiconductor layer is low.

The inversion layer 172 may be p-GaN doped with magnesium. The p-type dopant may be Zn or Be. The carrier concentration of the inversion layer 172 may be 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3 . The thickness of the inversion layer 172 may be 300 nm.

The inversion layer 172 introduces TMGa, NH _3, and bis (cyclopoentadienyl) magnesium (Cp 2 Mg) at 19 μmol / min, 12 L / min and a predetermined flow rate, respectively, to achieve a growth temperature of 1050 ° C. and 200 Torr. Under pressure, it may be epitaxially grown.

The contact region 174 may be an n + GaN region. n + GaN means a region where the concentration of the n-type carrier is higher than the n-type carrier concentration of n-GaN or the p-type carrier concentration of p-GaN. The carrier concentration of the n + GaN region may be 1 × 10 ¹⁸ cm ⁻³ or more. The contact region 174 may be formed by doping the n-type dopant in the inversion layer 172. The dope may be performed by ion implantation of an n-type dopant. The contact region 174 may be doped with Si at an acceleration voltage of 150 keV and the carrier concentration may be 5 × 10 ¹⁸ cm ⁻³ .

The gate oxide film 176 may be formed of an oxide film. The gate oxide film 176 may be formed of SiO ₂ . The gate oxide film 176 may be formed with a thickness of 60 nm to 100 nm. The gate oxide film 176 may be formed by plasma CVD. After the gate oxide film 176 is formed, it may be heated and annealed. By the annealing treatment, the density of the interface level at the interface between the inversion layer 172 and the gate oxide film 176 decreases. The annealing treatment may be performed at 800 ° C to 1000 ° C for 30 minutes.

The gate electrode 180 may be formed of a conductor. The gate electrode 180 may be formed of polysilicon. The source electrode 178 and the drain electrode 182 may be formed of a material in ohmic contact with the contact region 174. The source electrode 178 and the drain electrode 182 may be formed of a layer made of Ti. The source electrode 178 and the drain electrode 182 may have a layer made of Al on the layer made of Ti. The layer made of Ti is in ohmic bonding by contacting the electron traveling layer 162. After the source electrode 178 and the drain electrode 182 are formed, heat treatment may be performed. The heat treatment improves the ohmic characteristics. The heat treatment may be performed at 700 ° C. for 30 minutes. The source electrode 178 and the drain electrode 182 may be formed by sputtering or vapor deposition.

The distance between the gate and source and the distance between the gate and the drain may be the same. The gate-source distance is a distance between an end portion on the source electrode 178 side of the gate electrode 180 and an end portion on the gate electrode 180 side of the source electrode 178. The gate-drain distance is a distance between an end portion on the drain electrode 182 side of the gate electrode 180 and an end portion on the gate electrode 180 side of the drain electrode 182. The gate-source distance and the gate-drain distance may be 10 μm.

Although the present invention has been described using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be added to the above embodiments. It is clear from description of a claim that the form which added such a change or improvement can also be included in the technical scope of this invention.

The order of execution of each process such as operations, procedures, steps, and steps in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is specifically stated as "before", "before", and the like. It should be noted that the present invention can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the specification, and the drawings, descriptions made using "priority,""next," and the like for convenience do not necessarily imply that it is necessary to carry out in this order.

100 semiconductor substrate
102 silicon substrate
104 SiN layer
106 AlN buffer layer
108 intermediate buffer layer
110 GaN buffer layer
112 electronic traveling floor
114 Alloy Scattering Suppression Layer
116 electron supply layer
118 source electrode
120 drain electrode
122 gate electrode
130 semiconductor substrate
140 HFET
150 HFET
160 Schottky Barrier Diodes
162 electronic traveling floor
164 Ohmic Electrodes
166 Schottky Electrodes
170 MOSFET
172 Inversion Layer
174 contact area
176 gate oxide
178 source electrode
180 gate electrode
182 drain electrode

Claims (17)

A silicon substrate; And
A nitride semiconductor layer epitaxially grown on the (150) surface of the silicon substrate
Including,
A semiconductor substrate.
The method of claim 1,
Further comprising a silicon nitride layer formed between the silicon substrate and the nitride semiconductor layer,
A semiconductor substrate.
3. The method of claim 2,
The silicon nitride layer is a thickness of 2 atomic layers or less,
A semiconductor substrate.
4. The method according to any one of claims 1 to 3,
The nitride semiconductor layer is one of GaN, AlGaN and AlN, or a layer in which these are laminated
A semiconductor substrate.
5. The method according to any one of claims 1 to 4,
The growth surface of the nitride semiconductor layer is a (0001) plane,
A semiconductor substrate.
The method according to any one of claims 1 to 5,
The silicon substrate is cut out of the silicon single crystal grown by the CZ method,
A semiconductor substrate.
The semiconductor device formed in the semiconductor substrate of any one of Claims 1-6.
8. The method of claim 7,
The nitride semiconductor layer is an electron traveling layer on which electrons travel,
The semiconductor device is a field effect transistor,
A semiconductor device.
9. The method of claim 8,
Mobility is more than 1400 cm ² / Vs,
A semiconductor device.
8. The method of claim 7,
Which is either a Schottky barrier diode and a MOS transistor,
A semiconductor device.
A nitride semiconductor layer forming step of epitaxially growing a nitride semiconductor layer made of a nitride semiconductor on the (150) surface of the silicon substrate,
A method of manufacturing a semiconductor substrate.
12. The method of claim 11,
Before the nitride semiconductor layer forming step, further comprising the step of forming a silicon nitride layer by nitriding the (150) surface of the silicon substrate,
A method of manufacturing a semiconductor substrate.
The method of claim 12,
The silicon nitride layer has a film thickness of 2 atomic layers or less,
A method of manufacturing a semiconductor substrate.
14. The method according to any one of claims 11 to 13,
The nitride semiconductor layer is one of GaN, AlGaN and AlN, or a layer in which these are laminated
A method of manufacturing a semiconductor substrate.
15. The method according to any one of claims 11 to 14,
The growth surface of the nitride semiconductor layer is a (0001) plane,
A method of manufacturing a semiconductor substrate.
The method according to any one of claims 11 to 15,
The silicon substrate is cut out of the silicon single crystal grown by the CZ method,
A method of manufacturing a semiconductor substrate.
The semiconductor device formed on the semiconductor substrate manufactured by the manufacturing method of the semiconductor substrate of any one of Claims 11-16.

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