JP5384450B2 - Compound semiconductor substrate - Google Patents
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- JP5384450B2 JP5384450B2 JP2010197207A JP2010197207A JP5384450B2 JP 5384450 B2 JP5384450 B2 JP 5384450B2 JP 2010197207 A JP2010197207 A JP 2010197207A JP 2010197207 A JP2010197207 A JP 2010197207A JP 5384450 B2 JP5384450 B2 JP 5384450B2
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- 239000000758 substrate Substances 0.000 title claims description 134
- 239000004065 semiconductor Substances 0.000 title claims description 77
- 150000001875 compounds Chemical class 0.000 title claims description 46
- 239000013078 crystal Substances 0.000 claims description 83
- 239000002019 doping agent Substances 0.000 claims description 82
- 230000007704 transition Effects 0.000 claims description 36
- 150000004767 nitrides Chemical class 0.000 claims description 28
- 230000007423 decrease Effects 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 60
- 238000000034 method Methods 0.000 description 21
- 230000000694 effects Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 11
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 9
- 230000007547 defect Effects 0.000 description 9
- 229910002601 GaN Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000001947 vapour-phase growth Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 4
- 238000005336 cracking Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000002244 precipitate Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
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- 230000008569 process Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 238000012935 Averaging Methods 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
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- 238000000638 solvent extraction Methods 0.000 description 1
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- Crystals, And After-Treatments Of Crystals (AREA)
- Chemical Vapour Deposition (AREA)
Description
本発明は、発光ダイオード、レーザ発光素子、その他各種の電子素子用のＨＥＭＴ（High Electron Mobility Transistor；高電子移動度トランジスタ）構造を有する窒化物半導体等の化合物半導体に用いられる化合物半導体基板に関する。 The present invention relates to a compound semiconductor substrate used for a compound semiconductor such as a nitride semiconductor having a HEMT (High Electron Mobility Transistor) structure for light emitting diodes, laser light emitting elements, and other various electronic elements.
化合物半導体、特に、窒化ガリウム（ＧａＮ）や窒化アルミニウム（ＡｌＮ）等からなるワイドバンドギャップ窒化物半導体デバイスは、そのバンド構造を生かした青色、紫外等の短波長の発光デバイスの他、ヘテロ接合界面に発生する２次元電子ガスの高い電子移動度、材料自体の持つ高い耐熱性等の優れた特性を生かしたスイッチング電源向けの高速・高耐圧電子デバイスや、高周波アンプ向けの超高速電子デバイス等への応用が期待されている。 Compound semiconductors, especially wide bandgap nitride semiconductor devices made of gallium nitride (GaN), aluminum nitride (AlN), etc., are used for light emitting devices with short wavelengths such as blue and ultraviolet, and heterojunction interfaces. High-speed and high-voltage electronic devices for switching power supplies that take advantage of the high electron mobility of the two-dimensional electron gas generated in the material and the high heat resistance of the material itself, and ultra-high-speed electronic devices for high-frequency amplifiers The application of is expected.
この窒化物半導体に用いる窒化物半導体基板は、一例として、サファイア、６Ｈ−ＳｉＣ、Ｓｉ等の異種基板上へ窒化物半導体結晶を薄膜で成膜する方法で作製できるが、この場合、特にＳｉ基板を用いた場合は、他の異種基板と比べて、高品質な結晶を安定供給でき、低価格で大面積の基板が得られる点で、好適といえる。以下、このような異種材料基板上に窒化物半導体結晶を製膜したものを、化合物半導体基板と呼ぶこととする。 As an example, the nitride semiconductor substrate used for the nitride semiconductor can be manufactured by a method of forming a nitride semiconductor crystal as a thin film on a dissimilar substrate such as sapphire, 6H-SiC, Si, etc. Is preferable in that a high-quality crystal can be stably supplied and a large-area substrate can be obtained at a low price compared to other types of substrates. Hereinafter, a nitride semiconductor crystal formed on such a different material substrate is referred to as a compound semiconductor substrate.
ところで、Ｓｉ基板上に窒化物半導体結晶を成膜する場合、Ｓｉと窒化物半導体との熱膨張係数の違いにより発生する応力起因の基板の反り、窒化物半導体単結晶膜の割れさらにはＳｉ基板へのスリップ欠陥の導入といった問題がある。この解決のためにさまざまな方法が考えられており、Ｓｉ基板の基板特性を最適設計する手法も、いくつか試みられている。 By the way, when a nitride semiconductor crystal is formed on a Si substrate, warpage of the substrate due to a difference in thermal expansion coefficient between Si and the nitride semiconductor, cracking of the nitride semiconductor single crystal film, and Si substrate There are problems such as the introduction of slip defects. Various methods have been considered for solving this problem, and several methods for optimally designing the substrate characteristics of the Si substrate have been tried.
具体的には、Ｓｉ中の各種物質の濃度、例えば酸素濃度、窒素濃度、炭素濃度、酸素析出物等の欠陥濃度、ドーパント濃度を制御することが考えられる。特に、ドーパントとして含まれるボロン（Ｂ）、リン（Ｐ）、ヒ素（Ａｓ）等の各種元素の濃度を高くするとＳｉ基板の機械強度が向上することから、窒化物半導体基板の反りや割れ、スリップなどの欠陥導入頻度を大幅に低減させることが可能である。 Specifically, it is conceivable to control the concentration of various substances in Si, for example, oxygen concentration, nitrogen concentration, carbon concentration, defect concentration such as oxygen precipitates, and dopant concentration. In particular, when the concentration of various elements such as boron (B), phosphorus (P), and arsenic (As) contained as dopants is increased, the mechanical strength of the Si substrate is improved. It is possible to greatly reduce the frequency of defect introduction.
例えば、特許文献１には、シリコン基板よりも大きい熱膨張率を持つ半導体材料の層をエピタキシャル成長させても、シリコン基板の湾曲を抑制することができるシリコン基板及びその製造方法を提供することを目的として、一の主面からまたは該主面近傍の所定の深さから裏面まで、連続的または段階的に減少する窒素不純物の濃度分布を有し、該窒素不純物の濃度分布に概ね対応して分布する酸素析出物を有することを特徴とするシリコン基板という技術が開示されている。 For example, Patent Document 1 aims to provide a silicon substrate capable of suppressing the curvature of the silicon substrate even when a layer of a semiconductor material having a thermal expansion coefficient larger than that of the silicon substrate is epitaxially grown, and a method for manufacturing the same. A concentration distribution of nitrogen impurities that decreases continuously or stepwise from one main surface or from a predetermined depth in the vicinity of the main surface to the back surface, and a distribution approximately corresponding to the concentration distribution of the nitrogen impurities. There is disclosed a technique of a silicon substrate characterized by having oxygen precipitates.
また、特許文献２には、反りや割れの発生や、Ｓｉ基板へのスリップ欠陥の導入という課題の解決に関するものではないが、順方向電圧（Ｖｆ）が従来よりも低い窒化物系半導体素子を提供する目的で、基板にＳｉを用いる窒化物系半導体素子において、Ｓｉ基板の少なくとも一部と窒化物半導体層とを能動領域に含み、Ｓｉ基板における能動領域の導電型がｐ型であること、あるいは、Ｓｉ基板における能動領域の不純物濃度が、１Ｅ＋１８ａｔｏｍｓ／ｃｍ３以上１Ｅ＋２２ａｔｏｍｓ／ｃｍ３以下である窒化物系半導体素子という技術が開示されている。 Further, Patent Document 2 does not relate to the solution of the problems of warpage and cracking and the introduction of slip defects to the Si substrate, but a nitride-based semiconductor element having a forward voltage (Vf) lower than that of the prior art. For the purpose of providing, in a nitride semiconductor device using Si for a substrate, the active region includes at least a part of the Si substrate and a nitride semiconductor layer, and the conductivity type of the active region in the Si substrate is p-type, Alternatively, a technique of a nitride-based semiconductor element in which the impurity concentration of the active region in the Si substrate is 1E + 18 atoms / cm 3 or more and 1E + 22 atoms / cm 3 or less is disclosed.
ところで、Ｓｉ中のドーパント濃度については、例えば非特許文献１では、Ｓｉ中のドーパント濃度が高くなると、Ｓｉの熱伝導性が低下するということが開示されている。 By the way, about the dopant density | concentration in Si, for example, the nonpatent literature 1 is disclosing that the thermal conductivity of Si will fall, if the dopant density | concentration in Si becomes high.
特許文献１に記載の方法においては、酸素析出の生成時における膨張力を利用することにより、化合物半導体基板の反りを制御する方法が開示されているが、この方法は、化合物半導体層を形成後、所定の熱処理によって酸素析出物を生成させ、反りの制御を行うため、化合物半導体層の形成時に発生する応力は、従来と同様となる。そのため、化合物半導体層の形成時に発生するＳｉ基板へのスリップ欠陥導入に関しては、効果が得られない。 In the method described in Patent Document 1, a method of controlling the warpage of the compound semiconductor substrate by utilizing the expansion force at the time of generation of oxygen precipitation is disclosed, but this method is performed after the formation of the compound semiconductor layer. Since oxygen precipitates are generated by a predetermined heat treatment and the warpage is controlled, the stress generated during the formation of the compound semiconductor layer is the same as in the prior art. Therefore, no effect is obtained with respect to the introduction of slip defects to the Si substrate that occurs during the formation of the compound semiconductor layer.
特許文献２は、順方向電圧（Ｖｆ）が従来よりも低い窒化物系半導体素子を提供する目的で、Ｓｉ基板とＧａＮ層の界面に接するＳｉ基板の不純物すなわちドーパント濃度を高くすることが記載されており、Ｓｉ基板の不純物濃度が窒化物半導体の特性に影響することが示唆されている。しかし、反りや割れの発生や、転位や結晶欠陥の多発という課題に対して、Ｓｉ基板中のドーパント濃度の形態がどのように影響するかについては、特許文献２の記載のみでは明らかでないと考えられる。 Patent Document 2 describes that the impurity concentration of the Si substrate in contact with the interface between the Si substrate and the GaN layer, that is, the dopant concentration is increased for the purpose of providing a nitride-based semiconductor element having a lower forward voltage (Vf) than the conventional one. It is suggested that the impurity concentration of the Si substrate affects the characteristics of the nitride semiconductor. However, it is considered that it is not clear only by the description of Patent Document 2 how the form of the dopant concentration in the Si substrate affects the problems of warpage and cracking, and the frequent occurrence of dislocations and crystal defects. It is done.
一般に、Ｓｉ中のドーパントの濃度を高くすると、機械強度の向上、すなわち臨界せん断応力値の向上がみられるので、スリップ発生や反りの抑制には効果的である。一方、ドーパント濃度が高い場合においては、非特許文献１に記載されているように、Ｓｉ単結晶の熱伝導率が低下してしまい、化合物半導体基板を窒化物半導体光・電子デバイスとして用いるには好ましくない。高濃度ドーピングにおける機械強度と熱伝導率にはトレードオフの関係が存在するため、ドーパントの濃度、深さ方向の分布については、最適設計が必要となるが、これまでに十分な検討がなされていたとは言い難い。 In general, when the dopant concentration in Si is increased, mechanical strength is improved, that is, the critical shear stress value is improved, which is effective in suppressing slip generation and warpage. On the other hand, when the dopant concentration is high, as described in Non-Patent Document 1, the thermal conductivity of the Si single crystal is lowered, and the compound semiconductor substrate is used as a nitride semiconductor optical / electronic device. It is not preferable. Since there is a trade-off relationship between mechanical strength and thermal conductivity in high-concentration doping, optimal design is necessary for the dopant concentration and distribution in the depth direction, but sufficient studies have been made so far. It's hard to say.
本発明は、これらの課題を鑑みてなされたもので、効果的に転位発生の防止と基板の反りの低減を成すとともに、熱伝導率の低下を必要最小限に抑えることを簡易な手法で実現する、Ｓｉ単結晶基板を用いた化合物半導体基板を提供するものである。 The present invention has been made in view of these problems, and effectively achieves the prevention of dislocation generation and the reduction of the warpage of the substrate while minimizing the decrease in thermal conductivity to a necessary minimum. A compound semiconductor substrate using a Si single crystal substrate is provided.
本発明に係る化合物半導体基板は、Ｓｉ単結晶基板と、前記Ｓｉ単結晶基板の一主面上形成された化合物半導体からなる中間層と、前記中間層上に形成された化合物半導体からなるデバイス活性層から構成され、前記Ｓｉ単結晶基板は、前記中間層側の一主面の表面から厚さ方向に向かって平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である領域１と、前記領域１に続いて形成されドーパント濃度が連続的に減少する遷移領域１と、前記遷移領域１に続いて形成され平均ドーパント濃度が１×１０１２ａｔｏｍｓ／ｃｍ３以上５×１０１７ａｔｏｍｓ／ｃｍ３以下である領域２と、前記領域２に続いて形成されドーパント濃度が連続的に増加する遷移領域２と、前記遷移領域２に続いて前記Ｓｉ単結晶基板の他主面の表面まで形成され平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である領域３とが順次形成され、さらに、前記領域１と前記領域３のそれぞれの厚さが前記Ｓｉ単結晶基板の全体の厚さに対して１５％以上３５％以下の範囲であることを特徴とする。このような構成をとることで、基板におけるスリップなどの転位発生防止、基板の反り低減、基板の熱伝導率低下抑制という効果を、効率よく併せ持つ化合物半導体基板とすることができる。 The compound semiconductor substrate according to the present invention includes a Si single crystal substrate, an intermediate layer made of a compound semiconductor formed on one main surface of the Si single crystal substrate, and a device activity made of a compound semiconductor formed on the intermediate layer. The Si single crystal substrate has an average dopant concentration of 1 × 10 19 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 in the thickness direction from the surface of one main surface on the intermediate layer side. The following region 1, the transition region 1 formed following the region 1 where the dopant concentration continuously decreases, and the average dopant concentration formed following the transition region 1 is 1 × 10 12 atoms / cm 3 or more and 5 × 10 17 atoms / cm 3 regions 2 or less, a transition region 2 in which the dopant concentration is subsequently formed on the region 2 increases continuously, connection to the transition region 2 And region 3 average dopant concentration is formed to the surface of the other main surface is 1 × 10 21 atoms / cm 3 or less 1 × 10 19 atoms / cm 3 or more of the Si single crystal substrate Te are sequentially formed, further wherein The thickness of each of the region 1 and the region 3 is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate. By adopting such a configuration, it is possible to obtain a compound semiconductor substrate that efficiently combines the effects of preventing the occurrence of dislocation such as slip in the substrate, reducing the warpage of the substrate, and suppressing the decrease in thermal conductivity of the substrate.
また、本発明に係る化合物半導体基板におけるドーパントは、ボロン（Ｂ）、リン（Ｐ）、アンチモン（Ｓｂ）、ヒ素（Ａｓ）、アルミニウム（Ａｌ）、ガリウム（Ｇａ）、ゲルマニウム（Ｇｅ）のうち、いずれか１種類もしくは複数種類であることがさらに好ましい。このような構成をとることで、簡易かつ低コストで、効率よく基板におけるスリップなどの転位発生防止、基板の反り低減、基板の熱伝導率低下抑制という効果を得ることが出来る。これらの元素はＳｉの格子位置に置換して固溶するため、固溶強化によりＳｉ基板の機械強度、即ち臨界せん断応力を向上させることが出来る。 The dopant in the compound semiconductor substrate according to the present invention is boron (B), phosphorus (P), antimony (Sb), arsenic (As), aluminum (Al), gallium (Ga), germanium (Ge), More preferably, any one kind or plural kinds. By adopting such a configuration, it is possible to obtain the effects of preventing the occurrence of dislocation such as slip in the substrate, reducing the warpage of the substrate, and suppressing the decrease in the thermal conductivity of the substrate easily and at low cost. Since these elements are substituted into the lattice positions of Si and are dissolved, the mechanical strength of the Si substrate, that is, the critical shear stress can be improved by solid solution strengthening.
また、本発明に係る化合物半導体基板においては、中間層およびデバイス活性層は、アルミニウム（Ａｌ）とガリウム（Ｇａ）を含む窒化物半導体からなることが好ましい。このような構成をとることで、ワイドバンドギャップ材料の特性を生かした半導体デバイスの実現が可能となる他、それらの組み合わせによって、優れた基板の反り低減効果を発揮することが出来る。 In the compound semiconductor substrate according to the present invention, the intermediate layer and the device active layer are preferably made of a nitride semiconductor containing aluminum (Al) and gallium (Ga). By adopting such a configuration, it is possible to realize a semiconductor device utilizing the characteristics of the wide band gap material, and it is possible to exhibit an excellent substrate warpage reduction effect by combining them.
本発明に係る化合物半導体基板は、化合物半導体基板において重要である、スリップなどの欠陥発生防止、基板の反り低減、および基板厚さ方向の熱伝導率低下抑制という効果を、簡易な基板構造で効率的かつバランスよく実現することができ、優れた特性を有する化合物半導体基板を提供することが可能となる。 The compound semiconductor substrate according to the present invention has the effects of preventing defects such as slips, reducing the warpage of the substrate, and suppressing the decrease in thermal conductivity in the substrate thickness direction, which are important in the compound semiconductor substrate, with a simple substrate structure. Therefore, it is possible to provide a compound semiconductor substrate that can be realized in a proper and balanced manner and has excellent characteristics.
以下、本発明の実施形態について詳細に説明する。図１は、本発明の一実施形態に係る化合物半導体基板の構造を示す概念図、図２は、本発明に係るＳｉ単結晶基板の厚さ方向における領域１と領域２の関係を示す概念図、図３は、本発明に係るＳｉ単結晶基板の厚さ方向における遷移領域のドーパント濃度プロファイルの他の形態を示す概念図、図４は、本発明に係るＳｉ単結晶基板の各領域の形態を示す概略図、そして図５は、本発明に係るＳｉ単結晶基板の応力と曲げモーメントの関係を示す式と概念図である。 Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a conceptual diagram showing the structure of a compound semiconductor substrate according to an embodiment of the present invention. FIG. 2 is a conceptual diagram showing the relationship between regions 1 and 2 in the thickness direction of a Si single crystal substrate according to the present invention. FIG. 3 is a conceptual diagram showing another form of the dopant concentration profile in the transition region in the thickness direction of the Si single crystal substrate according to the present invention, and FIG. 4 is a view of each region of the Si single crystal substrate according to the present invention. FIG. 5 is a schematic diagram showing the relationship between the stress and bending moment of the Si single crystal substrate according to the present invention.
本発明に係る化合物半導体基板は、Ｓｉ単結晶基板と、前記Ｓｉ単結晶基板の一主面上に形成された化合物半導体からなる中間層と、前記中間層上に形成された化合物半導体からなるデバイス活性層から構成され、前記Ｓｉ単結晶基板は、前記中間層側の一主面の表面から厚さ方向に向かって平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である領域１と、前記領域１に続いて形成されドーパント濃度が連続的に減少する遷移領域１と、前記遷移領域１に続いて形成され平均ドーパント濃度が１×１０１２ａｔｏｍｓ／ｃｍ３以上５×１０１７ａｔｏｍｓ／ｃｍ３以下である領域２と、前記領域２に続いて形成されドーパント濃度が連続的に増加する遷移領域２と、前記遷移領域２に続いて前記Ｓｉ単結晶基板の他主面の表面まで形成され平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である領域３とが順次形成され、さらに、前記領域１と前記領域３のそれぞれの厚さが前記Ｓｉ単結晶基板の全体の厚さに対して、１５％以上３５％以下の範囲である。 A compound semiconductor substrate according to the present invention includes a Si single crystal substrate, an intermediate layer made of a compound semiconductor formed on one main surface of the Si single crystal substrate, and a device made of a compound semiconductor formed on the intermediate layer. The Si single crystal substrate is composed of an active layer, and the Si single crystal substrate has an average dopant concentration of 1 × 10 19 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 in the thickness direction from the surface of one main surface on the intermediate layer side. A region 1 that is 3 or less, a transition region 1 that is formed following the region 1 and the dopant concentration continuously decreases, and an average dopant concentration that is formed following the transition region 1 is 1 × 10 12 atoms / cm 3. or a 5 × 10 17 atoms / cm 3 regions 2 or less, a transition region 2 in which the dopant concentration is subsequently formed on the region 2 increases continuously, the transition region 2 There the average dopant concentration is formed to the surface of the other main surface is 1 × 10 19 atoms / cm 3 or more 1 × 10 21 atoms / cm 3 region 3 is less than the Si single crystal substrate is sequentially formed, further wherein The thickness of each of the region 1 and the region 3 is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate.
Ｓｉ単結晶基板は、化合物半導体を形成する下地として用いられるが、基本的な製法や結晶構造は特に限定されるものではなく、公知の半導体デバイス作製用のＳｉ単結晶基板を広く用いることができる。例えば、Ｓｉ単結晶育成方法としてはＣＺ法でもＦＺ法でもよく、基板加工処理として各種熱処理を施したウェーハも適用できる。また、基板の面方位やベベル形状、化合物半導体が形成される主面および裏面の面粗さ等の仕上げ状態についても、設計する化合物半導体基板の仕様に合わせて適時選択できる。 The Si single crystal substrate is used as a base for forming a compound semiconductor, but the basic manufacturing method and crystal structure are not particularly limited, and a wide variety of known Si single crystal substrates for manufacturing semiconductor devices can be used. . For example, the CZ method or the FZ method may be used as the Si single crystal growth method, and wafers that have been subjected to various heat treatments as the substrate processing treatment can also be applied. Further, the finished state such as the surface orientation of the substrate, the bevel shape, and the surface roughness of the main surface and the back surface on which the compound semiconductor is formed can be appropriately selected according to the specifications of the compound semiconductor substrate to be designed.
Ｓｉ単結晶基板の一主面上に形成された化合物半導体からなる中間層は、Ｓｉ基板とデバイス活性層である化合物半導体との、格子定数の違いによる不整合や熱膨張係数の違いにより発生する応力を緩和する働きをもつ。中間層の構造については、特に限定されるものではないが、比較的簡易に作製できることから、任意の厚さと組成をもつ化合物半導体の積層からなる多層構造であることが好ましい。 An intermediate layer made of a compound semiconductor formed on one main surface of a Si single crystal substrate is generated due to mismatch between the Si substrate and the compound semiconductor which is a device active layer due to a difference in lattice constant or a difference in thermal expansion coefficient. It works to relieve stress. The structure of the intermediate layer is not particularly limited, but it is preferably a multilayer structure composed of a stack of compound semiconductors having an arbitrary thickness and composition because it can be manufactured relatively easily.
中間層上には化合物半導体からなるデバイス活性層が形成される。化合物半導体としては、各種の材料が適用でき、例えばＡｌＧａＮ等の窒化物半導体結晶が用いられる。 A device active layer made of a compound semiconductor is formed on the intermediate layer. Various materials can be applied as the compound semiconductor, and for example, a nitride semiconductor crystal such as AlGaN is used.
そして、Ｓｉ単結晶基板は、前記中間層側の一主面の表面から厚さ方向に向かって平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である領域１と、前記領域１に続いて形成されドーパント濃度が連続的に減少する遷移領域１と、前記遷移領域１に続いて形成され平均ドーパント濃度が１×１０１２ａｔｏｍｓ／ｃｍ３以上５×１０１７ａｔｏｍｓ／ｃｍ３以下である領域２と、前記領域２に続いて形成されドーパント濃度が連続的に増加する遷移領域２と、前記遷移領域２に続いて前記Ｓｉ単結晶基板の他主面の表面まで形成され平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である領域３と、が順次形成されている。 In the Si single crystal substrate, a region in which an average dopant concentration is 1 × 10 19 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 or less in the thickness direction from the surface of one main surface on the intermediate layer side. 1, a transition region 1 formed following the region 1 where the dopant concentration continuously decreases, and an average dopant concentration formed following the transition region 1 of 1 × 10 12 atoms / cm 3 or more 5 × 10 17 a region 2 that is atoms / cm 3 or less, a transition region 2 that is formed following the region 2 and in which the dopant concentration continuously increases, and a surface of the other principal surface of the Si single crystal substrate following the transition region 2 The region 3 having an average dopant concentration of 1 × 10 19 atoms / cm 3 to 1 × 10 21 atoms / cm 3 is formed sequentially.
本発明において、領域１から領域３における平均ドーパント濃度とは、例えば領域１なら、一主面の表面から深さ方向における区間を任意に分割して得られた点でのドーパント濃度を平均した値で表現される。そして、ドーパント濃度は、例えば、広がり抵抗（ＳＲ）測定法や二次イオン質量分析（ＳＩＭＳ）法などの測定手法により、Ｓｉ単結晶基板の深さ方向に対して、数点望ましくは数十点以上測定することで得られる。このとき同時に、各領域の厚さも測定されるが、厚さは、別途他の手法で測定することもできる。なお、深さ方向とは、Ｓｉ単結晶基板の厚さ方向と同義で、一主面から他主面に対してほぼ垂直に向かう方向のことを指している。 In the present invention, the average dopant concentration in the region 1 to the region 3 is, for example, in the case of the region 1, a value obtained by averaging the dopant concentrations at points obtained by arbitrarily dividing a section in the depth direction from the surface of one main surface. It is expressed by The dopant concentration is several points, preferably several tens of points in the depth direction of the Si single crystal substrate, for example, by a measuring method such as a spreading resistance (SR) measurement method or a secondary ion mass spectrometry (SIMS) method. Obtained by measuring above. At the same time, the thickness of each region is also measured, but the thickness can also be measured by another method. The depth direction is synonymous with the thickness direction of the Si single crystal substrate, and refers to a direction from one main surface to a direction substantially perpendicular to the other main surface.
本発明においては、ドーパント濃度の平均値が本発明の実施範囲内であればよく、例えば領域１で２０ポイント測定して、１ポイントのドーパント濃度の測定値が領域２の濃度範囲であっても特に問題ない。この場合の目安として、測定ポイントの９０％以上、より好ましくは９５％以上が領域１の範囲であれば、それ以外の測定ポイントが全て領域２の濃度の範囲であっても、本発明の効果に大きな影響を与えない。 In the present invention, the average value of the dopant concentration only needs to be within the implementation range of the present invention. For example, 20 points are measured in the region 1, and the measured value of the dopant concentration of 1 point is within the concentration range of the region 2. There is no particular problem. As a guide in this case, if 90% or more, more preferably 95% or more of the measurement points are in the range of the region 1, the effect of the present invention can be obtained even if all other measurement points are in the concentration range of the region 2. It does not have a big influence on.
さらに、ドーパント濃度を厚さ方向にプロットすることでドーパント濃度プロファイルが得られるが、領域１から領域３の各領域内におけるドーパント濃度プロファイルの形状は、必ずしも一定のドーパント濃度値を保持した形状を要求するものではなく、例えば、深さ方向に対して、ドーパント濃度値が緩やかに低減または増加する形状でもよく、一旦ドーパント濃度値が上昇後減少に転じるような山なり形状でもよい。 Furthermore, a dopant concentration profile can be obtained by plotting the dopant concentration in the thickness direction, but the shape of the dopant concentration profile in each region from region 1 to region 3 requires a shape that does not necessarily maintain a constant dopant concentration value. For example, a shape in which the dopant concentration value gradually decreases or increases in the depth direction may be used, or a mountain shape in which the dopant concentration value once decreases and then decreases.
次に、各領域について説明する。領域１は、中間層側の一主面の表面から厚さ方向に向かって平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である。 Next, each area will be described. In the region 1, the average dopant concentration is 1 × 10 19 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 or less in the thickness direction from the surface of one main surface on the intermediate layer side.
Ｓｉ基板上に窒化物半導体結晶を成膜する場合、Ｓｉと窒化物半導体との熱膨張係数の違いにより発生する応力起因の基板の反り、窒化物半導体単結晶膜の割れ、さらにはＳｉ基板へのスリップ欠陥の導入といった問題がおこる。特に、デバイス活性層の厚膜化に伴い、応力が増大するので、この応力に対応するだけの臨界せん断応力をもたせるために、Ｓｉ単結晶基板のドーパント濃度を高くする必要がある。 When a nitride semiconductor crystal is formed on a Si substrate, the substrate is warped due to the difference in thermal expansion coefficient between Si and the nitride semiconductor, the nitride semiconductor single crystal film is cracked, and further to the Si substrate. Problems such as the introduction of slip defects occur. In particular, since the stress increases as the device active layer becomes thicker, it is necessary to increase the dopant concentration of the Si single crystal substrate in order to have a critical shear stress corresponding to this stress.
本発明においては、この応力に対応するだけの臨界せん断応力をもたせるのに必要な領域１の平均ドーパント濃度は、１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である。平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３未満では、必要な臨界せん断応力が得られず、一方１×１０２１ａｔｏｍｓ／ｃｍ３を超えると、臨界せん断応力の向上がほとんどみられないことと、ドーパントが過剰に存在することによる偏析や結晶性の悪化が懸念されるので、いずれも好ましくない。 In the present invention, the average dopant concentration in the region 1 necessary for providing a critical shear stress corresponding to this stress is 1 × 10 19 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 or less. If the average dopant concentration is less than 1 × 10 19 atoms / cm 3 , the necessary critical shear stress cannot be obtained, whereas if it exceeds 1 × 10 21 atoms / cm 3 , the improvement of the critical shear stress is hardly observed. , Both of which are unfavorable because there is concern about segregation and deterioration of crystallinity due to the presence of excessive dopant.
遷移領域１は、領域１に続いて基板の深さ方向に形成され、ドーパント濃度が連続的に変化する。図２は、領域１と領域２の間に形成された遷移領域１の、ドーパント濃度プロファイルの一形態を示す概念図である。 The transition region 1 is formed in the depth direction of the substrate subsequent to the region 1, and the dopant concentration continuously changes. FIG. 2 is a conceptual diagram showing one form of the dopant concentration profile of the transition region 1 formed between the region 1 and the region 2.
図３に、本発明に係る遷移領域１のドーパント濃度プロファイルの、他の形態を示す。本発明においては、ドーパント濃度が連続的に変化していれば、ごく短い深さ方向の間で急激に変化するいわゆる階段状の形態でもよい。また、図示しないが、ドーパント濃度の単位深さ方向あたりの減少率が一定である必要もなく、急激に変化したのち緩やかに変化してもよく、その逆でもよい。 FIG. 3 shows another form of the dopant concentration profile in the transition region 1 according to the present invention. In the present invention, as long as the dopant concentration is continuously changed, a so-called step-like form that changes abruptly in a very short depth direction may be used. Further, although not shown, the reduction rate of the dopant concentration per unit depth direction does not need to be constant, and may change gradually after abrupt change, or vice versa.
遷移領域１の深さ方向における厚さは、後述するように、領域１、領域２、領域３のそれぞれの厚さが、化合物半導体の反りや熱伝導率に寄与しているので、これに影響を及ぼさない範囲で薄いほうが好ましい。遷移領域１の制御可能な厚さの範囲は、製造方法により異なるが、最も一般的な表層からの不純物熱拡散法や、不純物濃度の異なる基板の貼り合せ、Ｓｉエピ等の製造方法においては、遷移領域１の深さ方向における厚さは、０．１μｍ以上１００μｍ以下の範囲が好ましいといえる。 As will be described later, the thickness of the transition region 1 in the depth direction is affected by the thickness of each of the regions 1, 2, and 3, which contributes to the warpage and thermal conductivity of the compound semiconductor. It is preferable that the thickness is as small as possible. The range of the controllable thickness of the transition region 1 varies depending on the manufacturing method, but in the most general surface thermal diffusion method from the surface layer, bonding of substrates having different impurity concentrations, manufacturing method such as Si epi, It can be said that the thickness of the transition region 1 in the depth direction is preferably in the range of 0.1 μm to 100 μm.
領域２は、遷移領域１に続いて形成され、平均ドーパント濃度が１×１０１２ａｔｏｍｓ／ｃｍ３以上５×１０１７ａｔｏｍｓ／ｃｍ３以下である。 Region 2 is formed following transition region 1 and has an average dopant concentration of 1 × 10 12 atoms / cm 3 or more and 5 × 10 17 atoms / cm 3 or less.
Ｓｉ単結晶基板の深さ方向全体を、領域１のドーパント濃度にすると、臨界せん断応力は向上するが、高ドーパント濃度のＳｉ単結晶基板は、フォノン散乱の増大により熱伝導率が低くなるため、化合物半導体基板の厚さ方向の熱抵抗も増大する。その結果、この化合物半導体基板上に各種デバイス構造を作製して動作させた場合、動作中のデバイス温度が上昇し、デバイスの寿命や信頼性を低下させてしまう。 When the entire depth direction of the Si single crystal substrate is set to the dopant concentration in the region 1, the critical shear stress is improved. However, the Si single crystal substrate having a high dopant concentration has a low thermal conductivity due to an increase in phonon scattering. The thermal resistance in the thickness direction of the compound semiconductor substrate also increases. As a result, when various device structures are fabricated and operated on this compound semiconductor substrate, the device temperature during operation rises and the lifetime and reliability of the device decrease.
図５は、Ｓｉ単結晶基板の応力と曲げモーメントの関係を示す式と概念図で、これは基板の曲げを簡略化したモデルである。せん断応力は、断面厚さ方向の中立線から一方は引っ張り応力、反対方向には圧縮応力となり、それぞれ基板の表面で最大応力となる。スリップは臨界せん断応力を超えたときに発生するので、基板の表面でスリップが発生する以上のせん断応力を有するドーパント濃度の領域があれば、Ｓｉ単結晶基板の厚さ方向の中心付近はこれより小さいせん断応力を有するドーパント濃度の領域でも、スリップ発生に対する基板の強度に影響はない。 FIG. 5 is an equation and a conceptual diagram showing the relationship between the stress and bending moment of the Si single crystal substrate, which is a model in which the bending of the substrate is simplified. One of the shear stresses is a tensile stress from the neutral line in the cross-sectional thickness direction, and the other is a compressive stress in the opposite direction. Since slip occurs when the critical shear stress is exceeded, if there is a region of dopant concentration having a shear stress higher than that where slip occurs on the surface of the substrate, the vicinity of the center in the thickness direction of the Si single crystal substrate is less than this. Even in the region of the dopant concentration having a small shear stress, the strength of the substrate against the occurrence of slip is not affected.
従って、Ｓｉ単結晶基板の深さ方向において、高ドーパント濃度の層と低ドーパント濃度の層２が適切な割合で存在すれば、臨界せん断応力と熱伝導率のバランスに優れたＳｉ単結晶基板とすることが可能となる。なお、本発明においては、平均ドーパント濃度が１×１０１２ａｔｏｍｓ／ｃｍ３以上という濃度は、実質的にドーパントを含まない、ノンドープのＳｉ単結晶基板の平均ドーパント濃度と同義とする。 Therefore, if a high dopant concentration layer and a low dopant concentration layer 2 are present in an appropriate ratio in the depth direction of the Si single crystal substrate, the Si single crystal substrate having an excellent balance between critical shear stress and thermal conductivity can be obtained. It becomes possible to do. In the present invention, an average dopant concentration of 1 × 10 12 atoms / cm 3 or more is synonymous with an average dopant concentration of a non-doped Si single crystal substrate that does not substantially contain a dopant.
遷移領域２は、領域２に続いて形成されドーパント濃度が連続的に増加する領域であり、次に形成される領域３を接合、区分する役割を有する。基本的には、遷移領域１と構造、作用は同じである。ただし、遷移領域１と遷移領域２とは、完全に同じ構造、すなわち、ドーパント濃度プロファイルの濃度、形状、領域の厚さが一致している必要はない。ドーパント濃度については、本発明の範囲内での差異があってもよく、厚さについても１〜３μｍ程度の差異があってもよい。 The transition region 2 is a region that is formed following the region 2 and in which the dopant concentration continuously increases, and has a role of joining and partitioning the region 3 to be formed next. Basically, the transition region 1 has the same structure and function. However, the transition region 1 and the transition region 2 do not necessarily have the same structure, that is, the concentration, shape, and region thickness of the dopant concentration profile. Regarding the dopant concentration, there may be a difference within the scope of the present invention, and the thickness may be about 1 to 3 μm.
領域３は、遷移領域２に続いて、Ｓｉ単結晶基板の他主面の表面まで形成され、平均ドーパント濃度が１×１０１９ａｔｏｍｓ／ｃｍ３以上１×１０２１ａｔｏｍｓ／ｃｍ３以下である。領域３も、基本的な構造と作用効果は領域１に準じ、Ｓｉ単結晶基板の機械強度を確保する目的で形成される。 The region 3 is formed up to the surface of the other main surface of the Si single crystal substrate following the transition region 2, and has an average dopant concentration of 1 × 10 19 atoms / cm 3 or more and 1 × 10 21 atoms / cm 3 or less. The region 3 is also formed for the purpose of ensuring the mechanical strength of the Si single crystal substrate in conformity with the region 1 in terms of the basic structure and operational effects.
さらに、本発明においては、領域１と領域３のそれぞれの厚さがＳｉ単結晶基板の全体の厚さに対して１５％以上３５％以下の範囲であることを特徴とする。これは、臨界せん断応力に優れる領域１と領域３と、熱伝導率が高い領域２との割合によっては、片方の特性が著しく損なわれる範囲が存在するためである。領域１と領域３のそれぞれの厚さが、１５％未満では機械強度が、３５％超では熱伝導率の低下が、それぞれ影響大となり、いずれも好ましくない。より好ましい範囲としては、２０％以上２５％以下である。図４に各領域とその形態を模式的に表現した概念図を示す。 Furthermore, the present invention is characterized in that the thickness of each of the regions 1 and 3 is in the range of 15% to 35% with respect to the total thickness of the Si single crystal substrate. This is because there is a range in which one of the characteristics is significantly impaired depending on the ratio of the region 1 and the region 3 excellent in critical shear stress and the region 2 having a high thermal conductivity. If the thickness of each of the regions 1 and 3 is less than 15%, the mechanical strength is greater than 35%, and if the thickness exceeds 35%, the decrease in thermal conductivity is significant. A more preferable range is 20% or more and 25% or less. FIG. 4 is a conceptual diagram schematically representing each region and its form.
なお、領域１と領域３は、必ずしもドーパント濃度プロファイル形状と厚さが同一であることを要せず、例えば厚さについては、領域１と領域３のそれぞれの厚さが、本発明の範囲内であればよい。また、目的に応じて、Ｓｉ単結晶基板の裏面側、すなわち化合物半導体層を形成しない側の面に各種の層や膜を形成することも、機械強度と熱伝導率の好ましいバランスを有するという、本発明の効果を損なわない限り、これを排除するものではない。 Note that the regions 1 and 3 do not necessarily have the same thickness as the dopant concentration profile shape. For example, the thicknesses of the regions 1 and 3 are within the scope of the present invention. If it is. In addition, depending on the purpose, forming various layers and films on the back side of the Si single crystal substrate, that is, the side on which the compound semiconductor layer is not formed also has a favorable balance of mechanical strength and thermal conductivity. This is not excluded unless the effects of the present invention are impaired.
本発明においては、ドーパントの種類としては、Ｓｉ単結晶のドーパントとして用いられる各種の元素が適用できるが、基板製造の容易さから、ボロン（Ｂ）、リン（Ｐ）、アンチモン（Ｓｂ）、ヒ素（Ａｓ）、アルミニウム（Ａｌ）、ガリウム（Ｇａ）、ゲルマニウム（Ｇｅ）のうち、いずれか１種類もしくは複数種類を適用することが好ましい。しかしながら、化合物半導体基板への影響を考慮すると、ボロン（Ｂ）、またはヒ素（Ａｓ）を単体で用いることが、より好ましい。 In the present invention, various types of elements used as Si single crystal dopants can be used as the type of dopant, but boron (B), phosphorus (P), antimony (Sb), arsenic are used because of the ease of substrate manufacture. It is preferable to apply one or more of (As), aluminum (Al), gallium (Ga), and germanium (Ge). However, considering the influence on the compound semiconductor substrate, it is more preferable to use boron (B) or arsenic (As) alone.
本発明に係る化合物半導体基板として、中間層およびデバイス活性層を、アルミニウム（Ａｌ）とガリウム（Ｇａ）を含む、具体的には組成ＡｌｘＧａ１−ｘＮ（０≦ｘ≦１）で表される窒化物半導体とすることがさらに好ましい。これらは、Ｓｉ単結晶基板との相性がよく、本発明の構成を適用することで発明の効果が、簡易かつ確実に得られるためである。 As the compound semiconductor substrate according to the present invention, the intermediate layer and the device active layer include aluminum (Al) and gallium (Ga), specifically represented by the composition Al x Ga 1-x N (0 ≦ x ≦ 1). More preferably, the nitride semiconductor is used. These are because the compatibility with the Si single crystal substrate is good, and the effects of the invention can be obtained easily and reliably by applying the configuration of the present invention.
なお、本発明に係るＳｉ単結晶基板は、広く公知の製造方法によって作製される。例えば、低ドーパント濃度のＳｉ単結晶基板上に気相成長法で高ドーパント濃度の層を形成するエピタキシャル法、低ドーパント濃度のＳｉ単結晶基板と高ドーパント濃度のＳｉ単結晶基板を準備しこれらを貼り合せる貼り合せ法、その他イオン打ち込み法などが適用できる。しかしながら、領域１〜３の厚さと遷移領域１，２のドーパント濃度プロファイル形状を、比較的安価かつ精密に制御できる点で、Ｓｉ単結晶基板表層に高ドーパント濃度の層を熱拡散その他の方法で形成し、その後拡散炉等の熱処理装置にて所定の深さ方向までドーパントを熱拡散することで製造される、いわゆる拡散ウェーハが好適に用いられる。 The Si single crystal substrate according to the present invention is manufactured by a widely known manufacturing method. For example, an epitaxial method in which a high dopant concentration layer is formed by vapor deposition on a low dopant concentration Si single crystal substrate, a low dopant concentration Si single crystal substrate and a high dopant concentration Si single crystal substrate are prepared. A bonding method for bonding, an ion implantation method, or the like can be applied. However, the thickness of the regions 1 to 3 and the shape of the dopant concentration profile of the transition regions 1 and 2 can be controlled relatively inexpensively and precisely. A so-called diffusion wafer, which is formed and then manufactured by thermally diffusing the dopant to a predetermined depth in a heat treatment apparatus such as a diffusion furnace, is preferably used.
以上のことから、本発明に係る化合物半導体基板は、化合物半導体基板において重要なスリップなどの欠陥発生防止、基板の反り低減、および基板厚さ方向の熱伝導率低下抑制という効果を、簡易な基板構造で効率的かつバランスよく実現することができ、優れた特性を有する化合物半導体基板を提供することが可能となる。 From the above, the compound semiconductor substrate according to the present invention has the effects of preventing the occurrence of defects such as slips that are important in the compound semiconductor substrate, reducing the warpage of the substrate, and suppressing the decrease in thermal conductivity in the substrate thickness direction. The structure can be realized efficiently and in a balanced manner, and a compound semiconductor substrate having excellent characteristics can be provided.
以下、本発明の好ましい実施形態を実施例に基づき説明するが、本発明はこの実施例により限定されるものではない。 Hereinafter, preferred embodiments of the present invention will be described based on examples, but the present invention is not limited to these examples.
ＣＺ法で製造された、面方位（１１１）、直径４インチ、厚さ６２５μｍ、ノンドープのＳｉ単結晶基板を準備した。そして、ドーパントとしてボロンまたはヒ素を用いて、横型熱処理炉を用いた熱拡散法にて、このＳｉ単結晶基板の両面から、深さ方向に対してドーパントを拡散して領域１と領域３を形成した。そして、ドーパント濃度と各領域の厚さについては表１に示す内容で、各サンプルを作製した。また、領域１（ｔａ）と領域３（ｔｃ）は同じ厚さとし、遷移領域１と遷移領域２の厚さは、ともに７０μｍから１００μｍの範囲とした。 A non-doped Si single crystal substrate manufactured by the CZ method and having a plane orientation (111), a diameter of 4 inches, a thickness of 625 μm was prepared. Then, using boron or arsenic as a dopant, regions 1 and 3 are formed by diffusing the dopant in the depth direction from both sides of the Si single crystal substrate by a thermal diffusion method using a horizontal heat treatment furnace. did. And about the dopant density | concentration and the thickness of each area | region, each sample was produced by the content shown in Table 1. FIG. The region 1 (t a ) and the region 3 (t c ) have the same thickness, and the thicknesses of the transition region 1 and the transition region 2 are both in the range of 70 μm to 100 μm.
次に、この各サンプルに対して、窒化物半導体からなる中間層とデバイス活性層を、気相成長法により堆積することで、窒化物半導体基板を作製した。なお、窒化物半導体の中間層およびデバイス活性層は、図１に示す構成とした。 Next, a nitride semiconductor substrate was fabricated by depositing an intermediate layer made of a nitride semiconductor and a device active layer on each sample by a vapor deposition method. The nitride semiconductor intermediate layer and the device active layer have the structure shown in FIG.
Ｓｉ単結晶基板１をＭＯＣＶＤ装置にセットし、原料としてトリメチルアルミニウム（ＴＭＡ）、およびＮＨ3を用い、１１００℃での気相成長により、厚さ１００ｎｍのＡｌＮ単結晶層２１を形成した。さらにその上に、原料としてトリメチルガリウム（ＴＭＧ）、ＴＭＡおよびＮＨ3を用い、１０００℃での気相成長により、厚さ２００ｎｍのＡｌ０．１Ｇａ０．９Ｎ単結晶層２２を積層させ、この２層を初期バッファ領域とした。 The Si single crystal substrate 1 was set in an MOCVD apparatus, and an AlN single crystal layer 21 having a thickness of 100 nm was formed by vapor phase growth at 1100 ° C. using trimethylaluminum (TMA) and NH 3 as raw materials. Further thereon, trimethylgallium (TMG), TMA and NH 3 are used as raw materials, and an Al 0.1 Ga 0.9 N single crystal layer 22 having a thickness of 200 nm is stacked by vapor phase growth at 1000 ° C. These two layers were used as the initial buffer area.
次に、原料としてＴＭＡおよびＮＨ3を用い、１０００℃での気相成長により、前記初期バッファ領域上に、厚さ５ｎｍのＡｌＮ単結晶層２３を積層させ、続けて厚さ２０ｎｍのＧａＮ単結晶層２４を積層させた。前記ＡｌＮ単結晶層２３およびＧａＮ単結晶層２４を同様の工程にて交互に繰り返し、積層数を５０として、第１の多層バッファ領域２５を形成した。さらに、前記第１の多層バッファ領域２５上に、厚さ５ｎｍのＡｌＮ単結晶層２６および厚さを２５０ｎｍのＧａＮ単結晶層２７を交互に繰り返し積層させ、積層数を２４として、それ以外は、前記第１の多層バッファ領域２５の形成と同様の工程にて、第２の多層バッファ領域２８を形成した。 Next, an AlN single crystal layer 23 having a thickness of 5 nm is laminated on the initial buffer region by vapor phase growth at 1000 ° C. using TMA and NH 3 as raw materials, and then a GaN single crystal having a thickness of 20 nm. Layer 24 was laminated. The AlN single crystal layer 23 and the GaN single crystal layer 24 were alternately repeated in the same process, and the number of stacked layers was set to 50 to form the first multilayer buffer region 25. Furthermore, on the first multilayer buffer region 25, an AlN single crystal layer 26 having a thickness of 5 nm and a GaN single crystal layer 27 having a thickness of 250 nm are alternately stacked repeatedly, and the number of stacks is set to 24. A second multilayer buffer region 28 was formed in the same process as the formation of the first multilayer buffer region 25.
前記第２の多層バッファ領域２８上に、原料としてＴＭＧおよびＮＨ3を用い、１０００℃での気相成長により、厚さ２０００ｎｍのＧａＮ単結晶層３１と、これに続けて、原料としてＴＭＧ、ＴＭＡ、およびＮＨ3を用い、１０００℃での気相成長により、厚さ２０ｎｍのＡｌ０．２５Ｇａ０．７５Ｎ単結晶層３２を積層させて、電子供給層３を形成した。なお、気相成長により形成した各層の厚さは、ガス流量および供給時間の調整により行った。さらに電子供給層３の上にソース、ゲート、ドレインの各電極をＥＢ蒸着により形成することにより、ＨＥＭＴ（High Electron Mobility Transistor；高電子移動度トランジスタ）デバイスを得た。 On the second multilayer buffer region 28, TMG and NH 3 are used as raw materials, and by vapor phase growth at 1000 ° C., a GaN single crystal layer 31 having a thickness of 2000 nm, and subsequently, TMG, TMA as raw materials. The electron supply layer 3 was formed by stacking the Al 0.25 Ga 0.75 N single crystal layer 32 having a thickness of 20 nm by vapor phase growth at 1000 ° C. using NH 3 and NH 3 . Note that the thickness of each layer formed by vapor phase growth was adjusted by adjusting the gas flow rate and the supply time. Further, the source, gate, and drain electrodes were formed on the electron supply layer 3 by EB vapor deposition to obtain a HEMT (High Electron Mobility Transistor) device.
次に作製された窒化物半導体基板について、スリップ発生の有無、および基板厚さ方向の熱伝導率について、それぞれ評価した。 Next, the produced nitride semiconductor substrate was evaluated for the occurrence of slip and the thermal conductivity in the substrate thickness direction.
スリップ発生の有無は、各サンプルのデバイス活性層面を斜光下検査して、目視でスリップが発生しているかどうかを確認した。基準は、目視判断できる範囲で１本でもスリップが確認できた場合は“有り”として
本発明の効果が得られなかったものと評価し、スリップを確認できなかった場合は“無”として本発明の効果があったものと評価した。
For the presence or absence of slip, the device active layer surface of each sample was inspected under oblique light to confirm whether or not slip occurred visually. The criterion is that if even one slip is confirmed within a visually discriminable range, it is evaluated as “present” and the effect of the present invention was not obtained, and if no slip is confirmed, “no” is determined. It was evaluated that there was an effect.
熱伝導性の評価は、ＦＥＴ素子の裏面を同形状のヒートシンクに貼り付け、同一条件でデバイス動作させた際における素子表面の最高温度を非接触のサーモビューワにより測定、比較することで相対評価を行った。各サンプルの、“素子表面の温度がほぼ同等から大幅に減少した”、とする範囲においては、本発明の効果があったものと評価し、増加したものは“増”と表記して、本発明の効果が得られなかったものと評価した。 Evaluation of thermal conductivity is performed by pasting the back surface of the FET element on a heat sink of the same shape, and measuring and comparing the maximum temperature of the element surface with a non-contact thermo viewer when the device is operated under the same conditions. went. Each sample was evaluated as having the effect of the present invention within the range that “the temperature of the element surface was substantially reduced from substantially the same”, and the increased was described as “increase”. It was evaluated that the effects of the invention could not be obtained.
以上のようにした、各サンプルの作製条件と評価結果を、表１に示す。 Table 1 shows the production conditions and evaluation results of each sample as described above.
表１の結果から、本発明の実施範囲においては、スリップの発生がなく、かつ各サンプルの裏面側の温度がほぼ同等か減少しており、本発明の効果が得られていた。一方、本発明の実施範囲を一部または全部外れた場合は、スリップまたは各サンプルの裏面側の温度の項目で少なくともいずれか一つについて、本発明の効果が得られていなかった。さらに、ドーパントがボロンとヒ素の場合でも、特に有意差はなく、本発明の効果が同様に確認された。 From the results of Table 1, in the implementation range of the present invention, there was no occurrence of slip, and the temperature on the back side of each sample was almost equal or decreased, and the effect of the present invention was obtained. On the other hand, when a part or all of the implementation range of the present invention was deviated, the effect of the present invention was not obtained for at least one of the items of slip or temperature on the back side of each sample. Further, even when the dopant is boron and arsenic, there is no significant difference, and the effect of the present invention was confirmed in the same manner.
本発明は、発光ダイオード、レーザ発光素子、また、高速・高温での動作可能な電子素子等に好適に用いられるＨＥＭＴ（High Electron Mobility Transistor；高電子移動度トランジスタ）構造を有する窒化物半導体基板として好適である。 The present invention is a nitride semiconductor substrate having a HEMT (High Electron Mobility Transistor) structure suitably used for a light emitting diode, a laser light emitting element, an electronic element operable at a high speed and a high temperature, and the like. Is preferred.
1…Ｓｉ単結晶基板、11…領域３、12…領域２、13…領域１、14…遷移領域２、15…遷移領域１、2…中間層、21…ＡｌＮ単結晶層２１、22…Ａｌ０．１Ｇａ０．９Ｎ単結晶層２２、23…ＡｌＮ単結晶層、24…ＧａＮ単結晶層、25…第１の多層バッファ領域、26…ＡｌＮ単結晶層、27…ＧａＮ単結晶層、28…第２の多層バッファ領域、3…デバイス活性層、31…ＧａＮ単結晶層、32…Ａｌ０．２５Ｇａ０．７５Ｎ単結晶層。 1 ... Si single crystal substrate, 11 ... region 3, 12 ... region 2, 13 ... region 1, 14 ... transition region 2, 15 ... transition region 1, 2 ... intermediate layer, 21 ... AlN single crystal layer 21, 22 ... Al 0.1 Ga 0.9 N single crystal layer 22, 23 ... AlN single crystal layer, 24 ... GaN single crystal layer, 25 ... first multilayer buffer region, 26 ... AlN single crystal layer, 27 ... GaN single crystal layer, 28 ... second multilayer buffer region, 3 ... device active layer, 31 ... GaN single crystal layer, 32 ... Al 0.25 Ga 0.75 N single crystal layer.
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| JP2014236093A (en) * | 2013-05-31 | 2014-12-15 | サンケン電気株式会社 | Silicon-based substrate, semiconductor device and method for manufacturing semiconductor device |
| WO2015111915A1 (en) | 2014-01-22 | 2015-07-30 | 엘지전자 주식회사 | Method for performing power control, and user equipment |
| EP4092719A1 (en) | 2015-03-31 | 2022-11-23 | SweGaN AB | Heterostructure and method of its production |
| JP2023080538A (en) * | 2021-11-30 | 2023-06-09 | 信越半導体株式会社 | Nitride semiconductor substrate and method for manufacturing the same |
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| JPH11251322A (en) * | 1998-02-27 | 1999-09-17 | Sony Corp | Epitaxial silicon substrate, solid-state image pickup device and manufacture thereof |
| JP2003218031A (en) * | 2002-01-28 | 2003-07-31 | Toshiba Ceramics Co Ltd | Method of manufacturing semiconductor wafer |
| KR101319512B1 (en) * | 2005-05-02 | 2013-10-21 | 니치아 카가쿠 고교 가부시키가이샤 | Nitride based semiconductor element and method for fabricating the same |
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| JP2009224722A (en) * | 2008-03-18 | 2009-10-01 | Covalent Materials Corp | Compound semiconductor board |
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