JP2015060883A - Compound semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable compound semiconductor device which inhibits the occurrence of a crack by decreasing a film thickness of a buffer layer and enables improvement of crystallinity by increasing a film thickness of a nitride semiconductor layer.SOLUTION: An AlGaN/GaN HEMT comprises: an Si substrate 1 having a first uneven surface; a second nitride film 2b which is formed on the Si substrate 1 via a first nitride film 2a and has a surface reflecting the first uneven surface; a buffer layer 3 which is formed on the second nitride film 2b and has a second uneven surface due to lateral crystal growth caused by a surface shape of the second nitride film 2b; and an electron transit layer 4a which is formed on the buffer layer 3 and composed of GaN crystal.

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  Compound semiconductor devices, particularly nitride semiconductor devices, have been actively developed as high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. As nitride semiconductor devices, many reports have been made on field effect transistors, in particular, high electron mobility transistors (HEMTs). In particular, AlGaN / GaN HEMTs using GaN as an electron transit layer and AlGaN as an electron supply layer are attracting attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, high breakdown voltage and high output can be realized.

  In growing GaN crystals, there is no suitable substrate with a matching lattice constant, and sapphire or SiC substrates are often used, but these are expensive and rare. In this respect, the Si substrate is inexpensive and highly versatile. However, since the Si substrate has a large lattice constant difference from GaN, many crystal defects are generated in the grown GaN. In addition, the reaction between Ga and Si causes so-called meltback etching on the Si substrate, and the crystallinity of GaN is significantly impaired. For this reason, when growing GaN on a Si substrate, it is known to form AlN as both buffer layers.

Japanese Patent Laid-Open No. 2002-11069 JP 2002-249400 A JP 2003-257879 A JP 2011-66390 A JP-A-11-265853

  In order to suppress the reaction between Ga and Si, it is necessary to form the buffer layer thick in order to give the AlN buffer layer a sufficient function. However, as the buffer layer is thickened, the generation of cracks due to strain due to the difference in lattice constant between AlN and Si is induced. Many crystal defects occur in the GaN nitride semiconductor layer grown on the buffer layer with many cracks, and the quality of GaN is greatly impaired. Further, since a large tensile stress is already applied to the Si substrate before the GaN is grown due to the thickening of the buffer layer, the Si substrate is destroyed if the nitride semiconductor layer is further grown thick. For this reason, it is necessary to reduce the thickness of the nitride semiconductor layer. However, if the nitride semiconductor layer is thinned, the crystallinity of GaN deteriorates.

  The present invention has been made in view of the above-described problems, and is capable of reducing the occurrence of cracks by reducing the thickness of the buffer layer and increasing the crystallinity by increasing the thickness of the nitride semiconductor layer. An object of the present invention is to provide a compound semiconductor device having a high level and a method for manufacturing the same.

  One embodiment of a semiconductor device includes a substrate having a first uneven surface, a nitride film formed on the substrate and having a surface reflecting the first uneven surface, and formed on the nitride film, the nitride A buffer layer having a second concavo-convex surface formed by lateral crystal growth caused by the surface shape of the film; and a crystalline nitride semiconductor layer formed on the buffer layer.

  One embodiment of a method for manufacturing a semiconductor device includes a step of forming a first uneven surface on a substrate, and a step of forming a nitride film on the substrate so as to have a surface shape reflecting the first uneven surface; A step of forming a buffer layer having a second irregular surface by laterally growing a crystal on the nitride film due to a surface shape of the nitride film; and a crystalline nitride semiconductor on the buffer layer Forming a layer.

  According to the above-described aspects, a highly reliable compound semiconductor device that can reduce the occurrence of cracks by reducing the thickness of the buffer layer and increase the crystallinity by increasing the thickness of the nitride semiconductor layer is realized. .

It is a schematic sectional drawing which shows the manufacturing method of AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 3. It is a schematic perspective view which shows the 1st uneven | corrugated surface formed in Si substrate. It is a schematic sectional drawing which shows the formation state (formation process) of a buffer layer and an electron transit layer. It is a connection diagram which shows schematic structure of the power supply device by 2nd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 3rd Embodiment.

(First embodiment)
In the present embodiment, a nitride semiconductor AlGaN / GaN.HEMT that is a compound semiconductor is disclosed as a semiconductor device.
1 to 4 are schematic cross-sectional views showing the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps.

As shown in FIG. 1A, for example, a Si substrate 1 is prepared as a growth substrate, and irregularities are formed on the surface of the Si substrate 1.
In this embodiment, the Si substrate 1 which is an inexpensive and highly versatile substrate is used as the growth substrate. Instead of the Si substrate 1, for example, a semi-insulating SiC substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used. Further, the conductivity of the substrate may be semi-insulating or conductive.

  The surface of the Si substrate 1 is processed by lithography and reactive ion etching (RIE) to form an uneven surface. Specifically, as shown in FIG. 5A, a plurality of grooves 1a having forward tapered inclination angles are formed on the surface of the Si substrate 1 in stripes parallel to each other. By forming a plurality of grooves 1 a on the surface of the Si substrate 1, the surface becomes uneven (first uneven surface). On the first uneven surface, the width L1 of the groove 1a is about 0.1 μm to 10 μm, the width L2 of the convex portion 1b formed by the groove 1a is about 0.5 μm to 20 μm, and the depth D of the groove 1a is 0. The inclination angle θ of the groove 1a is an acute angle of about 25 ° or more. More preferably, the width L1 is about 1 μm to about 3 μm, the width L2 is about 5 μm to about 10 μm, D is about 0.5 μm to about 1 μm, and the inclination angle θ is about 45 ° to about 60 °.

The first uneven surface of the Si substrate 1 may be realized by forming a pattern as shown in FIGS. 5B and 5C instead of forming the groove 1a.
In FIG. 5B, a plurality of grooves 1c having inversely tapered inclination angles are formed on the surface of the Si substrate 1 in stripes parallel to each other. By forming the plurality of grooves 1 c on the surface of the Si substrate 1, the surface becomes uneven (first uneven surface). On the first uneven surface, the inclination angle θ of the groove 1c is an obtuse angle of about 155 ° or less.

  In FIG. 5C, dots 1 d having a flat upper surface are formed on the surface of the Si substrate 1. By forming a plurality of dots 1d on the surface of the Si substrate 1, the surface becomes uneven (first uneven surface). Unlike the concave portions of the grooves 1a and 1c (or the convex portions formed by the grooves 1a and 1c), the dot 1d does not have a specific directionality. Therefore, during the lateral growth of GaN, which becomes an electron transit layer, which will be described later, symmetrical and uniform lateral growth of GaN having no directivity is obtained as a whole around each dot 1d. Further reduction is realized.

  Subsequently, as shown in FIGS. 1B to 2C, a first nitride film 2a, a second nitride film 2b, and a compound semiconductor multilayer structure 3 are formed. The first nitride film 2a, the second nitride film 2b, and the compound semiconductor stacked structure 3 are formed in a series of in situ in the reaction chamber of the MOCVD apparatus, for example, by metal organic chemical vapor deposition (MOCVD). Formed in the process. Process reduction is realized by a series of in situ processes. Instead of the MOCVD method, a molecular beam epitaxy (MBE) method or the like may be used.

First, as shown in FIG. 1B, a first nitride film 2 a is formed on the surface of the Si substrate 1.
Specifically, the surface of the Si substrate 1 is subjected to thermal nitridation in the reaction chamber of the MOCVD apparatus. As conditions for thermal nitriding, for example, the pressure is about 5 kPa to about 10 kPa, the flow rate of NH ₃ is about 1 slm to about 50 slm, and the annealing temperature is about 1000 ° C. to about 1300 ° C. By this heat treatment, a thin first nitride film 2 a having a surface reflecting the first uneven surface is formed on the entire surface of the Si substrate 1. The first nitride film 2a is thinly formed to a thickness within about 3 nm, for example. When the first nitride film 2a is formed thicker than about 3 nm, there is a concern that the surface morphology is deteriorated. For example, the first nitride film 2a having a good surface morphology can be obtained by forming the thickness within about 3 nm.

Next, as shown in FIG. 1C, a second nitride film 2b is formed on the first nitride film 2a.
Specifically, in the reaction chamber of the MOCVD apparatus, following the formation of the first nitride film 2a, SiN is epitaxially grown using SiH ₄ gas as a source gas. The epitaxial growth conditions are, for example, a pressure of about 5 kPa to about 10 kPa, a flow rate of SiH ₄ of about 50 sccm to about 300 sccm, a flow rate of NH ₃ of about 1 slm to about 50 slm, and a growth temperature of about 800 ° C. to about 1100 ° C. By this epitaxial growth, a second nitride film 2b having a surface reflecting the first uneven surface of the Si substrate 1 is formed on the entire surface of the first nitride film 2a. The second nitride film 2b is thicker than the first nitride film 2a, and is formed to a thickness of about 5 nm to 50 nm, for example. If the thickness of the second nitride film 2b is less than about 5 nm, the Si diffusion preventing effect of the Si substrate 1 described later is not sufficient. If the thickness of the second nitride film 2b is more than about 50 nm, the effect of improving the quality by the annealing process in the next process is sufficient. I can't get it. For example, by forming the film to a thickness of about 5 nm to about 50 nm, the second nitride film 2b having a high quality and a sufficient Si diffusion preventing function for the Si substrate 1 can be obtained. The nitride film 2 is configured as a stacked structure of the first nitride film 2a and the second nitride film 2b.

Next, as shown in FIG. 2A, the second nitride film 2b is annealed.
Specifically, the second nitride film 2b is annealed in the reaction chamber of the MOCVD apparatus following the formation of the second nitride film 2b. As conditions for the annealing treatment, for example, the pressure is about 5 kPa to about 10 kPa, the flow rate of NH ₃ is about 1 slm to about 50 slm, the annealing temperature is about 1000 ° C. to about 1300 ° C., and the annealing time is about 10 minutes to about 60 minutes. . By this annealing treatment, the second nitride film 2b has improved SiN crystallinity and high quality.

Next, as shown in FIG. 2B, the buffer layer 3 is formed.
Specifically, AlN is epitaxially grown on the second nitride film 2b following the annealing process of the second nitride film 2b in the reaction chamber of the MOCVD apparatus. Epitaxial growth conditions include, for example, a pressure of about 5 kPa to about 10 kPa, a flow rate of NH ₃ of about 1 slm to about 50 slm, a growth temperature of about 1000 ° C. to about 1300 ° C., and an appropriate flow rate of trimethylaluminum (TMAl) gas. . This epitaxial growth is based on a so-called ELO (Epitaxially Lateral Overgrowth) method. By this ELO method, due to the surface shape of the second nitride film 2b, AlN is preferential in the direction (lateral direction) parallel (not perpendicular) to the surface direction of the Si substrate 1 over the perpendicular direction. Crystal growth. Thereby, the buffer layer 3 is formed.

  The formation state of the buffer layer 3 is illustrated in FIG. The dislocation defect A1 caused by the lattice constant difference with the SiN of the second nitride film 2b of AlN is bent from the vertical direction to the horizontal direction. Due to the bending of the dislocation defect A1, the propagation of the dislocation defect A1 in the vertical direction to GaN, which will be described later, formed on the buffer layer 3 is suppressed. As a result, the buffer layer 3 having an uneven surface (second uneven surface) is formed on the second nitride film 2b. The buffer layer 3 is relatively thin and is formed to have a maximum thickness of about 0.01 μm to 0.5 μm. In the present embodiment, the generation of cracks in the buffer layer 3 is suppressed by forming the buffer layer 3 relatively thin. The buffer layer 3 has a low crack and a second uneven surface, and becomes a high-quality template excellent in crystallinity for growing GaN as an electron transit layer thereon.

Next, as illustrated in FIG. 2C, the compound semiconductor multilayer structure 4 is formed on the buffer layer 3.
The compound semiconductor multilayer structure 4 includes an electron transit layer 4a, a spacer layer 4b, an electron supply layer 4c, and a cap layer 4d.
Specifically, in the reaction chamber of the MOCVD apparatus, for example, i (intentional undoped) -GaN is relatively thick on the buffer layer 3, for example, about 0.5 μm to 3.0 μm, here about 1.0 μm. Grow to a thickness of. Subsequently, for example, i-AlGaN is grown to a thickness of about 5 nm, n-AlGaN is grown to a thickness of about 30 nm, and n-GaN is grown to a thickness of about 10 nm, for example. Thereby, the electron transit layer 4a, the spacer layer 4b, the electron supply layer 4c, and the cap layer 4d are formed.

As a growth condition for GaN, a mixed gas of trimethylgallium (TMGa) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMGa gas as a Ga source and TMAl gas as an Al source are appropriately set according to the compound semiconductor layer to be grown.

When growing AlGaN and GaN as n-type, that is, when forming the electron supply layer 4c and the cap layer 4d, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, GaN and AlGaN are doped with Si. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

First, when growing GaN of the electron transit layer 4a on the buffer layer 3, the epitaxial growth conditions are, for example, a pressure of about 5 kPa to about 80 kPa, a flow rate of NH ₃ of about 1 slm to about 50 slm, and a growth temperature. Is about 900 ° C. to 1200 ° C., and the flow rate of the TMAl gas is appropriately adjusted. This epitaxial growth is based on the ELO method.

  The formation process of the electron transit layer 4a is illustrated in FIGS. 6 (b) and 6 (c). By this ELO method, GaN grows in the lateral direction using the buffer layer 3 having the second uneven surface as a template. Therefore, the transition defect A1 of the buffer layer 3 propagates in the lateral direction almost as a transition defect A2 in GaN, and the vertical direction. Propagation to is suppressed. Near the surface of GaN grown to a predetermined thickness, the number of transition defects A2 is extremely small, and the dislocation density is reduced. Thus, the generation of crystal defects is suppressed as much as possible, and the electron transit layer 4a made of high quality GaN having excellent crystallinity is formed.

  In the present embodiment, the second nitride film 2b having high crystallinity is formed on the Si substrate 1 via the first nitride film 2a, so that the effect of suppressing Si diffusion from the Si substrate 1 is increased, and the buffer The layer 3 can be thinned. As a result, the generation of cracks in the buffer layer 3 is suppressed, and the quality of the GaN crystals of the electron transit layer 4a grown thereon is improved. In addition, since the strain before GaN is grown is reduced, it is possible to increase the film thickness of GaN and improve the crystallinity of GaN.

  Further, AlN of the buffer layer 3 is grown by the ELO method, the dislocation defect is bent upward, and the surface is made uneven. As a result, dislocation defects of GaN in the electron transit layer 4a grown on the buffer layer 3 are further bent, dislocation propagation upward is effectively suppressed, and high quality of GaN can be achieved.

  In the completed AlGaN / GaN HEMT, during its operation, a two-dimensional electron gas is present in the vicinity of the interface between the electron transit layer 4a and the electron supply layer 4c (more precisely, in the vicinity of the interface between the electron transit layer 4a and the spacer layer 4b). (2DEG) occurs. The 2DEG is generated based on a difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 4a and the compound semiconductor (here, AlGaN) of the electron supply layer 4c.

Subsequently, as shown in FIG. 3A, an element isolation structure 5 is formed.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor multilayer structure 4. Thereby, the element isolation structure 5 is formed in the compound semiconductor multilayer structure 4. An active region is defined on the compound semiconductor stacked structure 2 by the element isolation structure 5.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor multilayer structure 4.

Subsequently, as shown in FIG. 3B, a source electrode 6 and a drain electrode 7 are formed.
Specifically, first, electrode recesses 4 </ b> A and 4 </ b> B are formed at the planned formation positions (electrode formation planned positions) of the source electrode and the drain electrode on the surface of the compound semiconductor multilayer structure 4.
A resist is applied to the surface of the compound semiconductor multilayer structure 4. The resist is processed by lithography, and an opening exposing the surface of the compound semiconductor multilayer structure 4 corresponding to the electrode formation planned position is formed in the resist. Thus, a resist mask having the opening is formed.

Using this resist mask, the electrode formation planned position of the cap layer 4d is removed by dry etching until the surface of the electron supply layer 4c is exposed. As a result, electrode recesses 4A and 4B that expose the electrode formation scheduled positions on the surface of the electron supply layer 4c are formed. As an etching condition, using a chlorine-based gas of the inert gas and Cl ₂ and the like such as Ar as an etching gas, for example, Cl ₂ flow rate 30 sccm, 2 Pa pressure, the RF input power and 20W. The electrode recesses 4A and 4B may be formed by etching halfway through the cap layer 4d, or may be formed by etching up to and after the electron supply layer 4c.
The resist mask is removed by ashing or the like.

A resist mask for forming the source electrode and the drain electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied on the compound semiconductor multilayer structure 4 to form openings for exposing the electrode recesses 4A and 4B. Thus, a resist mask having the opening is formed.
Using this resist mask, as an electrode material, for example, Ta / Al (Ta is the lower layer, Al is the upper layer, or Ti / Al, etc.), including the inside of the opening exposing the electrode recesses 4A and 4B, for example, by vapor deposition Deposit on resist mask. The thickness of Ta is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ta / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated in a nitrogen atmosphere at a temperature of about 400 ° C. to 1000 ° C., for example, about 600 ° C., and the remaining Ta / Al is brought into ohmic contact with the electron supply layer 4c. If ohmic contact with the Ta / Al electron supply layer 4c is obtained, heat treatment may be unnecessary. In this way, the source electrode 6 and the drain electrode 7 are formed in which the electrode recesses 4A and 4B are embedded with part of the electrode material.

Subsequently, as shown in FIG. 3C, an electrode recess 4 </ b> C for the gate electrode is formed in the compound semiconductor multilayer structure 4.
Specifically, first, a resist is applied to the surface of the compound semiconductor multilayer structure 4. The resist is processed by lithography to form an opening in the resist that exposes the surface of the compound semiconductor multilayer structure 4 corresponding to the gate electrode formation planned position (electrode formation planned position). Thus, a resist mask having the opening is formed.

Using this resist mask, parts of the cap layer 4d and the electron supply layer 4c at the electrode formation scheduled position are removed by dry etching. As a result, an electrode recess 4C is formed that is dug up to a part of the cap layer 4d and the electron supply layer 4c. As an etching condition, using a chlorine-based gas of the inert gas and Cl ₂ and the like such as Ar as an etching gas, for example, Cl ₂ flow rate 30 sccm, 2 Pa pressure, the RF input power and 20W. The electrode recess 4C may be formed by etching partway through the cap layer 4d, or may be formed by etching up to a location deeper than the electron supply layer 4c.
The resist mask is removed by ashing or the like.

Subsequently, as shown in FIG. 4A, a gate insulating film 8 is formed.
Specifically, for example, Al ₂ O ₃ is deposited as an insulating material on the compound semiconductor multilayer structure 4 so as to cover the inner wall surface of the electrode recess 4C. Al ₂ O ₃ is deposited to a film thickness of about 2 nm to about 200 nm, here about 10 nm, for example, by atomic layer deposition (ALD method). Thereby, the gate insulating film 8 is formed.

Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

Subsequently, as shown in FIG. 4B, a gate electrode 9 is formed.
Specifically, first, a resist mask for forming the gate electrode is formed. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. This resist is applied on the gate insulating film 8 to form openings that expose the electrode recesses 4 </ b> C of the gate insulating film 8. Thus, a resist mask having the opening is formed.

  Using this resist mask, for example, Ni / Au is deposited as an electrode material on the resist mask including the inside of the opening exposing the electrode recess 4C of the gate insulating film 8 by, for example, vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. As described above, the gate electrode 9 is formed in which the electrode recess 4C is filled with part of the electrode material via the gate insulating film 8.

In the present embodiment, an MIS type AlGaN / GaN.HEMT having the gate insulating film 8 is exemplified, but the Schottky that does not have the gate insulating film 8 and the gate electrode 9 is in direct contact with the compound semiconductor multilayer structure 4. A type of AlGaN / GaN HEMT may be fabricated.
Further, without adopting a gate recess structure in which the gate electrode 9 is formed in the electrode recess 4C, a gate electrode is formed on the compound semiconductor multilayer structure 4 without recess through a gate insulating film or directly. May be.

  Thereafter, through various steps such as formation of an interlayer insulating film, formation of wiring connected to the source electrode 6, drain electrode 7, and gate electrode 9, formation of an upper protective film, formation of a connection electrode exposed on the outermost surface, and the like. The AlGaN / GaN HEMT according to the present embodiment is formed.

  As described above, in the present embodiment, the buffer layer 3 is thinned to suppress the generation of cracks, and the electron transit layer 4a is thickened to improve the crystallinity thereof. AlGaN / GaN HEMT is realized.

(Second Embodiment)
In the present embodiment, a power supply device to which the AlGaN / GaN HEMT according to the first embodiment is applied is disclosed.
FIG. 7 is a connection diagram illustrating a schematic configuration of the power supply device according to the second embodiment.

The power supply apparatus according to the present embodiment includes a high-voltage primary circuit 11 and a low-voltage secondary circuit 12, and a transformer 13 disposed between the primary circuit 11 and the secondary circuit 12. The
The primary side circuit 11 includes an AC power supply 14, a so-called bridge rectifier circuit 15, and a plurality (four in this case) of switching elements 16a, 16b, 16c, and 16d. The bridge rectifier circuit 15 includes a switching element 16e.
The secondary side circuit 42 includes a plurality of (here, three) switching elements 17a, 17b, and 17c.

  In the present embodiment, the switching elements 16a, 16b, 16c, 16d, and 16e of the primary side circuit 11 are the AlGaN / GaN HEMT according to the first embodiment. On the other hand, the switching elements 17a, 17b, and 17c of the secondary circuit 12 are normal MIS • FETs using silicon.

  In this embodiment, a highly reliable high withstand voltage AlGaN / GaN HEMT that can reduce the occurrence of cracks by reducing the thickness of the buffer layer and increase the crystallinity of the nitride semiconductor layer by increasing the thickness of the nitride semiconductor layer. Apply to high voltage circuit. As a result, a highly reliable high-power power supply circuit is realized.

(Third embodiment)
In the present embodiment, a high frequency amplifier to which the AlGaN / GaN HEMT of the first embodiment is applied is disclosed.
FIG. 8 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the third embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 21, mixers 22 a and 22 b, and a power amplifier 23.
The digital predistortion circuit 21 compensates for nonlinear distortion of the input signal. The mixer 22a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 23 amplifies the input signal mixed with the AC signal, and has the AlGaN / GaN HEMT of the first embodiment. In FIG. 8, for example, by switching the switch, the output side signal is mixed with the AC signal by the mixer 22b and sent to the digital predistortion circuit 21.

  In this embodiment, a highly reliable high withstand voltage AlGaN / GaN HEMT that can reduce the occurrence of cracks by reducing the thickness of the buffer layer and increase the crystallinity of the nitride semiconductor layer by increasing the thickness of the nitride semiconductor layer. Applicable to high frequency amplifiers. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to third embodiments described above, the AlGaN / GaN.HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other HEMT examples 1
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first embodiment described above, the electron transit layer is formed of i-GaN, the spacer layer is formed of i-AlN, the electron supply layer is formed of n-InAlN, and the cap layer is formed of n-GaN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by spontaneous polarization of InAlN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, the buffer layer is thinned to suppress the generation of cracks, and the electron transit layer is thickened to improve the crystallinity. And high withstand voltage InAlN / GaN.HEMT.

・ Other HEMT examples 2
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first embodiment described above, the electron transit layer is formed of i-GaN, the spacer layer is formed of i-AlN, the electron supply layer is formed of n-InAlGaN, and the cap layer is formed of n-GaN.

  According to this example, similarly to the AlGaN / GaN HEMT described above, the buffer layer is thinned to suppress the generation of cracks, and the electron transit layer is thickened to improve the crystallinity. And high withstand voltage InAlGaN / GaN HEMT.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Appendix 1)
A substrate having a first irregular surface;
A nitride film formed on the substrate and having a surface reflecting the first uneven surface;
A buffer layer formed on the nitride film and having a second concavo-convex surface by lateral crystal growth caused by a surface shape of the nitride film;
A compound semiconductor device comprising: a crystalline nitride semiconductor layer formed on the buffer layer.

  (Supplementary Note 2) The nitride film includes a first nitride film formed on the substrate and a second nitride film formed on the first nitride film to be thicker than the first nitride film. The compound semiconductor device according to appendix 1, wherein the compound semiconductor device is provided.

  (Supplementary note 3) The compound semiconductor device according to supplementary note 2, wherein the first nitride film is a thermal nitride film, and the second nitride film is an epitaxial growth film.

  (Supplementary note 4) The compound semiconductor device according to supplementary note 3, wherein the first nitride film is formed with a thickness of 3 nm or less, and the second nitride film is formed with a thickness of 5 nm or more and 50 nm or less. .

  (Supplementary note 5) The compound semiconductor device according to any one of supplementary notes 1 to 4, wherein the substrate has the first uneven surface formed by a plurality of stripe-shaped grooves.

  (Supplementary note 6) The compound semiconductor device according to supplementary note 5, wherein the groove is formed to have a forward tapered inclination angle.

  (Supplementary note 7) The compound semiconductor device according to supplementary note 5, wherein the groove is formed to have a reverse tapered inclination angle.

  (Appendix 8) The compound semiconductor device according to any one of appendices 1 to 4, wherein the substrate has the first uneven surface formed by dots having a flat upper surface.

(Additional remark 9) The process of forming the 1st uneven surface on a board | substrate,
Forming a nitride film on the substrate so as to have a surface shape reflecting the first uneven surface;
Forming a buffer layer having a second concavo-convex surface by laterally crystal growth on the nitride film due to the surface shape of the nitride film;
Forming a crystalline nitride semiconductor layer on the buffer layer. A method for manufacturing a compound semiconductor device.

  (Supplementary Note 10) The nitride film includes a first nitride film formed on the substrate and a second nitride film formed thicker than the first nitride film on the first nitride film. The method for manufacturing a compound semiconductor device according to appendix 9, characterized by comprising:

  (Supplementary note 11) The method of manufacturing a compound semiconductor device according to supplementary note 10, wherein the first nitride film is formed by a thermal nitridation method, and the second nitride film is formed by an epitaxial growth method.

  (Supplementary note 12) The compound semiconductor device according to Supplementary note 11, wherein the first nitride film is formed with a thickness of 3 nm or less, and the second nitride film is formed with a thickness of 5 nm or more and 50 nm or less. Production method.

  (Supplementary note 13) The method of manufacturing a compound semiconductor device according to supplementary note 11 or 12, wherein the second nitride film is annealed after epitaxially growing the second nitride film.

  (Appendix 14) The method for manufacturing a compound semiconductor device according to any one of appendices 9 to 13, wherein the substrate has the first uneven surface formed by a plurality of stripe-shaped grooves.

  (Additional remark 15) The said groove | channel is formed in the forward taper-shaped inclination angle, The manufacturing method of the compound semiconductor device of Additional remark 14 characterized by the above-mentioned.

  (Additional remark 16) The said groove | channel is formed in the reverse taper-shaped inclination angle, The manufacturing method of the compound semiconductor device of Additional remark 14 characterized by the above-mentioned.

  (Supplementary note 17) The method for manufacturing a compound semiconductor device according to any one of supplementary notes 9 to 13, wherein the first uneven surface of the substrate is formed by dots having a flat upper surface.

(Supplementary note 18) A power supply circuit comprising a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A substrate having a first irregular surface;
A nitride film formed on the substrate and having a surface reflecting the first uneven surface;
A buffer layer formed on the nitride film and having a second concavo-convex surface by lateral crystal growth caused by a surface shape of the nitride film;
A power supply circuit comprising: a crystalline nitride semiconductor layer formed on the buffer layer.

(Supplementary note 19) A high-frequency amplifier that amplifies and outputs an input high-frequency voltage,
Has a transistor,
The transistor is
A substrate having a first irregular surface;
A nitride film formed on the substrate and having a surface reflecting the first uneven surface;
A buffer layer formed on the nitride film and having a second concavo-convex surface by lateral crystal growth caused by a surface shape of the nitride film;
A high frequency amplifier comprising: a crystalline nitride semiconductor layer formed on the buffer layer.

DESCRIPTION OF SYMBOLS 1 Si substrate 1a, 1c Groove 1b Protrusion part 1d Dot 2 Nitride film 2a 1st nitride film 2b 2nd nitride film 4A, 4B, 4C Recess for electrodes 3 Buffer layer 4 Compound semiconductor laminated structure 4a Electron travel layer 4b Spacer layer 4c Electron supply layer 4d Cap layer 5 Element isolation region 6 Source electrode 7 Drain electrode 8 Gate insulating film 9 Gate electrode 11 Primary side circuit 12 Secondary side circuit 13 Transformer 14 AC power supply 15 Bridge rectifier circuits 16a, 16b, 16c, 16d, 16e, 17a, 17b, 17c Switching element 21 Digital predistortion circuit 22a, 22b Mixer 23 Power amplifier

Claims (8)

A substrate having a first irregular surface;
A nitride film formed on the substrate and having a surface reflecting the first uneven surface;
A buffer layer formed on the nitride film and having a second concavo-convex surface by lateral crystal growth caused by a surface shape of the nitride film;
A compound semiconductor device comprising: a crystalline nitride semiconductor layer formed on the buffer layer.   The nitride film includes a first nitride film formed on the substrate, and a second nitride film formed thicker than the first nitride film on the first nitride film. The compound semiconductor device according to claim 1.   The compound semiconductor device according to claim 2, wherein the first nitride film is a thermal nitride film, and the second nitride film is an epitaxial growth film.   4. The compound semiconductor device according to claim 1, wherein the substrate has the first uneven surface formed by a plurality of stripe-shaped grooves. 5.   The compound semiconductor device according to claim 1, wherein the first uneven surface of the substrate is formed by dots having a flat upper surface. Forming a first uneven surface on the substrate;
Forming a nitride film on the substrate so as to have a surface shape reflecting the first uneven surface;
Forming a buffer layer having a second concavo-convex surface by laterally crystal growth on the nitride film due to the surface shape of the nitride film;
Forming a crystalline nitride semiconductor layer on the buffer layer. A method for manufacturing a compound semiconductor device.   The nitride film includes a first nitride film formed on the substrate, and a second nitride film formed thicker than the first nitride film on the first nitride film. A method for manufacturing a compound semiconductor device according to claim 6.   8. The method of manufacturing a compound semiconductor device according to claim 7, wherein the first nitride film is formed by a thermal nitridation method, and the second nitride film is formed by an epitaxial growth method.

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