KR20140036717A

KR20140036717A - Light emitting device

Info

Publication number: KR20140036717A
Application number: KR1020120103160A
Authority: KR
Inventors: 최운경; 이은득
Original assignee: 엘지이노텍 주식회사
Priority date: 2012-09-18
Filing date: 2012-09-18
Publication date: 2014-03-26

Abstract

The light emitting device according to the embodiment, the light transmitting substrate having a constant thickness; A first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and disposed between the first conductive semiconductor layer and the second conductive semiconductor layer A light emitting structure including an active layer; A first electrode disposed on the first conductive semiconductor layer and a second electrode disposed on the second conductive semiconductor layer; A first electrode pad electrically connected to the first electrode and a second electrode pad electrically connected to the second electrode; And a semi-insulated submount substrate on which the first and second electrode pads are disposed, the area of the upper surface of the substrate and the area of the side surfaces of the substrate relative to the area of the upper surface of the substrate. The thickness is set so that the ratio of is included between the first set value and the second set value.

Description

[0001] LIGHT EMITTING DEVICE [0002]

The embodiment relates to a light emitting device, and more particularly to a light emitting device that emits ultraviolet light.

A light emitting diode (LED) is a kind of p-n junction diode, and is a semiconductor device using electroluminescence, a phenomenon in which monochromatic light is emitted when a voltage is applied in a forward direction. That is, when the forward voltage is applied, the electrons of the n-layer and the holes of the p-layer are combined to emit energy corresponding to the height difference (energy gap) between the conduction band and the valence band. Light emitting diodes emit energy in the form of light.

As such, the light emitting diode emits light using a combination of electrons and holes, and the combination of electrons and holes is performed in the active layer of the light emitting diode. In general, Group III nitrides such as gallium nitride (GaN), aluminum nitride (AlN), indium gallium nitride (InGaN), and the like are used in light emitting diodes due to their excellent physical and chemical properties. Specifically, group III nitrides are widely used in blue light emitting diodes (Blue LEDs) emitting blue light and ultraviolet light emitting diodes (UV LEDs) emitting ultraviolet rays. However, due to the characteristics of the group III nitride, which absorb light having a short wavelength and have low crystallinity, the ultraviolet light emitting diode has a lower internal quantum efficiency than the blue light emitting diode.

The light emitting diodes may be classified into horizontally structured light emitting diodes and vertically structured light emitting diodes according to the chip structure.

In addition, the horizontal structured light emitting diodes may be classified into Top-Emitting Light Emitting Diodes and Flip-Chip Light Emitting Diodes. At this time, the top-emit type light emitting diode has a structure that emits light through the ohmic electrode layer in contact with the second conductivity type semiconductor layer, while the flip chip type light emitting diode has a structure which emits light through the sapphire substrate.

That is, since the flip chip light emitting diode emits light directly through the sapphire substrate, the light extraction efficiency of the light emitting diode may vary according to the characteristics, structure, and shape of the sapphire substrate.

Embodiments provide a light emitting device in which an external light emitting device improves overall quantum efficiency by improving light extraction efficiency when a light emitting device emitting ultraviolet light is generated in a flip chip form.

When the light emitting device according to the embodiment is used, when the light emitting device emitting ultraviolet light is generated in the form of a flip chip, the light emitting device having improved overall external quantum efficiency may be provided.

1 is a view showing a light emitting device according to an embodiment.
2 is a three-dimensional view of the substrate of FIG. 1 according to an embodiment.
3 is a view showing an optical output amount corresponding to a change in thickness of the substrate of FIG. 1 according to an embodiment.
4 illustrates roughness present on the side of a substrate according to another embodiment.
FIG. 5 is a view illustrating an amount of light output corresponding to a thickness change of the substrate of FIG. 1 when roughness exists on a side surface of the substrate according to another embodiment.

The thickness and size of each layer in the accompanying drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

In the description of the embodiment according to the present invention, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

Hereinafter, a light emitting device according to an embodiment will be described with reference to the accompanying drawings.

1 is a view illustrating a light emitting device according to an embodiment.

Referring to FIG. 1, the light emitting device 100 according to the embodiment may include a chip 119 and a submount 127.

In the chip 119 of the light emitting device 100, the substrate 110 and the first conductive semiconductor layer 111 are disposed on the substrate 110, and the active layer 112 and the second conductive semiconductor layer ( A light emitting structure 114 in which 113 is sequentially stacked, a first electrode 115 formed on the second conductive semiconductor layer 113, and a second formed on the first conductive semiconductor layer 111. An electrode 117, a first under metal oxide (UBM) layer 116 formed on the first electrode 115, and a second base metal (UBM) formed on the second electrode 117. Layer 118 may be included.

The submount 127 of the light emitting device 100 may include a submount substrate 120, a first electrode pad 121 formed on the first region 120 on the right side of the submount substrate 120, A third base metal (UBM) layer 122 formed on the first electrode pad 121 and a second electrode pad 124 formed on the second region 120 of the submount substrate 120. ) And a fourth base metal (UBM) layer 125 formed on the second electrode pad 124.

The chip 119 of the light emitting device 100 and the submount 127 of the light emitting device 100 may be coupled by a first solder bumper 123 and a second solder bumper 126. Can be. More specifically, the first solder bumper 123 may include a first base metal layer (UBM) 116 of the chip 119 and a third base metal (UBM) layer 122 of the submount 127. The second solder bumper 126 is disposed between the second base metal (UBM) layer 118 of the chip 119 and the fourth base metal (UBM) of the submount 127. May be disposed between layers 125.

The substrate 110 may have a light transmitting property through which light can pass. The substrate 110 is an insulating substrate such as sapphire (Al 2 O 3), spinel (MgAl 2 O 4) mainly on the C surface, R surface, or A surface, SiC (including 6H, 4H, 3C), Si, GaAs, GaN At least one of semiconductor substrates such as ZnO, Si, GaP, InP, and Ge. However, the substrate 110 is not limited to the substrates described above, and the first conductive semiconductor layer 111, the active layer 112, and the second conductive semiconductor layer 113 may be sequentially grown. It is to be understood that the substrate includes any substrate.

2 is a three-dimensional view of the substrate of FIG. 1 according to an embodiment. As shown in FIG. 2, the substrate 110 has a hexahedron shape, and an upper surface (A surface) has a length (a) and a length (b), and side surfaces (B surface, C surface, and D). Surface, surface E) may have a length of thickness c.

In an embodiment, the ratio of the area of the upper surface A of the substrate 110 to the areas B, C, D, and E of the substrate 110 is based on the upper surface A of the substrate 110. The thickness of the substrate 110 may be set to be included between the first and second set values. In an embodiment, the first set value and the second set value may be set to 0.91 and 4.57, respectively. In another embodiment, the first setting value and the second setting value may be set to 1.14 and 2.86, respectively, in consideration of the efficiency of increasing the amount of light emitted according to the thickness.

The area of the upper surface A is the product of the horizontal a and the vertical b of the upper surface. In an embodiment, both the length (a) and length (b) of the substrate 110 may be set to 350 μm. In an embodiment, the first setting value and the second setting value are the characteristics of the substrate, the demand of the substrate currently used, This value is set in consideration of the manufacturing process. Therefore, the first set value and the second set value are not necessarily limited thereto, and may be changed in consideration of the area of the upper surface of the substrate, the characteristics of the substrate, the demand of the substrate, the manufacturing process of the substrate, and the like. For example, as in another embodiment, the first setting value and the second setting value may be set to 1.14 and 2.86, respectively, in consideration of the light emission amount increasing efficiency according to the thickness.

The area of the side surfaces (B surface, C surface, D surface, and E surface) of the substrate is the sum of the B surface, the C surface, the D surface, and the E surface of each side of the substrate. In an embodiment, the area of plane B and plane D is the product of the width a and the thickness c. In addition, the area | region of C surface and E surface becomes a product of length (b) and thickness (c). By this calculation method it is possible to calculate the area of the sides which is the sum of the sides of the substrate. In the embodiment, the area of the upper surface and the sides of the substrate is calculated by the above-described method, and the thickness c of the substrate is set to 80 μm to 400 μm using 0.91 and 4.57 as the first and second setting values. Can be. In addition, according to another exemplary embodiment, the thickness c of the substrate may be set to 100 μm to 250 μm using 1.14 and 2.86 as the first and second setting values.

3 is a view showing an amount of light output corresponding to a change in thickness of the substrate of FIG. 1 according to an embodiment. In FIG. 3, the horizontal axis represents the thickness of the substrate, and the vertical axis represents the light output. The light output amount corresponds to the amount of light emitted by the light emitting device according to the embodiment. Therefore, the relative size of the light emission amount of the light emitting device corresponding to the change of the thickness of the substrate according to the embodiment can be seen through the drawing of FIG. 3.

As shown in FIG. 3, in FIG. 3, the light output when the thickness of the substrate is 100 μm is set to 1 as a reference, and the relative light output according to the change in the thickness of the substrate is illustrated. The light emission amount of the light emitting device according to the embodiment is 1 at 100 μm, 1.3 at 130 μm, 1.4 at 150 μm, 1.5 at 200 μm, and 1.55 at 250 μm.

As shown in FIG. 3, in the light emitting device according to the embodiment, the light emission amount gradually increases as the thickness of the substrate 110 increases, but the increase is slowed down as the thickness increases. Here, the increase in the amount of emitted light can be interpreted as increasing the external quantum efficiency of the light emitting device. In the light emitting device according to the embodiment, when the thickness of the substrate 110 is increased, the area of the side surfaces of the substrate 110 is increased, thereby increasing the amount of light that can be emitted through the sides of the substrate 110. to be. That is, as the thickness of the substrate 110 increases, the external quantum efficiency of the light emitting device according to the embodiment increases. However, when the substrate 110 is 250 μm or more, since the increase in light emission amount is not large, it can be seen that the external quantum increase efficiency is not large compared to the increase in thickness.

4 illustrates roughness present on the side of a substrate according to another embodiment. 4 is a front view of the C surface, which is a side surface of the substrate 110 shown in FIG. 2.

As shown in FIG. 4, the region where roughness exists is an X region, and the region where roughness does not exist is a Y region. Roughness can be produced by a cutting process. For example, when cutting the substrate 110 according to the embodiment, when cutting the length x1 vertically from the top in the Figure of Figure 4, and split the substrate, roughness (roughness) may be generated by the length x1. Since the total area of the side surface of the substrate 110 is X + Y, and the area of the portion where roughness exists in the side surface of the substrate is X, the ratio of roughness occupies (X / (X + Y)). Here, roughness means that the surface is rough and irregular. As such, when roughness is present on the side of the substrate 110, the amount of light reflected from the side to the inside decreases, thereby increasing the amount of light emitted from the side. Therefore, the amount of light emitted from the side of the substrate is increased, thereby improving the external quantum efficiency of the light emitting device according to the embodiment.

FIG. 5 is a view illustrating an amount of light output corresponding to a thickness change of the substrate of FIG. 1 when roughness exists on a side surface of the substrate according to another embodiment.

3 and 5, when the thickness of the substrate 110 is the same, it can be seen that when the roughness exists in the substrate 110, the light output amount is further increased. For example, in FIG. 3, when the thickness of the substrate 110 is 200 μm, the light output is 1.5, whereas in FIG. 5, when the thickness of the substrate 110 is 200 μm, the light output is 1.7. As such, by including a roughness of a predetermined ratio or more in the substrate 110, the luminous efficiency of the light emitting device according to the embodiment may be increased. At this time, the ratio X / (X + Y) occupied by the roughness on the side of the substrate 110 may be set in a range of 20% to 80%. According to the ratio of the roughness, the amount of emitted light varies by up to 20%. In the embodiment, the ratio of roughness is set to 20% to 80%, but is not necessarily limited thereto, and may vary depending on the manufacturing process technology and manufacturing method of the substrate.

Although not described in FIG. 1, a buffer layer (not shown) may be disposed between the substrate 110 and the light emitting structure 114. Specifically, the buffer layer (not shown) is a layer for improving lattice matching with the substrate 110 before growing the first conductivity-type semiconductor layer 111 on the substrate 110. It may be omitted depending on device characteristics.

The first conductivity type semiconductor layer 111 may be, for example, an n-type semiconductor layer, and may have an In _X Al _Y Ga _1-XY N composition formula (where 0 ≦ X, 0 ≦ Y, and X + Y ≦ 1). It may be made of a semiconductor material having. Here, the material of the first conductivity type semiconductor layer 111 is not necessarily limited to such a semiconductor material. More specifically, the first conductivity type semiconductor layer 111 may be formed of a GaN layer or a GaN / AlGaN layer doped with an n-type dopant. In this case, the n-type dopant may be included in the first conductivity type semiconductor layer 300 at a concentration of 3 × 10 18 / cm 3 or more, preferably 5 × 10 18 / cm 3 or more. When the n-type dopant is heavily doped in this way, the forward voltage Vf and the threshold current can be lowered. If the concentration of the dopant is out of the above range, Vf will not be substantially lowered. In addition, when the first conductivity type semiconductor layer 111 is formed on u-GaN having good crystallinity, it may have good crystallinity even though it contains a high concentration of n-type dopant. Although the upper limit of the concentration of the n-type dopant is not limited, the upper limit is preferably 5 x 10 < 21 > / cm < 3 > or less in order to maintain good crystallinity.

As illustrated in FIG. 1, the first conductive semiconductor layer 111 may have a single layer structure or a multilayer structure.

The first conductivity-type semiconductor layer 111 may include a third region 111 on which the first electrode 115 is disposed and a fourth region 111 on which the second electrode 117 is disposed. It can be divided into. The third region defines a light emitting surface, and accordingly, an area of the third region may be larger than that of the fourth region to improve luminance characteristics of the device.

In the active layer 112, electrons (or holes) injected through the first conductivity type semiconductor layer 111 and holes (or electrons) injected through the second conductivity type semiconductor layer 113 formed later meet each other (Recombination). ), A layer that emits light due to a band gap difference of an energy band according to a material forming the active layer 112.

The active layer 112 may be formed of a single quantum well structure or a multi quantum well structure (MQW). The active layer 112 may be an MQW having an InGaN / GaN layer.

The active layer 112 generally includes a quantum well layer and a barrier layer. Here, the order of stacking the barrier layer and the quantum well layer is not specifically defined. However, the order of stacking the barrier layer and the quantum well layer may be laminated from the quantum well layer to the quantum well layer, or may be laminated from the quantum well layer to the barrier layer. In addition, the barrier layer may be laminated from the barrier layer to the barrier layer, or may be laminated from the barrier layer to the quantum well layer.

The second conductivity-type semiconductor layer 113 is, for example, a p-type semiconductor layer, and has In _X Al _Y Ga ₁ _-X- _Y N composition formula (where 0 ≦ X, 0 ≦ Y, and X + Y ≦ 1). It may be a semiconductor material having.

The second conductive semiconductor layer 113 is doped with p-type dopants such as Mg and Ba. Here, when the p-type dopant is Mg, the p-type characteristic is easily obtained, and the ohmic contact is easy to be obtained. The concentration of Mg may be 1 × 10 18 / cm 3 to 1 × 10 21 / cm 3, preferably 5 × 10 19 / cm 3 to 3 × 10 20 / cm 3, more preferably 1 × 10 20 / cm 3. If the Mg concentration is within this range, a good p-type film can be easily obtained and the Vf can be lowered.

Here, the second conductivity type semiconductor layer 113 may have a single layer structure or a multilayer structure.

The first electrode 115 is formed on the first conductive semiconductor layer 113. The first electrode 115 may be formed of at least one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. For example, the first electrode 115 may include a single layer or a reflective electrode / ohmic contact electrode, an ohmic contact electrode / a transparent electrode, or an ohmic contact electrode including any one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. It is a multi-layer consisting of transparent electrode and reflective electrode, and can be selected according to process conditions and device characteristics.

The second electrode 117 is formed on the fourth region of the first conductivity type semiconductor layer 111. The fourth region of the first conductivity type semiconductor layer 111 is a region in which part of the emission surface is removed by mesa etching. The second electrode 117 may be formed of at least one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. For example, the second electrode 117 may include a single layer or a reflective electrode / ohmic contact electrode, an ohmic contact electrode / a transparent electrode, or an ohmic contact electrode including one layer selected from a reflective electrode, an ohmic contact electrode, and a transparent electrode. It is a multi-layer consisting of transparent electrode and reflective electrode, and can be selected according to process conditions and device characteristics.

A first base metal (UBM) layer 116 is formed on the first electrode 115. In the first base metal (UBM) layer 116, the first solder bumper 123 may pass through the first electrode 115 to form the light emitting structure 114, that is, the second conductive semiconductor layer. (113), the active layer 112 and the first conductivity type semiconductor layer 111 is diffused to prevent the chip portion of the light emitting device 100 is destroyed, and the first electrode 115 And to enhance the adhesive force between the first solder bumper (solder bumper) (123).

A second base metal (UBM) layer 118 is formed on the first electrode 117. The second base metal (UBM) layer 118 has the second solder bumper 126 diffused through the first electrode 117 into the first conductive semiconductor layer 111 to emit light. It serves to prevent the chip portion of the device 100 from being destroyed, and also enhances the adhesion between the second electrode 117 and the second solder bumper 126.

The first and second base metal (UBM) layers 116 and 118 may include a first adhesive layer (not shown) for enhancing adhesion to the first electrode 115 or the second electrode 117, and A diffusion barrier layer (not shown) for preventing the first or second solder bumpers 123 and 126 from being diffused into the chip portion of the light emitting device 100, and the first or second solder bumpers 123 and 126. It may include a second adhesive layer (not shown) to enhance the adhesive force with). The first adhesive layer (not shown) may be made of one of metals including chromium (Cr) and titanium (Ti), and the diffusion barrier layer may be made of one of metals including copper (Cu) and tungsten (W). The second adhesive layer (not shown) may be made of one of metals including gold (Au) and nickel (Ni).

The submount substrate 120 may be a semi-insulated substrate, such as a silicon (Si) substrate. In this case, when the submount substrate 120 is a semi-insulator substrate, since the passivation layer does not need to be used, heat from the chip may be easily transferred to the submount substrate 120.

The submount substrate 120 may be replaced with a printed circuit board (PCB). The submount substrate 120 may be mounted with a plurality of chips to be used as a light source or an indicator.

First and second electrode pads 121 and 124 may be formed on the submount substrate 120 to face the first and second electrodes 115 and 117 of the chip. Specifically, the first electrode pad 121 is formed in a predetermined region on the submount substrate 120 facing the first electrode 115 and the submount substrate facing the second electrode 117. The second electrode pad 124 may be formed in a predetermined region on the 120. In this case, the first electrode pad 121 and the second electrode pad 124 may be spaced apart from each other on the submount substrate 120 by a predetermined distance.

Subsequently, the third base metal (UBM) layer 122 may be disposed to face the first base metal (UBM) layer 116 on the first electrode pad 121. In addition, the fourth base metal (UBM) layer 125 may be disposed to face the second base metal (UBM) layer 118 on the second electrode pad 124.

Here, the third and fourth base metal (UBM) layers 122 and 125 may include the first or second solder bumpers 123 and 126, and the first or second electrode pads 121 and 124. ) To prevent diffusion into the submount substrate 120, and also to the first or second electrode pads 121 and 124 and the first or second solder bumper 123. 126) to strengthen the adhesive force.

To this end, the third and fourth base metal (UBM) layers 122 and 125 may include a first adhesive layer (not shown) for enhancing adhesion to the first or second electrode pads 121 and 125. And a diffusion barrier layer (not shown) for preventing the first or second solder bumpers 123 and 126 from being diffused into the submount substrate 120, and the adhesion force between the first or second solder bumpers 123 and 126. It may include a second adhesive layer (not shown) to strengthen the. The first adhesive layer (not shown) may be made of one of metals including chromium (Cr) and titanium (Ti), and the diffusion barrier layer may be made of one of metals including copper (Cu) and tungsten (W). The second adhesive layer (not shown) may be made of one of metals including gold (Au) and nickel (Ni).

The light emitting device 100 may include the first base metal (UBM) layer 116 of the chip and the third base metal (UBM) layer of the submount in order to bond the chip and the submount to one. A first solder bumper 123 is formed between the 122s. A second solder bumper 126 is formed between the second base metal (UBM) layer 118 of the chip and the fourth base metal (UBM) layer 125 of the submount. have.

The first and second solder bumpers 123 and 126 may transfer heat generated from the chip through electrical contact between the chip and the submount through the first to fourth base metal layers 116, 118, 122, and 125. A passage for delivering to the mount substrate 120 is provided.

The first and second solder bumpers 123 and 126 may generally be made of a conductive metal mainly composed of lead (Pb) and tin (Sn), and the first base metal (UBM) layer 116 and the first Flip chip bonding is performed between the three base metal (UBM) layers 122 and between the second base metal (UBM) layer 118 and the fourth base metal (UBM) layer 125.

Although the above description has been made with reference to the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not illustrated above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

100: Light emitting element
110 substrate 111 first conductive semiconductor layer
112: active layer 113: second conductive semiconductor layer
114: light emitting structure 115: first electrode
116: First Bumper Metalization (UBM) layer
117: second electrode 118: second base metal (UBM) layer
120: submount substrate 121: first electrode pad
122: third base metal (UBM) layer
123: first solder bumper
124: second electrode pad 125: fourth base metal (UBM) layer
126: second solder bumper

Claims

A light transmissive substrate having a constant thickness;
A first conductive semiconductor layer disposed on the substrate, a second conductive semiconductor layer disposed on the first conductive semiconductor layer, and disposed between the first conductive semiconductor layer and the second conductive semiconductor layer A light emitting structure including an active layer;
A first electrode disposed on the first conductive semiconductor layer and a second electrode disposed on the second conductive semiconductor layer;
A first electrode pad electrically connected to the first electrode and a second electrode pad electrically connected to the second electrode; And
A semi-insulated submount substrate on which the first and second electrode pads are disposed;
And setting the thickness such that a ratio of the area of the upper surface of the substrate to the area of the side surfaces of the substrate is included between the first and second setting values based on the area of the upper surface of the substrate.

The method of claim 2, wherein the first setting value and the second setting value,
The light emitting element which is 0.91 and 4.57, respectively.

The horizontal length and vertical length of the upper surface of the substrate,
A light emitting element, each 350 μm.

The method of claim 1, wherein the thickness is,
The light emitting element set in the range of 80 micrometers-400 micrometers.

The method of claim 1, wherein the sides of the substrate,
A light emitting device having a roughness ratio of the thickness.

The method of claim 5, wherein the predetermined ratio is
20% to 80%.

The method of claim 1, wherein the active layer
The light emitting element which radiates the ultraviolet-ray whose length of wavelength is 280 nm or less.