KR20140024535A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Array substrate for liquid crystal display device and method of fabricating the same Download PDF

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KR20140024535A
KR20140024535A KR1020120090512A KR20120090512A KR20140024535A KR 20140024535 A KR20140024535 A KR 20140024535A KR 1020120090512 A KR1020120090512 A KR 1020120090512A KR 20120090512 A KR20120090512 A KR 20120090512A KR 20140024535 A KR20140024535 A KR 20140024535A
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oxide semiconductor
semiconductor layer
electrode
pixel electrode
gate
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KR1020120090512A
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Korean (ko)
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KR102035004B1 (en
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김민주
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엘지디스플레이 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

The present invention provides an array substrate for a liquid crystal display device comprising: a gate line and a data line which crosses each other to define a pixel area; a gate electrode which is connected to the gate line; a gate insulation film for covering the gate line and the gate electrode; an oxide semiconductor layer which is located on the gate insulation layer to correspond to the gate electrode; a pixel electrode which is located on the gate insulation layer to be formed on the pixel area; a first etch stopper for covering the center part of the oxide semiconductor layer; a source electrode which is connected to the data line and is in contact with one end of the oxide semiconductor layer; and a drain electrode which is spaced from the source electrode, has one end in contact with the other end of the oxide semiconductor layer and has the other end in contact with the pixel electrode, wherein the pixel electrode is made of the same material in the same layer as the oxide semiconductor layer.

Description

Array substrate for liquid crystal display device and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device, and in particular, an array substrate for a liquid crystal display device capable of preventing an increase in a mask process while having an advantage of a high transmittance and a narrow bezel using an oxide semiconductor layer having excellent device characteristic stability. And it relates to a manufacturing method thereof.

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In such a liquid crystal display device, an array substrate including a thin film transistor, which is essentially a switching element, is configured to remove each of the pixel areas on and off.

1 is a cross-sectional view of a portion of a conventional array substrate constituting a liquid crystal display device in which one pixel region is cut including a thin film transistor.

As shown in the drawing, a gate electrode may be formed in the switching region TrA in the plurality of pixel regions P defined by crossing a plurality of gate lines (not shown) and a plurality of data lines 33 on the array substrate 11. 15) is formed. In addition, a gate insulating film 18 is formed on the entire surface of the gate electrode 15, and a semiconductor layer including an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon is sequentially formed thereon. 28 is formed.

In addition, the ohmic contact layer 26 is spaced apart from each other to correspond to the gate electrode 15, and a source electrode 36 and a drain electrode 38 are formed. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, the thickness difference (t1 ≠ t2) of the active layer 22, more precisely the source and drain in which the channel layer is formed therein. As the thickness of the thin film transistor Tr is reduced in the portions exposed between the electrodes, deterioration of the characteristics of the thin film transistor Tr occurs.

Therefore, recently, as shown in Fig. 2 (sectional view of one pixel region of an array substrate having a thin film transistor having an oxide semiconductor layer), a thin film using an oxide semiconductor material without requiring an ohmic contact layer is required. Transistors have been developed.

The thin film transistor Tr using an oxide semiconductor material includes a gate electrode 73, a gate insulating layer 75, an oxide semiconductor layer 77, a source electrode 81, and a drain electrode 83. In addition, a pixel electrode 89 connected to the drain electrode 83 may be provided, and a protective layer 85 may be formed between the drain electrode 83 and the pixel electrode 89.

Since the oxide semiconductor layer 77 does not need to form an ohmic contact layer, in order to form an ohmic contact layer spaced from each other made of impurity amorphous silicon, which is a similar material, as in an array substrate having a semiconductor layer made of conventional amorphous silicon. Since it does not need to be exposed to the ongoing dry etching, it is possible to prevent degradation of the characteristics of the thin film transistor (Tr).

Since the thin film transistor using the oxide semiconductor layer 77 has higher charge mobility than the thin film transistor using amorphous silicon, the size of the thin film transistor can be reduced. Therefore, it has the advantage of the narrow bezel that the transmittance is improved and the size of the non-display area is reduced.

In a mobile display device requiring high resolution, low power consumption and narrow bezel characteristics are required, and an array substrate using an oxide semiconductor layer is widely used for this purpose.

However, when the oxide semiconductor layer 77 is exposed to an etchant used for patterning a metal layer for forming the source electrode 81 and the drain electrode 83, the oxide semiconductor layer 77 has no selectivity with the metal layer and is etched away or is removed. The damage by may affect the characteristics of the thin film transistor Tr.

Accordingly, the oxide semiconductor layer 77 disposed below the oxide semiconductor layer 77 is exposed to an etchant reacting with the metal material forming the source and drain electrodes 81 and 83 during patterning for forming the source and drain electrodes 81 and 83. In order to prevent this, an etch stopper 79 is formed corresponding to the central portion of the oxide semiconductor layer 77.

However, in order to manufacture the conventional array substrate 71 including the oxide semiconductor layer 77 and the thin film transistor Tr having the etch stopper 79 thereon, one time is required to form the etch stopper 79. Additional mask processing is needed.

Since the mask process includes a photoresist coating process, an exposure process using an exposure mask, a developing process of an exposed photoresist, an etching process, and a strip process, the process is complicated and a large amount of chemical is used. The longer the manufacturing time is, the more the productivity is charged per unit time and the manufacturing cost increases.

An object of the present invention is to prevent an increase in a mask process in an array substrate for an LCD device including an oxide semiconductor layer and an etch stopper.

That is, the use of the oxide semiconductor layer has the advantages of high transmittance and narrow bezel, while preventing the increase of the mask process to provide a high-quality array substrate for the liquid crystal display device while simplifying the manufacturing process and reducing the manufacturing cost.

In order to solve the above problems, the present invention includes a gate wiring and a data wiring crossing each other to define a pixel region; A gate electrode connected to the gate wiring; A gate insulating film covering the gate wiring and the gate electrode; An oxide semiconductor layer on the gate insulating layer and corresponding to the gate electrode; A pixel electrode on the gate insulating layer and formed in the pixel region; A first etch stopper covering a central portion of the oxide semiconductor layer; A source electrode connected to the data line and in contact with one end of the oxide semiconductor layer; A drain electrode spaced apart from the source electrode, one end of which is in contact with the other end of the oxide semiconductor layer and the other end of which is in contact with the pixel electrode, wherein the pixel electrode is made of the same material as the oxide semiconductor layer. An array substrate for a liquid crystal display device is provided.

In the array substrate for a liquid crystal display device of the present invention, the oxide semiconductor layer is indium-gallium-zinc-oxide (IGZO) or indium-tin-zinc-oxide. oxide, ITZO) is characterized in that it is made of an oxide semiconductor material.

In the array substrate for a liquid crystal display device of the present invention, the pixel electrode is formed by performing a plasma treatment process on the oxide semiconductor layer.

In the array substrate for liquid crystal display device of the present invention, the plasma processing step is characterized by using helium plasma.

An array substrate for a liquid crystal display device of the present invention, comprising: a second etch stopper exposing one end of the pixel electrode and covering the pixel electrode, wherein the drain electrode is in contact with one end of the pixel electrode.

An array substrate for a liquid crystal display device of the present invention, comprising: a protective layer on the data line, the source electrode, the drain electrode, and the pixel electrode; And a common electrode on the passivation layer and having at least one opening corresponding to the pixel electrode.

In another aspect, the present invention includes the steps of forming a gate wiring and a gate electrode connected to the gate wiring; Forming a gate insulating film covering the gate wiring and the gate electrode; Forming an oxide semiconductor layer and a pixel electrode on the gate insulating film, the oxide semiconductor layer corresponding to the gate electrode; Forming a first etch stopper covering a central portion of the oxide semiconductor layer; A data line crossing the gate line, a source electrode connected to the data line and in contact with one end of the oxide semiconductor layer, and one end spaced from the source electrode and one end contacting the other end of the oxide semiconductor layer and the other end of the pixel It provides a method for manufacturing an array substrate for a liquid crystal display device comprising the step of forming a drain electrode in contact with the electrode.

In the method of manufacturing an array substrate for a liquid crystal display device of the present invention, the oxide semiconductor layer and the pixel electrode are made of the same material.

In the method of manufacturing an array substrate for a liquid crystal display device of the present invention, the oxide semiconductor layer and the pixel electrode is indium-gallium-zinc-oxide (IGZO) or indium-tin-zinc-oxide and an oxide semiconductor material selected from indium-tin-zinc-oxide (ITZO), and the pixel electrode is formed by performing a plasma treatment process on the oxide semiconductor layer.

In the method of manufacturing an array substrate for a liquid crystal display device of the present invention, after the step of forming an oxide semiconductor layer and a pixel electrode corresponding to the gate electrode on the gate insulating film, a heat treatment process is performed, It is characterized by using a helium plasma.

In the method of manufacturing an array substrate for a liquid crystal display device of the present invention, the heat treatment process is characterized in that for 1 to 3 hours at 200 ~ 300 ℃ temperature conditions.

In the method of manufacturing an array substrate for a liquid crystal display device of the present invention, forming an oxide semiconductor layer and a pixel electrode corresponding to the gate electrode on the gate insulating film, forming an oxide semiconductor material layer on the gate insulating film Making a step; Forming a first photoresist pattern having a first height and a second photoresist pattern having a second height smaller than the first height on the oxide semiconductor layer; Forming the oxide semiconductor layer and the pixel electrode by etching the oxide semiconductor layer using the first and second photoresist patterns; Performing an ashing process to remove the second photoresist pattern on the pixel electrode and to form a third photoresist pattern on the oxide semiconductor layer from the first photoresist pattern; Plasma processing the third photoresist pattern as a blocking mask; And removing the third photoresist pattern.

In the method of manufacturing an array substrate for a liquid crystal display device of the present invention, the forming of the first etch stopper covering the center portion of the oxide semiconductor layer may include forming a second etch stopper exposing one end of the pixel electrode and covering the pixel electrode. And forming a drain electrode in contact with one end of the pixel electrode.

A method of manufacturing an array substrate for a liquid crystal display device according to the present invention, comprising: forming a protective layer on the data line, the source electrode, the drain electrode, and the pixel electrode; And forming a common electrode on the passivation layer, the common electrode having at least one opening corresponding to the pixel electrode.

According to the present invention, since the thin film transistor is formed using the oxide semiconductor layer, the characteristics of the thin film transistor are improved, thereby providing an array substrate for a liquid crystal display device having advantages of increased transmittance and narrow bezel due to the size reduction of the thin film transistor.

In addition, by forming a pixel electrode by plasma treating the oxide semiconductor material, an increase in a mask process can be prevented while using an oxide semiconductor layer that requires an etch stopper. In particular, through the helium plasma treatment, the resistance can be prevented from being increased by the heat treatment process to form a conductive pixel electrode.

As a result, the manufacturing process of the array substrate for the liquid crystal display device becomes complicated and the manufacturing cost increases.

1 is a cross-sectional view of one pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device;
FIG. 2 is a cross-sectional view of one pixel region of an array substrate for a liquid crystal display device having a thin film transistor having a conventional oxide semiconductor layer. FIG.
3 is a plan view of a portion of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a cross-sectional view taken along the line IV-IV in Fig. 3;
5A to 5F are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device shown in FIG. 4.
6 is a graph showing the sheet resistance change of the oxide semiconductor layer according to the plasma treatment and heat treatment process.

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

3 is a plan view of a portion of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3. For explanation, the region where the thin film transistor is located is defined as the switching region TrA.

As illustrated, an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention includes a substrate 110, a gate wiring 112, a data wiring 150, and a thin film transistor (Tr) formed on the substrate 110. ), A pixel electrode 130, and a common electrode 170.

The gate line 112 and the data line 150 cross each other to define a pixel region P, and the thin film transistor Tr is connected to the gate line 112 and the data line 150. It is located in the switching area TrA in the pixel area P. FIG.

The thin film transistor Tr includes a gate electrode 114 on the substrate 110, a gate insulating layer 116 covering the gate electrode 114, and an oxide semiconductor layer 120 positioned on the gate insulating layer 116. ), A first etch stopper 142 covering the center of the oxide semiconductor layer 120, a source electrode 152 and a drain electrode 154 contacting both ends of the oxide semiconductor layer 120 and spaced apart from each other. Is done. The oxide semiconductor layer 120 is an oxide semiconductor material such as indium-gallium-zinc-oxide (IGZO) or indium-tin-zinc-oxide (ITZO). Is made of. The gate electrode 114 is connected to the gate wiring 112, and the source electrode 152 is connected to the data wiring 150.

The pixel electrode 130 has a plate shape in the pixel region P and is connected to the drain electrode 154. A second etch stopper 144 exposing one end is formed on the pixel electrode 130. In addition, since the drain electrode 154 is formed on the upper layer than the pixel electrode 130, the drain electrode 154 is in contact with one side and the top edge of the pixel electrode 130. That is, the drain electrode 154 is in contact with one end of the pixel electrode 130 exposed by the second etch stopper 144.

A passivation layer 160 is formed to cover the thin film transistor Tr and the pixel electrode 130, and the passivation layer 160 has at least one opening 172 corresponding to the pixel electrode 130. The plate-shaped common electrode 170 is formed.

In this structure, when a data voltage is applied to the pixel electrode 130 by switching the thin film transistor Tr, a fringe field is formed between the pixel electrode 130 and the common electrode 170. Is formed.

Alternatively, the pixel electrode and the common electrode have a bar shape and are alternately arranged to form an array substrate for an in-plane switching mode liquid crystal display device. In addition, only a plate-shaped pixel electrode may be formed, and a plate-shaped pixel electrode may be formed on a color filter substrate facing the array substrate to use a vertical electric field.

The pixel electrode 130 is positioned on the same layer as the oxide semiconductor layer 120 and is formed of the same material. That is, the pixel electrode 130 is formed of an oxide semiconductor material such as IGZO or ITZO, and the oxide semiconductor material is conductorized by decreasing its resistance by plasma treatment.

The oxide semiconductor material itself cannot be used as a pixel electrode to form an electric field with the common electrode 170 by applying a voltage. However, in the present invention, the oxide semiconductor material is subjected to a plasma treatment to conduct a conductor and use it as the pixel electrode 130.

The plasma treatment is preferably a helium (He) plasma treatment, which will be described later.

In an array substrate having such a structure, since an oxide semiconductor material is used, characteristics such as charge mobility of the thin film transistor Tr are improved, and thus the size of the thin film transistor Tr has the advantage of a narrow bezel.

In addition, damage to the oxide semiconductor layer 120 can be prevented by forming the first etch stopper 142. That is, after the oxide semiconductor layer 120 is formed, the source layer 152 and the drain electrode 154 are formed by a wet etching process using an etchant after forming the metal layer. The first etch stopper 142 may form the metal layer. The oxide semiconductor layer 120 is prevented from being damaged by exposure to the etchant.

The pixel electrode 130 and the oxide semiconductor layer 120 are formed by one mask process. Therefore, although one mask process is additionally required to form the first etch stopper 142 for protecting the oxide semiconductor layer 120, the pixel electrode 130 and the oxide semiconductor layer 120 may be formed in one. Since it is formed by the mask process, an increase in the mask process does not occur.

5A through 5F are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device shown in FIG. 4.

As shown in FIG. 5A, copper (Cu), copper alloy (AlNd), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), titanium (Ti), or molybdenum-titanium alloy on the substrate 110. A low-resistance metal material such as (MoTi) is deposited to form a first metal material layer (not shown), and patterned by performing a mask process to form a gate wiring 112 (see FIG. 3) and a gate electrode 114. The gate wiring 112 extends along the boundary of the pixel region P, and the gate electrode 114 extends from the gate wiring 112 and is positioned in the switching region TrA.

Next, an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the gate line 112 and the gate electrode 114 to form a gate insulating layer 116.

Next, as shown in FIG. 5B, an oxide semiconductor layer such as IGZO or ITZO is deposited to form an oxide semiconductor material layer 118. Subsequently, a photoresist is applied and an exposure and development process is performed using an exposure mask (not shown), respectively, in the region where the oxide semiconductor layer (120 in FIG. 5C) is to be formed and in the region where the pixel electrode (130 in FIG. 5C) is to be formed. Corresponding first and second photoresist patterns 191 and 192 are formed. The oxide semiconductor material layer 118 is exposed in a region where the first and second photoresist patterns 191 and 192 are not formed.

Although not shown, the exposure mask has a transmissive part, a blocking part, and a transflective part, the first photoresist pattern 191 is formed corresponding to the blocking part, and the second photoresist pattern 192 is formed in the transflective part. Correspondingly formed. The photoresist is fully developed in correspondence to the transmissive portion to expose the oxide semiconductor material layer 118.

That is, the first and second photoresist patterns 191 and 192 are formed by a halftone mask process or a diffraction exposure process, and the first photoresist pattern 191 is formed from the second photoresist pattern 192. Spaced apart from the second photoresist pattern 192.

5C, the exposed oxide semiconductor material layer 118 is etched using the first and second photoresist patterns 191 and 192 of FIG. 5B as an etching mask. Thereafter, an ashing process is performed on the first and second photoresist patterns 191 and 192 to remove the second photoresist pattern 192 having a small thickness. In this case, the thickness of the first photoresist pattern 191 decreases to become the third photoresist pattern 193.

Thereafter, the oxide semiconductor material is conductored by performing a plasma treatment using the third photoresist pattern 193 as a blocking mask. Accordingly, a pixel electrode 130 made of an oxide semiconductor material conductively formed by plasma processing is formed in the pixel region P. Referring to FIG. In this case, since the oxide semiconductor layer 120 is covered by the third photoresist pattern 193, the oxide semiconductor layer 120 is not conductive and maintains semiconductor characteristics.

Plasma treatment for the conductorization of the oxide semiconductor material may be performed using hydrogen plasma or helium plasma, and the plasma semiconductor lowers the resistance of the oxide semiconductor layer.

Referring to FIG. 6, which is a graph showing the sheet resistance change of the oxide semiconductor layer according to the plasma treatment and the heat treatment process, when the plasma treatment process is performed after the deposition of the oxide semiconductor layer (As-Dep), the sheet resistance of the oxide semiconductor layer is increased. It can be seen that the sharp decrease.

Meanwhile, in order to improve the characteristics of the thin film transistor or to remove moisture, the oxide semiconductor layer 120 may be formed using an oxide semiconductor material, and then an annealing process may be performed. That is, by performing a heat treatment process for about 1 to 3 hours at a temperature condition of about 200 ~ 300 ℃, to compensate the oxygen to the oxide semiconductor layer 120 or to remove the moisture after the cleaning process. The oxide semiconductor layer 120 may change its properties, that is, carrier concentration, depending on the content of oxygen. If the content of oxygen is too small, the oxide semiconductor layer 120 may have conductor properties. By compensating for oxygen lost in the process after the oxide semiconductor layer 120 is formed by the heat treatment process, the semiconductor characteristics of the oxide semiconductor layer 120 are improved.

However, as shown in FIG. 6, when such a heat treatment process is performed, the surface resistance of the oxide semiconductor material subjected to the hydrogen plasma treatment process is rapidly increased. Accordingly, the oxide semiconductor material conductive by the hydrogen plasma treatment may be used as the pixel electrode 130, but may not be used as the pixel electrode after the heat treatment process is performed.

Meanwhile, the oxide semiconductor material subjected to the helium plasma treatment process has a very low rate of increase in sheet resistance even after the heat treatment process is performed. Therefore, the oxide semiconductor material subjected to the helium plasma treatment process may be used as the pixel electrode 130 even after the heat treatment process is performed.

Accordingly, in the present invention, even when the heat treatment process is performed to improve the characteristics of the oxide semiconductor layer 120, it is preferable to proceed with the helium plasma treatment process to form the pixel electrode 130 with the oxide semiconductor material. However, if the heat treatment step does not proceed, the hydrogen plasma treatment step may proceed.

Next, a strip process is performed to remove the third photoresist pattern 193.

Next, as shown in FIG. 5D, an inorganic insulating material such as silicon oxide is deposited on the oxide semiconductor layer 120 and the pixel electrode 130 to form an inorganic insulating material layer (not shown), and then By patterning, the first and second etch stoppers 142 and 144 are formed. The first etch stopper 142 is positioned at the center of the oxide semiconductor layer 142 to correspond to the gate electrode 114, and the second etch stopper 144 exposes one end of the pixel electrode 144. And covers the pixel electrode 144.

Next, as shown in FIG. 5E, copper (Cu), copper alloy (AlNd), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), titanium (Ti) or molybdenum-titanium alloy (MoTi) and The same low resistance metal material is deposited to form a second metal material layer (not shown), and patterned by a mask process to form the data line 150, the source electrode 152, and the drain electrode 154.

The data line 150 crosses the gate line 112 and is connected to the source electrode 152. The source electrode 152 and the drain electrode 154 are positioned in the switching region TrA and spaced apart from each other. The source electrode 152 covers one end of the etch stopper 142 and one end of the oxide semiconductor layer 120, and the drain electrode 154 has the other end of the etch stopper 130 and the oxide semiconductor layer 120. Cover the other end of the).

The pattern process of the second metal material layer is performed by wet etching using an etchant, and damage occurs when the oxide semiconductor layer 120 or the pixel electrode 130 is exposed to the etchant. However, in the present invention, since the oxide semiconductor layer 120 and the pixel electrode 130 are covered with the first and second etch stoppers 142 and 144, damage to the etching solution due to exposure to the etchant is fundamentally prevented.

The gate electrode 114, the gate insulating layer 116, the oxide semiconductor layer 120, the first etch stopper 142, the source electrode 152, and the drain electrode 154 stacked in the switching region TrA are thin films. The transistor Tr is constituted.

Next, as shown in FIG. 5F, an organic insulating material such as photo-acrylic or benzocyclobutene is coated on the data line 150, the thin film transistor Tr, and the second etch stopper 144. An inorganic insulating material such as silicon oxide or silicon nitride is deposited to form the protective layer 160.

Thereafter, a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited on the protective layer 160 to form a transparent conductive material. Form a layer (not shown). By patterning the transparent conductive material layer to form a common electrode 170 having at least one opening 172 corresponding to the pixel electrode 130, an array substrate for a liquid crystal display device according to an exemplary embodiment of the present invention can be obtained. have.

In the above-described process, the heat treatment process for the oxide semiconductor layer 120 is a process for forming the first and second etch stoppers 142 and 144 or the data line 150, the source electrode 152 and the drain electrode. And proceed with the forming process of 154.

In the array substrate for a liquid crystal display device of the present invention, by forming a thin film transistor using an oxide semiconductor layer, it has advantages of excellent electrical characteristics and narrow bezel.

In addition, an increase in the mask process can be prevented by forming the pixel electrode and the oxide semiconductor layer by one mask process while forming an etch stopper for protecting the oxide semiconductor layer.

In addition, since the oxide semiconductor material has a conductor characteristic by the helium plasma treatment process, the oxide semiconductor material can be used as a pixel electrode even if a heat treatment process for improving the characteristics of the oxide semiconductor layer is performed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

110: substrate 112: gate wiring
114: gate electrode 120: oxide semiconductor layer
130: pixel electrode 142, 144: etch stopper
150: data wiring 152: source electrode
154: drain electrode 170: common electrode
Tr: Thin Film Transistor

Claims (14)

Gate wiring and data wiring crossing each other to define a pixel region;
A gate electrode connected to the gate wiring;
A gate insulating film covering the gate wiring and the gate electrode;
An oxide semiconductor layer on the gate insulating layer and corresponding to the gate electrode;
A pixel electrode on the gate insulating layer and formed in the pixel region;
A first etch stopper covering a central portion of the oxide semiconductor layer;
A source electrode connected to the data line and in contact with one end of the oxide semiconductor layer;
A drain electrode spaced apart from the source electrode, one end of which is in contact with the other end of the oxide semiconductor layer and the other end of which is in contact with the pixel electrode;
And the pixel electrode is made of the same material as the oxide semiconductor layer.
The method of claim 1,
The oxide semiconductor layer is made of an oxide semiconductor material selected from indium-gallium-zinc-oxide (IGZO) or indium-tin-zinc-oxide (ITZO). An array substrate for a liquid crystal display device, characterized in that.
3. The method of claim 2,
And the pixel electrode is formed by performing a plasma treatment process on the oxide semiconductor layer.
The method of claim 3, wherein
And said plasma processing step uses helium plasma.
The method of claim 1,
And a second etch stopper exposing one end of the pixel electrode and covering the pixel electrode, wherein the drain electrode is in contact with one end of the pixel electrode.
The method of claim 1,
A protective layer on the data line, the source electrode, the drain electrode, and the pixel electrode;
And a common electrode on the passivation layer and having at least one opening corresponding to the pixel electrode.
Forming a gate wiring and a gate electrode connected to the gate wiring;
Forming a gate insulating film covering the gate wiring and the gate electrode;
Forming an oxide semiconductor layer and a pixel electrode on the gate insulating film, the oxide semiconductor layer corresponding to the gate electrode;
Forming a first etch stopper covering a central portion of the oxide semiconductor layer;
A data line crossing the gate line, a source electrode connected to the data line and in contact with one end of the oxide semiconductor layer, and one end spaced from the source electrode and one end contacting the other end of the oxide semiconductor layer and the other end of the pixel Forming a drain electrode in contact with the electrode
Method of manufacturing an array substrate for a liquid crystal display device comprising a.
The method of claim 7, wherein
And the oxide semiconductor layer and the pixel electrode are made of the same material.
The method of claim 8,
The oxide semiconductor layer and the pixel electrode are selected from indium-gallium-zinc-oxide (IGZO) or indium-tin-zinc-oxide (ITZO). Made of semiconductor material,
And the pixel electrode is formed by performing a plasma treatment process on the oxide semiconductor layer.
The method of claim 9,
After the step of forming the oxide semiconductor layer and the pixel electrode corresponding to the gate electrode on the gate insulating film, a heat treatment process is performed,
The plasma processing step is a method of manufacturing an array substrate for a liquid crystal display device, characterized in that using helium plasma.
11. The method of claim 10,
The heat treatment process is a method of manufacturing an array substrate for a liquid crystal display device, characterized in that for 1 to 3 hours at 200 ~ 300 ℃ temperature conditions.
The method of claim 7, wherein
Forming the oxide semiconductor layer and the pixel electrode corresponding to the gate electrode on the gate insulating film,
Forming an oxide semiconductor material layer on the gate insulating film;
Forming a first photoresist pattern having a first height and a second photoresist pattern having a second height smaller than the first height on the oxide semiconductor layer;
Forming the oxide semiconductor layer and the pixel electrode by etching the oxide semiconductor layer using the first and second photoresist patterns;
Performing an ashing process to remove the second photoresist pattern on the pixel electrode and to form a third photoresist pattern on the oxide semiconductor layer from the first photoresist pattern;
Plasma processing the third photoresist pattern as a blocking mask;
And removing the third photoresist pattern.
The method of claim 7, wherein
Forming a first etch stopper covering a central portion of the oxide semiconductor layer, forming a second etch stopper exposing one end of the pixel electrode and covering the pixel electrode;
And the drain electrode is in contact with one end of the pixel electrode.
The method of claim 7, wherein
Forming a protective layer on the data line, the source electrode, the drain electrode, and the pixel electrode;
Forming a common electrode having at least one opening corresponding to the pixel electrode on the passivation layer.
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