KR20130112633A - Voltage control device and semiconductor device having the same - Google Patents

Abstract

PURPOSE: A potential control device is provided to prevent unnecessary current consumption by setting the potential of a terminal depending on whether the terminal is connected to power or not, thereby improving the power usage efficiency. CONSTITUTION: A potential control device (100) includes a first terminal (CON) connected to a first power supply (VCCQ); a switch (110) which controls the electrical connection state between the first terminal and a second terminal, which has a second potential level lower than the potential level of the first power supply, depending on a control signal (DISCH); and a switch control unit (120). The switch control unit includes a first control unit (121) which controls a control signal at a first potential level; a second control unit (122) which controls a control signal at a second potential level, which is lower than the first potential level; and a logic control unit (123) which controls the first control unit and the second control unit depending on the potential level of the first terminal.

Description

Potential control device and semiconductor device including the same {VOLTAGE CONTROL DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME}

The present invention relates to a potential control device for controlling a potential of a terminal and a semiconductor device including the same. The present invention also relates to a potential control device for setting an address of a chip and a semiconductor device including the same.

1 is a circuit diagram showing a conventional potential control device 1.

The conventional potential control device 1 pulls down the potential of the terminal A to the ground potential when the terminal A is in the floating state. In the conventional potential control device 1, when a power supply potential (for example, VDD) is applied to the terminal A, the potential is fixed to the power supply potential. That is, the conventional potential control apparatus 1 sets the potential of the terminal A to a low level when the terminal A is floating, and sets the potential of the terminal A to the high level when the terminal A is connected to the power supply potential. Set to.

FIG. 2 is a block diagram showing a semiconductor device 20 using the potential control device 1 of FIG. 1 to set a chip address.

The semiconductor device 20 includes a plurality of chips (or dies) 10, 10 ′. Each chip 10, 10 ′ has pad circuits 11, 11 ′ and an internal circuit. The pad circuits 11 and 11 'include potential control devices 1 and 1', pads and buffers.

The leads 21 and 22 installed in the package of the semiconductor device 20 may or may not be connected to pads in the pad circuits 11 and 11 ′ of the semiconductor chips 10 and 10 ′. In the illustrated example, lead 1 21 is not connected to the pad of semiconductor chip 10, and lead 2 22 is connected to the pad of semiconductor chip 10 ′.

As described in FIG. 1, when the potential control device 1 sets the terminal A of the pad circuit 11 to the ground potential and the potential control device 1 ′ is applied with a power supply potential to the lead 2 22. The potential of the terminal A 'of the pad circuit 11' is set to a power supply potential.

The potentials of these terminals A, A 'can be used, for example, as an address for identifying a chip, ie a chip address. 2, the chip address of the semiconductor chip 10 is set to '0' and the chip address of the semiconductor chip 10 is set to '1'. Each of the semiconductor chips 10 and 10 ′ includes a plurality of pad circuits, and a chip address of a multi-bit can be set by connecting or not connecting pads in each pad circuit with leads.

The internal circuits of each of the semiconductor chips 10 and 10 'receive the chip addresses of the semiconductor chips 10 and 10' according to the potentials of the terminals A and A 'output from the buffers of the pad circuits 11 and 11'. To identify.

The conventional potential control apparatuses 1 and 1 ′ can set the chip address as they are connected or not connected to one of the leads 21 and 22, thereby reducing the number of leads required for setting the chip address. However, the conventional potential control apparatuses 1 and 1 'have a problem of continuously wasting unnecessary current by forming a current path from the terminal A to the ground terminal when a power supply potential is applied to the terminal A.

An object of the present invention is to provide a potential control device that prevents unnecessary current consumption by blocking generation of a current path even when the potential of the terminal is set at a high level.

It is also an object of the present invention to provide a semiconductor device having improved power efficiency, including a potential control device that prevents unnecessary current consumption when the potential of the terminal is set at a high level.

The potential control device according to the present invention has a first terminal electrically connected to or disconnected from an external terminal connected to a first power source, and a potential lower than that of the first terminal and the first power source when the external terminal is connected to the first terminal. And a control unit for blocking a current path between second terminals having the second terminal and setting the potential of the first terminal to a potential lower than that of the first power supply when the external terminal is separated from the first terminal.

In the potential control device according to the present invention, the control unit includes a switch for connecting or disconnecting the first terminal and the second terminal according to a control signal; And a switch for outputting a control signal for controlling the connection between the first terminal and the second terminal when the external terminal is connected to the first terminal and the first terminal and the second terminal when the external terminal is disconnected from the first terminal. It includes a control unit.

In the controller of the potential controller according to the present invention, the switch controller includes: a first controller configured to control the control signal to a first potential; A second control unit controlling the control signal to a second potential lower than the first potential; And a logic control unit for controlling the first control unit and the second control unit according to the potential of the first terminal.

In the potential control apparatus according to the present invention, the first control unit further includes a bias setting unit for adjusting the potential of the control signal.

In the potential control apparatus according to the present invention, the logic controller activates the first controller according to an initialization signal of power supplied to the first controller.

In the potential control device according to the present invention, the power source provided to the first control unit is a second power source different from the first power source.

In the potential control device according to the present invention, the power source provided to the first control unit is the same as the first power source.

In the potential control device according to the present invention, the initialization signal is a pulse signal generated when the power supplied to the first control unit is activated.

In the potential control apparatus according to the present invention, the initialization signal is a pulse signal generated when a second power source different from the first power source is activated while the first power source is activated or the first power source is deactivated.

The potential control device according to the present invention further includes an initialization unit for initializing a control signal using a second power source different from the first power source before the first power source is activated.

In the potential control device according to the present invention, the initialization unit is a switch for connecting or disconnecting the control signal and the second power source according to the potential of the first power source.

In the potential control device according to the present invention, the initialization unit further includes a bias setting unit for dropping the potential of the second power supply and providing it to one end of the switch.

In the potential control device according to the present invention, the switch further includes an initialization switch for connecting or disconnecting the first terminal and the second terminal according to an initialization signal of a second power source different from the first power source.

The semiconductor device according to the present invention includes a lead to which a first power is applied and a plurality of semiconductor chips, wherein at least one of the plurality of semiconductor chips is connected to a first terminal and a lead electrically connected to or separated from the lead. Block the current path between the first terminal and a second terminal having a potential lower than that of the first power supply, and when the lead is disconnected from the first terminal, the potential of the first terminal to a potential lower than that of the first power supply. And a potential control device including a control unit for setting.

In the semiconductor device according to the present invention, the controller includes a switch for connecting or disconnecting the first terminal and the second terminal according to a control signal; And a switch for outputting a control signal for controlling the connection between the first terminal and the second terminal when the external terminal is connected to the first terminal and the first terminal and the second terminal when the external terminal is disconnected from the first terminal. It includes a control unit.

In the semiconductor device according to the present invention, the switch controller includes: a first controller configured to control a control signal to a first potential; A second control unit controlling the control signal to a second potential lower than the first potential; And a logic control unit for controlling the first control unit and the second control unit according to the potential of the first terminal.

In the semiconductor device according to the present invention, the first control unit further includes a bias setting unit that adjusts the potential of the control signal.

In the semiconductor device according to the present invention, the logic controller activates the first controller according to an initialization signal of power supplied to the first controller.

In the semiconductor device according to the present invention, the power source provided to the first control unit is a second power source different from the first power source.

In the semiconductor device according to the present invention, the power source provided to the first control unit is the same as the first power source.

In the semiconductor device according to the present invention, the initialization signal is a pulse signal generated when the power provided to the first controller is activated.

In the semiconductor device according to the present invention, the initialization signal is a pulse signal generated when a second power source different from the first power source is activated while the first power source is activated or the first power source is deactivated.

The semiconductor device according to the present invention further includes an initialization unit for initializing a control signal using a second power source different from the first power source before the first power source is activated.

In the semiconductor device according to the present invention, the initialization unit is a switch for connecting or disconnecting the control signal and the second power source according to the potential of the first power source.

In the semiconductor device according to the present invention, the initialization unit further includes a bias setting unit for dropping the potential of the second power supply and providing it to one end of the switch.

In the semiconductor device according to the present invention, the switch further includes an initialization switch for connecting or disconnecting the first terminal and the second terminal according to an initialization signal of a second power source different from the first power source.

In the semiconductor device according to the present invention, at least one of the plurality of semiconductor chips includes two or more potential control devices, and the first terminal of each of the potential control devices is independently connected or separated from the leads.

The semiconductor device according to the present invention further includes an activation controller for activating at least one of the plurality of semiconductor chips by comparing an externally input signal with a first potential of each of the plurality of semiconductor chips.

In the semiconductor device according to the present invention, each of the plurality of semiconductor chips further includes an activation control unit configured to compare the control signal input from the outside with the first potential and determine whether to activate each of them.

The signal input from the outside of the semiconductor device according to the present invention is all or part of the address signal.

In the semiconductor device according to the present invention, the potential of the first terminal is set to a chip address.

The present invention provides a potential control device for setting a potential of a terminal depending on whether it is connected to a power source. The potential control device according to the present invention can prevent a waste of power by blocking the formation of a current path between the terminal to which the power is applied and the ground terminal while the power is applied to the terminal. Therefore, the semiconductor device including the potential control device according to the present invention can also reduce power consumption, thereby improving power efficiency.

1 is a circuit diagram showing a conventional potential control device.
2 is a semiconductor device including a conventional potential control device.
3 is a circuit diagram showing a potential control device according to a first embodiment of the present invention.
4 is a circuit diagram showing a potential control device according to a second embodiment of the present invention.
Fig. 5 is a circuit diagram showing a potential control device according to a third embodiment of the present invention.
6 is a timing diagram showing one operation of the potential control device shown in FIG. 5;
FIG. 7 is a timing diagram showing another operation of the potential control device shown in FIG. 5; FIG.
8 is a block diagram showing a semiconductor device according to a fourth embodiment of the present invention.
9 is a block diagram showing a semiconductor device according to the fifth embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention. The following description is provided for the purpose of explanation of the invention and is not intended to limit the scope of the invention.

3 is a circuit diagram showing the potential control device 100 according to the first embodiment of the present invention.

The potential control device 100 according to the present exemplary embodiment includes a first terminal CON, a switch 110, and a switch controller 120.

The first terminal CON is connected to or separated from an external terminal (not shown) connected to the first power supply VCCQ. In one embodiment, the external terminal may be a lead of the semiconductor package. In one embodiment, the lead and the first terminal may be fixed by wire soldering or the like. However, other embodiments may control whether the external terminal is connected to the first terminal, for example, by programming a nonvolatile memory device such as a ROM or a flash memory and controlling the switch by a signal output from the nonvolatile memory device. .

The switch 110 has a second terminal (eg, a ground terminal) having a second potential (eg, a ground potential) lower than that of the first terminal CON and the first power supply VCCQ according to the control signal DISCH. (GND)) controls whether or not the electrical connection between. In this embodiment, the switch 110 includes an NMOS transistor. When the control signal DISCH applied to the gate is at the high level, the NMOS transistor connects the first terminal CON to the second terminal, and when the control signal DISCH applied to the gate is at the low level, the switch is connected to the first terminal. CON) and the second terminal GND.

The switch controller 120 may include a first controller 121 for controlling the control signal DISCH to a first potential (for example, a power supply potential VCCI), and a second potential lower than the first potential to be controlled. For example, a second control unit 122 for controlling the ground potential) and a logic control unit 123 for controlling the first control unit 121 and the second control unit 122 according to the potential of the first terminal CON. .

When the output of the logic controller 123 is at a low level, the first controller 121 is turned on to activate the control signal DISCH to a high level. As a result, the switch 110 is turned on to pull down the potential of the first terminal CON to the ground potential. In the present embodiment, the logic controller 120 is supplied with a second power source VCCI different from the first power source VCCQ through the first control unit 121.

Here, the second power source VCCI refers to an internal power source that receives a power source VCC different from the first power source VCCQ from an outside of a device (for example, a semiconductor device) and changes a potential level therein. Both VCC and VCCI may be referred to as a second power source different from the first power source VCCQ, but VCCI is referred to as a second power source for the purpose of unification of the description.

In the present embodiment, the first control unit 121 includes a PMOS transistor. In addition, the first controller 121 may further include a diode-connected NMOS transistor to adjust the potential level of the control signal DISCH.

When the output of the logic controller 123 is at a high level, the second controller 122 is turned on to deactivate the control signal DISCH to a low level. As a result, the switch 110 is turned off to block the current path between the first terminal CON and the ground terminal GND. In the present embodiment, the second control unit 122 includes an NMOS transistor.

The logic controller 123 controls the first controller 121 and the second controller 122 according to the potential of the first terminal CON. In the present embodiment, the logic controller 123 includes an inverter that receives a signal of the first terminal CON and a NOR gate that receives an output and an initialization signal POR of the inverter.

As is well known, the power-on reset signal used as the initialization signal POR is a pulse signal generated when the power source (second power source (VCCI) in this embodiment) is activated at a high level. Maintain a low level in the normal state when activated to a high level.

First, the first power source VCCQ and the second power source VCI will be described based on the normal state in which both are activated to a high level. In this case, since the initialization signal POR maintains a low level, the output of the logic controller 123 becomes the same as the logic level of the first terminal CON. In this case, the logic controller 123 of the present embodiment may be viewed as a simple buffer.

If the first terminal CON is connected to an external terminal connected to the first power supply VCCQ, the second control unit 122 is turned on so that the control signal DISCH becomes low level, and as a result, the switch 110 is cut off. . Therefore, the current path is blocked between the first terminal CON and the second terminal (for example, the ground terminal GND) while the potential of the first terminal CON is fixed at a high level, thereby preventing unnecessary waste of current. can do.

If the first terminal CON is not connected to an external terminal (not shown), the potential of the first terminal CON may be affected by an initial state. The initial state is set by an initialization signal POR that generates a high level pulse at the moment the second power supply VCCI is activated. That is, when the initialization signal POR is at the high level, the output of the logic controller 123 is at a low level. As a result, the PMOS transistor of the first controller 121 is turned on to set the control signal DISCH to the high level. Accordingly, the switch 110 is turned on to pull down the potential of the first terminal CON to the ground potential. That is, the potential of the first terminal CON is initialized to the low level.

As described above, since the initialization signal POR is at the low level when the second power supply VCCI is already activated at the high level, the output of the logic controller 123 is at the same low level as the logic level of the first terminal CON. As a result, the first controller 121 is turned on and the switch 110 is turned on so that the potential of the first terminal CON is maintained at a low level. That is, when the first terminal CON is not connected to the external terminal, the potential of the first terminal CON is maintained at a low level.

As described above, the control signal DISCH is activated to the high level in the period in which the initialization signal POR maintains the high level, thereby initializing the first terminal CON. Such an operation may occur while the first terminal CON is connected to an external terminal connected to the first power supply VCCQ. If it is assumed that the first power supply VCCQ is activated first as compared to the second power supply VCI, the ground terminal is connected to the ground terminal from the first terminal CON through the switch 110 while the initialization signal POR maintains a high level. Current flows.

The period in which the initialization signal POR maintains a high level is very short, and the amount of current consumed at that moment is also very small. However, by slightly lowering the potential of the control signal DISCH, the current consumed through the switch 110 may be further reduced. In this embodiment, the potential of the control signal DISCH is lowered by using an NMOS transistor diode-connected to the first control unit 110 of the switch control unit 120. At the same time or separately, a method of reducing the turn-on current of the NMOS transistor may be used by adjusting the channel width and length of the NMOS transistor of the switch 110.

4 is a circuit diagram showing a potential control device 100 according to a second embodiment of the present invention. In the second exemplary embodiment, the first power source VCCQ is applied to the first control unit 121 of the switch control unit 120 instead of the second power source VCCI. The basic operation is the same as that of the first embodiment except that the power-on reset signal INIT of the first power supply VCCQ is used instead of the power-on reset signal POR of the VCCI.

The initialization signal INIT, which is a power-on reset signal for the first power supply VCCQ while the first power supply VCCQ is activated, maintains a low level.

If the first terminal CON is connected to the first power supply VCCQ through an external terminal (not shown), the logic controller 123 outputs a high level to turn on the second controller 122 and as a result, a control signal. (DISCH) is activated to turn off the switch (110). Therefore, the current path between the first terminal CON and the ground terminal GND is blocked.

If the first terminal CON is not connected to the external terminal, the potential of the first terminal CON maintains a low level, which is an initial value, in the same manner as described in the first embodiment.

When the first power supply VCCQ is activated, the initialization signal INIT forms a high level pulse to perform an initialization operation. In this case, if the first terminal CON is connected to an external terminal (not shown) connected to the first power supply VCCQ, the control signal DISCH may be at a high level and current may flow through the switch 110. .

However, the duration of the pulse is short, so the amount of current is very small. However, the amount can be further reduced by lowering the level of the control signal DISCH. In this embodiment, the potential of the control signal DISCH is lowered by adding a diode-connected NMOS transistor to the first switch 121 of the switch controller 120. In addition, the turn-on current may be reduced by adjusting the channel width and length of the NMOS transistor in the switch 110.

5 is a circuit diagram showing a potential control device 100 according to a third embodiment of the present invention.

The third embodiment adds some configurations to the second embodiment. For example, the third embodiment further includes an initialization unit 130 and an initialization switch 112. Although the initialization unit 130 and the initialization switch 112 are both shown in the third embodiment, an embodiment including only one of the two may be possible.

The initialization unit 130 receives a second power source VCI different from the first power source VCCQ and initializes the control signal DISCH. The initialization unit 130 activates the potential of the control signal DISCH to a high level by using the second power source VCI that is activated before the first power source VCCQ in a period in which the first power source VCCQ is deactivated. Initializes the potential of one terminal CON to a low level.

The initialization switch 112 is turned on according to the initialization signal POR generated when the second power source VCCI is activated. Accordingly, the potential of the first terminal CON may be initialized to a low level. However, if the first power supply VCCQ in the activated state is provided to the first terminal CON, the switch 112 may be turned on instantaneously by a pulse of the initialization signal POR, and current may flow, but the pulse is high. Since the current path is cut except for the leveled section, the amount of current consumed is very small. In this case, in order to reduce the amount of current consumed, the turn-on current of the NMOS transistor 112 may be designed to be small.

In the present embodiment, the initialization signal INIT is the same as the power-on reset signal generated in the period in which the first power source VCCQ is activated to the high level as in the second embodiment. However, according to the design needs, the power-on reset signal, which is a pulse signal generated when the first power supply VCCQ is activated to the high level as the initialization signal INIT, and the second power supply in the state where the first power supply VCCQ is activated. A signal obtained by synthesizing a power-on reset signal, which is a pulse signal generated in a section in which VCCI is activated, may be used. In any case, there is no difference in the operation of the potential control device according to the present embodiment in the normal state in which all powers are activated.

6 and 7 are timing diagrams showing the operation of the third embodiment of the present invention. FIG. 6 illustrates a case where the first power source VCCQ is activated later than the second power source VCCCI, and FIG. 7 illustrates a case where the first power source VCCQ is activated earlier than the second power source VCCCI. 6 and 7, "SHORT" indicates a case where the first terminal CON is connected to an external terminal, and "OPEN" indicates a case where the first terminal CON is not connected to the external terminal.

The operating principle of the potential control device according to the third embodiment is as described above. Hereinafter, the operation of the potential control device according to the third embodiment of the present invention will be described with reference to FIGS. 6 and 7.

FIG. 6 is a timing diagram illustrating a case in which the second power source VCI is activated before the first power source VCCQ.

First, when the second power supply VCI is activated while the first power supply VCCQ is not activated, a high level pulse of the power on reset signal POR is generated. At this time, the initialization switch 112 is turned on to initialize the first terminal CON to a low level. The initialization switch 112 is turned off while the power on reset signal POR transitions to a low level. In addition, as the second power is activated, the initialization unit 130 is turned on so that the control signal DISCH maintains a high level so that the first terminal CON is initialized to a low level. In this state, when the first power VCCQ is activated, the initialization unit 130 is turned off.

As the first power source VCCQ is activated, a high level pulse of the initialization signal INIT occurs, and the output of the logic controller 123 becomes a low level in a section in which the initialization signal INIT is at a high level. 121 is turned on to maintain the control signal DISCH at a high level.

If the first terminal CON is in the "SHORT" state, the first power supply VCCQ of a high level is continuously supplied to the first terminal CON, and as a result, the logic controller 123 continuously outputs a high level to generate a first level. 2 The control unit 122 is turned on to maintain the control signal DISCH at a low level. This state persists until the first power supply VCCQ is deactivated to a low level. That is, while the activated first power source VCCQ is being supplied to the first terminal CON (A), the switch 110 may maintain a turn-off state to waste unnecessary current.

If the first terminal CON is in the " OPEN " state, the output of the logic controller 123 becomes low by the potential of the first terminal CON initialized to the low level and the low level initialization signal INIT. As a result, the first control unit 121 maintains the turned-on state so that the control signal DISCH maintains a high level. Accordingly, the switch 110 is turned on to set the potential of the first terminal CON to a low level.

FIG. 7 is a timing diagram illustrating a case where the first power source VCCQ is activated prior to the second power source VCI.

First, when the first power supply VCCQ is activated, a high level pulse of the initialization signal INIT is generated. At this time, the output of the logic controller 123 transitions to the low level, thereby turning on the first controller 121, and as a result, the control signal DISCH is controlled to the high level, thereby turning on the switch 110.

Therefore, if the first terminal CON is in the "SHORT" state, a current path through the NMOS transistor 111 is formed between the first terminal CON and the ground terminal GND during the high level period of the initialization signal INIT. Can be. However, the period at which the pulse stays high is short, resulting in very low current consumption. In this case, the current flowing through the NMOS transistor 111 may be reduced by lowering the potential level of the control signal DISCH through the NMOS transistor diode-connected to the first controller 121. In addition, the width and length design of the channel may be changed such that the turn-on current of the NMOS transistor 111 is reduced.

While the first power source VCCQ maintains the active state after the initialization signal INIT falls to the low level (A), the logic controller (B) is operated by the high level potential of the first terminal CON in the same manner as described above. The 123 outputs a high level signal and accordingly maintains the control signal DISCH at a low level to turn off the switch 110 to cut off the current path between the first terminal CON and the ground terminal GND. Current consumption is prevented.

If the first terminal CON is in the " OPEN " state, the output of the logic controller 123 becomes low level by the potential of the first terminal CON initialized to the low level and the low level initialization signal INIT. The first controller 121 maintains the turned-on state, and as a result, the control signal DISCH maintains a high level, thereby maintaining the potential of the first terminal CON at a low level through the NMOS transistor 111.

In the period in which the first power source VCCQ is deactivated to the low level after the period A and the second power source VCCI is activated, the control signal DISCH is set to the high level by the initialization unit 130 and thus the first terminal CON is removed. The switch 111 sets the potential to a low level.

8 is a block diagram showing a fourth embodiment of the present invention. A fourth embodiment of the present invention relates to a semiconductor device 2000 including semiconductor chips 1000 and 1000 'including potential control devices 100 and 100' according to the present invention.

This is basically the same as the conventional semiconductor device described in FIG. However, the fourth embodiment differs from the prior art in that the potential control device according to the present invention is used as the potential control devices 100 and 100 'rather than the conventional potential control device.

Since the potential control device according to the present invention has been described in detail through Examples 1 to 3, repeated description thereof will be omitted. When the power supply voltage is applied to the leads 1 and 2 (2001, 2002) of the semiconductor device 2000 according to the present invention by using the potential control devices 100, 100 'according to the present invention, the terminal A is at a low level. Keep it. In addition, the terminal A 'maintains a high level and at the same time, a current path is blocked between the terminal A' and the ground terminal, thereby consequently preventing current consumption of the semiconductor device 2000.

In the fourth embodiment, the potential control devices 100 and 100 'may be used to set chip addresses of the semiconductor chips 1000 and 1000'. However, the functions of the potential control devices 100 and 100 'are not limited thereto. For example, the potential control apparatus 100, 100 ′ according to the present invention may be used to determine whether to activate an option that can be set for each semiconductor chip or semiconductor device. Here, the type of option may exist in various ways depending on the embodiment.

9 is a block diagram showing a fifth embodiment of the present invention.

The semiconductor device 2000 according to the fourth embodiment includes a plurality of semiconductor chips 1000 and 1000 ′, each semiconductor chip 1100 having one pad circuit 1100 (or one potential control device 100). Includes only. This means that the semiconductor chips 1000 and 1000 ′ according to the fourth embodiment may have only one bit of chip address.

In contrast, the semiconductor device 2000 according to the fifth embodiment includes a plurality of semiconductor chips 1000 and 1000 ′, and each of the semiconductor chips 1000 includes a plurality of pad circuits 1100 ₁ and 1100 ₂ (or a plurality of potentials). Control device 100 ₁ , 100 ₂ ). Each of the plurality of pad circuits in one semiconductor chip may be independently connected to or separated from one lead to set a multi-bit chip address A ₁ A ₂ . By increasing or decreasing the number of pad circuits therein, the number of bits of the chip address can be increased or decreased.

As such, in the fifth embodiment, the potential control devices 100 ₁ and 100 ₂ may be used to set the chip address of the semiconductor chip 1000. However, the function of the potential control device 100 ₁ , 100 ₂ is not necessarily limited thereto. The potential control device 100 ₁ , 100 ₂ according to the present invention can be used to determine, for example, whether to activate an option that can be set for each semiconductor chip or semiconductor device. Here, the type of option may exist in various ways depending on the embodiment.

Common to the fourth and fifth embodiments, the pad circuit and the lead of the semiconductor device may be permanently fixed by wire soldering, but through a switch in which a connection between the lead and the pad circuit is determined through a programmable nonvolatile memory device. May be connected.

In addition, the semiconductor chip 1000 according to the present invention includes an activation control unit capable of determining whether to activate the semiconductor chip by comparing a chip address set according to a potential of terminals in a pad circuit with a part or all of an externally input address signal ( Not shown). This can prevent power waste by deactivating semiconductor chips that do not need to be used.

In some embodiments, the activation controller may be separately included outside the semiconductor chip. In this case, the activation control unit compares the chip address with some or all of the address signals provided from the outside of the semiconductor device, including a mapping table that receives the chip address from all the semiconductor chips or stores the mapping relationship between the chip address and the semiconductor chip. Only semiconductor chips that need to be used can be activated.

Since the above-described activation control unit can be easily implemented by a person skilled in the art, a detailed embodiment will be omitted.

The present invention has been disclosed by describing various embodiments of the present invention with reference to the drawings. Since the scope of the present invention is defined by the claims, the scope of the present invention is not limited to the embodiments described above. In addition, equivalents that can be easily modified or changed by those skilled in the art from the claims should be considered to be included in the scope of the present invention.

110: switch
120: switch control unit
121: first control unit
122: second control unit
123: logic controller
130: initialization unit
131: initialization switch
1, 100: potential control device
11, 1100: pad circuit
10, 1000: semiconductor chip
20, 2000: semiconductor device

Claims (31)

A first terminal electrically connected to or disconnected from an external terminal connected to the first power source; and
Interrupts the current path between the first terminal and a second terminal having a potential lower than that of the first power source when the external terminal is connected to the first terminal, and when the external terminal is separated from the first terminal. Control unit for setting the potential of the first terminal to a potential lower than the potential of the first power supply
Potential control device comprising a. The apparatus of claim 1,
A switch connecting or disconnecting the first terminal and the second terminal according to a control signal; And
Blocking between the first terminal and the second terminal when the external terminal is connected to the first terminal, and controls to connect the first terminal and the second terminal when the external terminal is separated from the first terminal A switch controller for outputting the control signal
Potential control device comprising a. The method of claim 1, wherein the switch control unit
A first control unit controlling the control signal to a first potential;
A second controller for controlling the control signal to a second potential lower than the first potential;
Logic control unit for controlling the first control unit and the second control unit according to the potential of the first terminal
Potential control device comprising a. The potential control device of claim 3, wherein the first controller further comprises a bias setting unit configured to adjust the potential of the control signal. The potential control device of claim 3, wherein the logic control unit activates the first control unit according to an initialization signal of power supplied to the first control unit. 6. The potential control device of claim 5, wherein the power source is a second power source different from the first power source. 6. The potential control device of claim 5, wherein the power source is the same as the first power source. The method according to claim 5, wherein the initialization signal
And a pulse signal generated when the power supplied to the first controller is activated. The method of claim 7, wherein the initialization signal
And a pulse signal generated when a second power source different from the first power source is activated while the first power source is activated or the first power source is deactivated. The method according to claim 2,
And an initialization unit configured to initialize the control signal by using a second power source different from the first power source before the first power source is activated. The method of claim 10, wherein the initialization unit
And a switch for connecting or disconnecting the control signal and the second power source in accordance with the potential of the first power source. The method of claim 11, wherein the initialization unit
And a bias setting unit for dropping the potential of the second power supply and providing it to one end of the switch. The method of claim 2, wherein the switch
And an initialization switch for connecting or disconnecting the first terminal and the second terminal according to an initialization signal of a second power source different from the first power source. A lead to which the first power source is applied;
Multiple semiconductor chips
Including, but at least one of the plurality of semiconductor chips
A first terminal electrically connected to or separated from the lead; and
Interrupts the current path between the first terminal and a second terminal having a potential lower than that of the first power source when the lead is connected to the first terminal and the first terminal when the lead is separated from the first terminal. To set the potential of to a potential lower than that of the first power source
Potential control device comprising a
. The method of claim 14, wherein the control unit
A switch connecting or disconnecting the first terminal and the second terminal according to a control signal; And
Blocking between the first terminal and the second terminal when the external terminal is connected to the first terminal, and controls to connect the first terminal and the second terminal when the external terminal is separated from the first terminal A switch controller for outputting the control signal
. The method of claim 14, wherein the switch control unit
A first control unit controlling the control signal to a first potential;
A second controller for controlling the control signal to a second potential lower than the first potential;
Logic control unit for controlling the first control unit and the second control unit according to the potential of the first terminal
. The semiconductor device of claim 16, wherein the first controller further comprises a bias setting unit configured to adjust a potential of the control signal. The semiconductor device of claim 16, wherein the logic controller activates the first controller according to an initialization signal of power supplied to the first controller. The semiconductor device according to claim 18, wherein the power source is a second power source different from the first power source. The semiconductor device of claim 18, wherein the power source is the same as the first power source. The method of claim 18, wherein the initialization signal is
And a pulse signal generated when power supplied to the first controller is activated. The method of claim 20, wherein the initialization signal is
And a pulse signal generated when a second power source different from the first power source is activated while the first power source is activated or the first power source is deactivated. 16. The method of claim 15,
And an initialization unit configured to initialize the control signal by using a second power different from the first power before the first power is activated. The method of claim 23, wherein the initialization unit
And a switch connecting or disconnecting the control signal and the second power supply in accordance with the potential of the first power supply. The method of claim 24, wherein the initialization unit
And a bias setting unit for dropping a potential of the second power supply and providing it to one end of the switch. The method of claim 15, wherein the switch
And an initialization switch for connecting or disconnecting the first terminal and the second terminal according to an initialization signal of a second power source different from the first power source. The method of claim 14, wherein at least one of the plurality of semiconductor chips
And at least two of the potential control devices, wherein the first terminal of each of the potential control devices is independently connected or separated from the lead. The method according to claim 14,
An activation control unit for activating at least one of the plurality of semiconductor chips by comparing an externally input signal with a potential of the first terminal of each of the plurality of semiconductor chips.
Further comprising: The method of claim 14, wherein each of the plurality of semiconductor chips
Activation control unit for determining whether to activate the respective by comparing the potential of the first terminal and the signal input from the outside
Further comprising: 30. The semiconductor device according to claim 28 or 29, wherein the externally input signal is all or part of an address signal. The semiconductor device according to claim 14, wherein a potential of the first terminal indicates a chip address of the semiconductor chip.

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