JP4723278B2 - Semiconductor integrated circuit device and semiconductor integrated circuit system - Google Patents

Description

  The present invention relates to high-speed operation of a semiconductor integrated circuit device and a semiconductor integrated circuit system.

  2. Description of the Related Art In recent years, semiconductor integrated circuit devices and semiconductor integrated circuit systems have been highly integrated and reduced in power consumption with the miniaturization of mounted semiconductor elements such as transistors. However, as high integration and low power consumption progress, a through current (leakage current) in a semiconductor integrated circuit occupies a large weight of system power consumption.

Therefore, a technique for changing the switching timing of the transistor in order to reduce the through current is disclosed, for example, in Patent Document 1 below.
JP 63-169120 A

  In the conventional method, switching timing is set at the design stage. For this reason, when setting the switching timing, the margin is estimated in advance. However, if the margin is too large, the operation speed may be reduced.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit device and a semiconductor integrated circuit system that have a high operation speed.

  A semiconductor integrated circuit device according to the present invention includes a sample circuit for monitoring a through current at the time of transistor switching, a non-overlap circuit for outputting an output signal for switching the sample circuit, A current detection circuit that detects a through current at the time of switching and a reference current value of the through current are set. The current value detected by the current detection circuit is compared with the reference current value, and a comparison result is obtained. A current comparison circuit for outputting to the non-overlap circuit.

  According to the present invention, the non-overlap circuit can be adjusted so as to output an output signal for switching at a timing such that the through current of the sample circuit becomes a value corresponding to the reference current value. Therefore, it is not necessary to set the switching timing at the design stage as in the conventional method. For this reason, when setting the switching timing, it is not necessary to estimate the margin in advance, and there is no possibility that the operation speed is lowered due to an excessive margin. That is, according to the present invention, a semiconductor integrated circuit device having a high operating speed can be obtained.

  The non-overlap circuit is configured to set a delay time for an output signal for switching based on the comparison result output from the current comparison circuit, or to set a transition time of the output signal for switching. It is preferable to further include a buffer to be set.

  Thus, the switching timing of the sample circuit can be adjusted by setting a delay time or a transition time.

  The non-overlap circuit includes both the delay circuit and the buffer. The delay circuit and the buffer are used for the switching so that the average power supply current value becomes the smallest when the power supply current is supplied. If the delay time and the transition time of the output signal are set, a power consumption reduction effect can be obtained.

  Each of the delay circuit and the buffer includes a plurality of transistors connected in parallel, and the channel widths and channel lengths of the plurality of transistors are different from each other, and each of the delay circuit and the buffer includes each of the plurality of transistors. The delay time or transition time of the output signal for the switching may be set by selecting at least one of them.

  Each of the delay circuit and the buffer may include a transistor, and the delay time or transition time of the output signal may be set by changing the substrate potential of the transistor.

  The reference current value may be set according to a power supply voltage, a temperature condition, and a frequency of an input signal to the non-overlap circuit.

  If the storage means for storing the delay time or transition time of the output signal for switching is further provided, the delay time or transition time of the output signal for switching is stored in the storage means in advance. There is no need to operate the current detection circuit and the current comparison circuit. Therefore, it is possible to reduce the time until the switching timing of the sample circuit is adjusted, and further the power consumption of the entire semiconductor integrated circuit device.

  A reference phase difference of an input signal to the sample circuit is set, and further includes a phase difference comparison circuit that detects a phase difference of the input signal to the sample circuit, and the phase difference comparison circuit is connected to the sample circuit. A configuration may be adopted in which the phase difference of the input signal is adjusted to be the same as the reference phase difference.

  The phase difference comparison circuit may be configured such that the reference phase difference is set from the outside.

  The current detection circuit may be configured to calculate a difference between the current value detected by the current detection circuit and the reference current value and adjust a phase difference of an input signal to the sample circuit according to the difference. .

  The current detection circuit may be configured such that the reference current amount is set from the outside.

  A limiter circuit for limiting the phase difference comparison circuit may be provided so that the phase difference of the input signal to the sample circuit does not exceed a set value.

  The semiconductor integrated circuit system of the present invention includes the sample circuit, a non-overlap circuit that is connected to the sample circuit and outputs an output signal for switching the sample circuit, and is connected to the sample circuit. A current detection circuit that detects a through current at the time of switching, and a current value that is connected to the current detection circuit and detected by the current detection circuit is compared with a preset reference current value, and the comparison result is A semiconductor integrated circuit including a current comparison circuit for outputting to the overlap circuit; and an internal circuit to which an output signal of the non-overlap circuit is input.

  According to the present invention, even when there are a plurality of internal circuits, the switching timing of each internal circuit can be set in the semiconductor integrated circuit. That is, according to the present embodiment, it is not necessary to provide a semiconductor integrated circuit for setting the switching timing in each internal circuit, and space saving of the semiconductor integrated circuit system can be achieved.

  The semiconductor integrated circuit system may further include a monitor for power consumption, work load, or average current value.

  The semiconductor integrated circuit may be configured to operate according to an operation mode of the semiconductor integrated circuit system.

  According to the present invention, a semiconductor integrated circuit device and a semiconductor integrated circuit system having a high operating speed are provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in order to avoid the complexity of description, the component common to each embodiment is shown with the same referential mark.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the semiconductor integrated circuit device of this embodiment.

  As shown in FIG. 1, the semiconductor integrated circuit device 100 of this embodiment includes a non-overlap circuit 3, a sample circuit 11, a current detection circuit 9, a counter 10, and a current comparison circuit 20. .

  Non-overlap circuit 3 includes input terminals 1 and 2 and output nodes 12 and 13. An enable signal (hereinafter referred to as an EN signal) is input to the input terminal 1, and an input signal for performing an actual circuit operation is input to the input terminal 2. A more detailed configuration of the non-overlap circuit 3 will be described later.

  The sample circuit 11 includes, for example, a P-channel transistor 7 (hereinafter referred to as P-type transistor 7), an N-channel transistor 8 (hereinafter referred to as N-type transistor 8), and an output terminal 5. The source of the P-type transistor 7 is connected to the power supply (VDD), and the drain is connected to the drain of the N-type transistor 8. The source of the N-type transistor 8 is grounded (GND), and the output terminal 5 is connected to the drains of the P-type transistor 7 and the N-type transistor 8. In each transistor, the substrate and the source are connected, and the output nodes 12 and 13 of the non-overlap circuit 3 are connected to the gates of the P-type transistor 7 and the N-type transistor 8 of the sample circuit 11, respectively. ing. Note that the configuration of the sample circuit 11 is not limited to that of the present embodiment, and any configuration may be used as long as the output terminal 5 is precharged by the input from the output node 12 or discharged by the input from the output node 13. .

  The current detection circuit 9 receives a current between the N-type transistor 8 of the sample circuit 11 and GND, and outputs current detection information.

  The current comparison circuit 20 creates comparison reference information from the comparison reference information input from the input terminal 19 and the current detection information from the current detection circuit 9, and outputs a delay control signal a and a buffer control signal b.

  The counter 10 is configured to receive the delay control signal “a” and the buffer control signal “b” output from the current comparison circuit 20, count those inputs, and output the delay control signal “A” and the buffer control signal “B”. ing.

    FIG. 2 is a diagram illustrating the configuration of the non-overlap circuit 3. As shown in FIG. 2, the non-overlap circuit 3 includes NAND circuits 37a and 37b, a NOR circuit 38, INV circuits 39a and 39b, delay circuits 35 and 36, and buffers 31 and 34, and an input terminal 1 EN1 signal, input signal at input terminal 2, delay control signal A from counter 10, and buffer control signal B are input and output from output nodes 12 and 13.

  As shown in FIG. 2, the NAND circuit 37a has an input side connected to the input terminals 1 and 2 and an output side connected to the input side of the NAND circuit 37b and the NOR circuit 38.

  The NOR circuit 38 and the NAND circuit 37b have an input side connected to the NAND circuit 37a and an output side connected to the output nodes 12 and 13 through the buffers 31 and 34, respectively. Further, both the NOR circuit 38 and the NAND circuit 37b branch on the output side in front of the buffers 31 and 34 and are connected to the input sides of the delay circuits 35 and 36, respectively.

  The delay circuits 35 and 36 are connected to the input sides of the NAND circuit 37b and the NOR circuit 38 through the INV circuits 39a and 39b, respectively, so that the delay control signal A is input thereto.

  The non-overlap circuit 3 can adjust the timing of output signals from the output nodes 12 and 13 by setting the delay circuits 35 and 36 and the buffers 31 and 34.

  Next, the configuration of the delay circuits 35 and 36 and the buffers 31 and 34 will be described with reference to FIG.

  FIGS. 3A and 3B show the configurations in the delay circuits 35 and 36 in FIG. As shown in FIGS. 3A and 3B, the delay circuit 35 (36) has a configuration in which a plurality of delay units 311 are connected in series.

  As shown in FIG. 3A, the delay unit 311 has a configuration in which a P-type transistor 314 for precharging the output terminal 38, an N-type transistor 313 for discharging, and a P-type transistor 314 by an input signal to the gate. It is composed of a plurality of stages including a P-type select transistor 315 that selects application of the power supply voltage VDD and an N-type select transistor 312 that selects application of the ground potential GND to the N-type transistor 313 by an input signal to the gate. That is, the delay unit 311 includes an inverter including a P-type transistor 314 and an N-type transistor 313, and a P-type select transistor 315 and an N-type select transistor 312 connected to the inverter. Note that the channel lengths of the P-type transistor 314 and the N-type transistor 313 are different among the inverters. Further, the input terminal 30 is connected in common to the gates of the P-type transistors 314 and N-type transistors 313, and the output terminal 38 is commonly connected to the drains of the P-type transistors 314 and N-type transistors 313. It is connected.

  Signals input to the gates of each P-type select transistor 315 and each N-type select transistor 312 are controlled by select signals PA, PB,... PE and NA, NB,. . Note that the inverted signal of PA is input to NA, which is the same for each stage.

  With the above configuration, the delay circuit 35 (36) of this embodiment selects at least one or more inverters having different channel lengths with the select signals PA, PB,... PE and NA, NB,. Thus, the channel length of the transistors constituting the delay unit 311 is changed, and thereby the timing between the input signal to the input terminal 316 and the output signal from the output terminal 318 is adjusted.

  FIG. 3C is a timing chart of the input signal to the input terminal 30 and the output signal from the output terminal 38 of the delay unit 311 of this embodiment. As shown in FIG. 3C, a certain delay time (delay value D) is generated between the input terminal 30 and the output terminal 38. The delay value D can be adjusted as described above by the select signals PA, PB,... PE and NA, NB,. If the channel widths of the P-type transistor 314 and the N-type transistor 313 are different between the inverters, the select signals PA, PB,... PE and NA, NB,. It is possible to change the channel width of the inverter constituting the delay unit 311.

  In the present embodiment, the circuit configurations of the delay circuits 35 and 36 are shown in FIG. 3, but any circuit having a configuration in which the channel length and the channel width can be controlled by signals may be used. The circuit configurations of the delay circuits 35 and 36 shown in the present embodiment are the same as the configurations of the buffers 31 and 34. By changing the channel length and channel width of each transistor of the inverter, the circuit configuration shown in FIG. The slope of the output signal, that is, the transition time (rise time and fall time) of the output signal is changed.

  Next, the operation of the semiconductor integrated circuit device 100 of this embodiment will be described with reference to FIG.

(Timing generation step)
With the configuration of the non-overlap circuit 3 in FIG. 1, when the EN signal is “H”, the non-overlap circuit 3 operates, and between the output nodes 12 and 13 according to the input signal input to the input terminal 2. To generate output signals whose timings are shifted from each other, and output them to the sample circuit 11.

(Current detection step)
The output signals of the output nodes 12 and 13 generated in the timing generation step are input to the gates of the P-type transistor 7 and the N-type transistor 8 of the sample circuit 11, and the output signals of the input output nodes 12 and 13 are input. Is output to the output terminal 5. At this time, in the sample circuit 11, a through current that flows through the source of the N-type transistor 8 during switching is input to the current detection circuit 9. The current detection circuit 9 detects a through current and outputs detected current detection information.

(Current comparison step)
The current detection information detected in the current detection step is compared by the current comparison circuit 20 based on the comparison reference information input from the input terminal 19, and the comparison result information is used as the delay control signal a and the buffer control signal b. Output.

(Counter step)
The counter 10 counts the delay control signal a and the buffer control signal b output from the current comparison step, and outputs the converted information (counter value) as the delay control signal A and the buffer control signal B.

(Feedback step)
The delay control signal A output in the counter step is input to the delay circuits 35 and 36 in the non-overlap circuit 3, the buffer control signal B is input to the buffers 31 and 34, and the delay capability (delay value D) , Adjust the buffer capacity (tilt of the output signal).

  By performing the above-described timing generation step, current detection step, current comparison step, counter step, and feedback step for several cycles, the delay circuit 35 in the non-overlap circuit 3 at an optimal timing at which no through current flows through the sample circuit 11. And 36, buffers 31 and 34 are adjusted. That is, according to the semiconductor integrated circuit device 100 of the present embodiment, it is not necessary to set the switching timing at the design stage as in the conventional method. For this reason, when setting the switching timing, it is not necessary to estimate the margin in advance, and there is no possibility that the operation speed is lowered due to an excessive margin. That is, according to this embodiment, a semiconductor integrated circuit device with low power consumption and high operating speed can be obtained.

  Furthermore, in the semiconductor integrated circuit device 100 of this embodiment, after the counter 10 is set so that no through current flows, the power consumption is suppressed by stopping the operations of the current detection circuit 9 and the current comparison circuit 20. Can do.

  Next, a typical configuration of the current comparison step will be described.

  In the current comparison step, as comparison reference information, a correlation between conditions such as power supply voltage, temperature, and frequency of the input signal and a reference through current value (reference current value) is input, and current detection information and the current comparison circuit 20 are input. Compare with. This makes it possible to compare with the reference current value that is optimum for the power supply voltage, temperature, frequency of the input signal, and the like. Note that the reference current value can be set for any one condition such as the power supply voltage, temperature, and frequency of the input signal, and can be set in consideration of a plurality of conditions.

  FIG. 4 is a table showing the correlation between the power supply voltage and the reference current value. For example, if the table shown in FIG. 4 is prepared and set as comparison reference information, the reference current value can be set according to the power supply voltage. As a result, it is possible to reduce the through current with high efficiency according to the power supply voltage. Also, the same effect can be obtained by preparing a table similar to FIG. 4 for the temperature and the frequency of the input signal and setting the reference current value.

  In this embodiment, the delay circuits 35 and 36 and the buffers 31 and 34 are adjusted (delay buffer feedback method) in the feedback step. However, the present invention is not limited to this, and the delay circuits 35 and 36 are controlled. It is also possible to adopt a configuration that only feeds back (delay feedback scheme), a configuration that feeds back only to the buffers 31 and 34 (buffer feedback scheme), or the like.

  In this embodiment, the delay buffer feedback method is employed, and there are a plurality of combinations of delay circuit and buffer settings that can be set at the same timing with respect to the timing settings of the output nodes 12 and 13. Therefore, if the delay circuit and the buffer are adjusted so that the power supply current value is optimized, an effect of reducing power consumption can be obtained. Therefore, if the power supply current is monitored for each combination of the delay circuit and the buffer, and the combination with the smallest average power supply current is determined, the timing setting of the output nodes 12 and 13 with the least through current is performed, and the power consumption is reduced. Further reduction in power consumption can be realized by determining the least delay and buffer combination.

(Embodiment 2)
In the present embodiment, another configuration of the delay circuits 35 and 36 and the buffers 31 and 34 of the semiconductor integrated circuit device 100 of the first embodiment will be described with reference to FIG.

  FIGS. 5A and 5B show the configurations in the delay circuits 35 and 36 in FIG. As shown in FIGS. 5A and 5B, the delay circuit 35 (36) has a configuration in which a plurality of delay units 335 are connected.

  The delay unit 335 includes a P-type transistor 331 that precharges the output terminal 338 to the power supply voltage VDD by an input signal from the input terminal 330, and an N-type transistor 332 that discharges to the ground potential GND by the input signal from the input terminal 330. Further, a node 336 is connected to the substrate of the P-type transistor 331, and a node 337 is connected to the substrate of the N-type transistor 332.

  FIG. 5C is a timing chart of an input signal to the input terminal 330 and an output signal from the output terminal 338 of the delay unit 335 of the present embodiment. The delay unit 335 changes the voltage applied to the nodes 336 and 337 (that is, the substrate potential) to change the delay time or slope of the output signal from the output terminal 338 with respect to the input signal as shown in FIG. Can be adjusted. Using this action, the delay circuits 35 and 36 can adjust the timing of the input 316 and the output 318.

(Embodiment 3)
FIG. 6 is a block diagram showing the configuration of the semiconductor integrated circuit system of this embodiment. As shown in FIG. 6, the semiconductor integrated circuit system 200 of this embodiment includes a replica circuit 41 and an internal circuit 42.

  The replica circuit 41 includes a non-overlap circuit 3, a sample circuit 11, a current detection circuit 9, a counter 10, and a current comparison circuit 20. That is, the replica circuit 41 has the same configuration as the semiconductor integrated circuit device 100 of the first embodiment. Therefore, the replica circuit 41 is provided with each internal circuit 42 (here, an inverter circuit is provided as an example) through the wiring 43 provided to branch to the output nodes 12 and 13 of the non-overlap circuit 3 (see FIG. 1). In contrast, an individual output signal is output to the gate of each of the P-type transistor and the N-type transistor in each internal circuit 42 at an optimal timing at which no through current flows.

  According to the configuration of the present embodiment, even when there are a plurality of internal circuits 42, the switching timing of each internal circuit 42 can be set by one replica circuit 41. That is, according to the present embodiment, it is not necessary to provide the semiconductor integrated circuit device 100 shown in the first embodiment for setting the switching timing in each internal circuit 42, and the semiconductor integrated circuit system 200 can be saved. Space can be achieved.

(Embodiment 4)
The semiconductor integrated circuit device of this embodiment will be described with reference to FIG.

  FIG. 7A is a block diagram showing the configuration of the semiconductor integrated circuit system 300 of this embodiment. As shown in FIG. 7A, the semiconductor integrated circuit system 300 according to this embodiment includes a replica circuit 41 ′ and an internal circuit 42.

  The replica circuit 41 ′ has a configuration in which selectors 514 and 518, a nonvolatile memory 51, and a register 52 are further provided in the replica circuit 41 of the third embodiment. The selector 514 has an input side connected to the output nodes 12 and 13 (see FIG. 1) of the non-overlap circuit 3 and an output side connected to the wiring 43 and the sample circuit 11. The selector 518 has an input side connected to the counter 10 and the output side of the register 52, and an output side connected to the non-overlap circuit 3.

  The input side of the nonvolatile memory 51 is branched and connected to the output side to the selector 518 of the counter 10, and the output side is connected to the input side of the register 52. The output side of the register 52 is connected to the selector 518.

  Also in this embodiment, the replica circuit 41 ′ penetrates each internal circuit 42 (here, an inverter circuit is provided as an example) through a wiring 43 that is branched from the output nodes 12 and 13. An individual output signal is output to the gate of each of the P-type transistor and N-type transistor in each internal circuit 42 at an optimal timing at which no current flows.

  Next, the operation of the semiconductor integrated circuit system 300 of this embodiment will be described with reference to FIGS. 7 (a) and 7 (b). FIG. 7B is a flowchart showing the operation of the semiconductor integrated circuit system 300 of this embodiment. Here, it is assumed that the semiconductor integrated circuit system 300 shown in FIG. 7A is configured by one chip.

(Counter value determination step)
First, the semiconductor integrated circuit system 300 operates the replica circuit 41 ′ by setting the EN signal of the non-overlap circuit 3 to “H” in the shipping test. As a result, the counter 10 is set at a timing when no through current flows through the sample circuit 11, and the counter value is determined.

(Non-volatile memory writing step)
After the counter value determining step, the counter value determined by the counter 10 is written from the counter 10 to the nonvolatile memory 51 when the write mode to the nonvolatile memory is active.

(Non-volatile memory reading step)
When the read mode of the nonvolatile memory is active, the counter value written in the nonvolatile memory writing step is read from the nonvolatile memory 51 and the data is stored in the register 52.

(Register read step)
After the nonvolatile memory reading step, the data stored in the register 52 is read from the register 52 when the register reading mode is active, and the data is transferred to the selector 518.

(Selector switching step)
After the register reading step, the selector 518 enables the output side of the register 52 and transfers it to the non-overlap circuit 3. At the same time, the selector 514 enables the output to the wiring 43 and the output signal from the non-overlap circuit 3 is transferred to the internal circuit 42.

  As shown in FIG. 7B, the test flow from the counter value determination step to the nonvolatile memory writing step is a test flow that operates at the time of the test, and the steps from the nonvolatile memory reading step to the selector mode step are performed when the circuit is actually operated. Assuming that the actual operation flow is to be performed, the test flow is performed in the shipping test, and the actual operation flow is performed in the actual operation, so that the counter value of the counter 10 is transferred to the nonvolatile memory 51 during the actual operation of the internal circuit 42. Therefore, it is not necessary to operate the sample circuit 11, the current detection circuit 9, the current comparison circuit 20, and the counter 10. Therefore, until the replica circuit 41 ′ outputs an output signal to each internal circuit 42 through the wiring 43 provided to branch to the output nodes 12 and 13 at an optimal timing at which no through current flows. Can save time. Furthermore, the power consumption of the entire semiconductor integrated circuit system 300 can be reduced.

  In the present embodiment, the sample circuit 11, the current detection circuit 9, the current comparison circuit 20, and the counter 10 need only be provided at the time of the shipping test, and are not required during actual operation. Therefore, the sample circuit 11, the current detection circuit 9, the current comparison circuit 20, and the counter 10 may be externally added only during the shipping test. In this case, since it is not necessary to provide the sample circuit 11, the current detection circuit 9, the current comparison circuit 20, and the counter 10 in the semiconductor integrated circuit system 300, it is possible to save the space of the semiconductor integrated circuit system 300. .

(Embodiment 5)
In the present embodiment, applications suitable for the first to fourth embodiments will be described.

  A typical application of the first to fourth embodiments includes a system including any one of the semiconductor integrated circuit device 100 and the replica circuit 41 or 41 'according to the above embodiment.

  First, as a first application example, the above system monitors the power consumption of the system, and when the power consumption reaches a reference value or higher, the semiconductor integrated circuit device 100, the replica circuit 41 or 41 ′ is operated. By providing the power monitor and operating the semiconductor integrated circuit device 100, it is possible to reduce the power consumption of the system and increase the operation speed.

  As a second application example, the actual work amount of the system including the semiconductor integrated circuit device 100 and the replica circuit device 41 or 41 ′ of the above embodiment is monitored, and the semiconductor integrated circuit device 100 and the replica are selected according to the system work amount. A system work amount monitor for operating either the circuit 41 or 41 ′ may be provided.

  As a third application example, as shown in FIG. 8, there is a system 62 including the semiconductor integrated circuit device 100 of the above embodiment, a system control device 63, and a system operation mode input terminal 64. In the system 62, the system operation mode signal is simultaneously input to the semiconductor integrated circuit device 100. Therefore, the semiconductor integrated circuit device 100 may be configured to operate only in the specific system operation mode by operating the EN signal in the semiconductor integrated circuit device 100 as “H” for the specific system operation mode. As a result, the power consumption and the operation speed of the system 62 can be switched as necessary to achieve higher efficiency, lower power consumption, and higher operation speed as the entire system.

  The average current value of the system including the semiconductor integrated circuit device 100 and the replica circuit device 41 or 41 ′ of the above embodiment is always monitored, and the semiconductor integrated circuit device 100 and the replica circuit 41 are always set so that the average current value is not more than the reference value. Alternatively, a system current value monitor for operating either one of 41 'may be provided.

(Embodiment 6)
FIG. 9 is a block diagram showing the configuration of the semiconductor integrated circuit device of this embodiment.

  As shown in FIG. 9, the semiconductor integrated circuit device 400 of this embodiment includes a non-overlap circuit 3, a phase difference comparison circuit 71, a sample circuit 11, a current detection circuit 9, a current comparison circuit 20, and a counter. 10 and a selector 72. The non-overlap circuit 3, the sample circuit 11, the current detection circuit 9, the current comparison circuit 20, and the counter 10 have the same configuration as that of the first embodiment.

  The phase difference comparison circuit 71 outputs a delay buffer control signal Q corresponding to the input signals from the output nodes 12 and 13 from the non-overlap circuit 3 to the selector 72.

  The selector 72 enables the delay buffer control signal Q when the select mode is active, and inputs the delay control signal A and the buffer control signal B to the non-overlap circuit 3.

  According to this embodiment, the phase difference comparison circuit 71 detects the phase difference between the output nodes 12 and 13 output from the non-overlap circuit 3 and compares it with a preset reference phase difference. The delay buffer control signal Q is output according to the result. Since the delay buffer control signal Q is fed back to the non-overlap circuit 3 through the selector 72, the phase difference between the output nodes 12 and 13 output from the non-overlap circuit 3 can be quickly set to the reference phase difference. .

  For this reason, it is not necessary to set the switching timing at the design stage as in the conventional method. Therefore, when setting the switching timing, it is not necessary to estimate the margin in advance, and there is no possibility that the operation speed is lowered due to an excessive margin. That is, according to this embodiment, a semiconductor integrated circuit device having a high operation speed can be obtained. Furthermore, also in this embodiment, after the counter 10 is set so that no through current flows, power consumption can be suppressed by stopping the operations of the current detection circuit 9 and the current comparison circuit 20.

  In addition, the phase difference between the output nodes 12 and 13 output from the non-overlap circuit 3 is input to the phase difference comparison circuit 71 in advance to generate the delay buffer control signal Q and fed back to the non-overlap circuit 3. Good. In this case, it is possible to feed back to the non-overlap circuit 3 based on the phase difference between the output nodes 12 and 13.

(Embodiment 7)
FIG. 10 is a block diagram showing the configuration of the semiconductor integrated circuit device of this embodiment.

  As shown in FIG. 10, the semiconductor integrated circuit device 500 of this embodiment includes a non-overlap circuit 3, a sample circuit 11, a current detection circuit 9, and a current comparison circuit 20 ′. The configuration is almost the same as that of the semiconductor integrated circuit device 100 of the first embodiment. However, the difference is that a current comparison circuit 20 'is provided instead of the current comparison circuit 20, and a counter is not provided.

In the semiconductor integrated circuit device 500, the current comparison circuit 20 ′ calculates a difference in current value between the comparison reference information input from the input terminal 19 and the current detection information, and outputs the delay control signal A and the buffer control signal B. Created and fed back to the non-overlap circuit 3. The delay control signal A and the buffer control signal B created from the difference between the current values determine the magnitude of the phase difference between the output nodes 12 and 13. For example, the delay control signal A is set so that the phase difference between the output signals from the output nodes 12 and 13 increases when the current value difference is large, and the phase difference decreases when the current value difference is small. The current comparison circuit 20 ′ is set so as to generate the buffer control signal B. Of course, if necessary, the phase difference between the output signals from the output nodes 12 and 13 is reduced when the current value difference is large, and the phase difference is increased when the current value difference is small. The current comparison circuit 20 ′ may be set so as to generate the delay control signal A and the buffer control signal B. With the above configuration, the semiconductor integrated circuit device 500 according to the present embodiment can quickly set the optimum output node 12 and The switching timing of the output signal from 13 can be set.

  Further, the current comparison circuit 20 'may be configured such that a current value difference is input to the current comparison circuit 20' in advance, and the switching timing of the output signals from the output nodes 12 and 13 can be adjusted from the outside as needed. In this case, even after the semiconductor integrated circuit device 500 is manufactured, the switching timing of the output signals from the output nodes 12 and 13 can be adjusted.

(Embodiment 8)
FIG. 11 is a block diagram showing the configuration of the semiconductor integrated circuit device of this embodiment.

  As shown in FIG. 11, the semiconductor integrated circuit device 600 of this embodiment includes a non-overlap circuit 3, a phase difference comparison circuit 71, a limiter setting circuit 73, a sample circuit 11, a current detection circuit 9, and a current. The comparison circuit 20, the counter 10, and the selector 72 are configured, and have substantially the same configuration as that of the semiconductor integrated circuit device 400 of the sixth embodiment. However, it differs from the semiconductor integrated circuit device 400 of the above embodiment only in that the limiter setting circuit 73 is connected to the phase difference comparison circuit 71.

  The limiter setting circuit 73 outputs a limiter setting value and controls the phase difference comparison circuit 71 so that the phase difference between the output nodes 12 and 13 does not exceed the limiter setting value.

  In the semiconductor integrated circuit device 600 of the present embodiment, there is no operation failure due to excessive phase difference.

  The limiter setting circuit 73 may have a configuration in which the limiter set value is set in advance or can be set from the outside at any time. In particular, in a configuration in which the limiter set value can be set from the outside at any time, the limiter set value can be set at any time after the semiconductor integrated circuit device 600 is manufactured.

  The present invention is useful for semiconductor integrated circuit devices and semiconductor integrated circuit systems that require high-speed operation.

FIG. 1 is a block diagram illustrating the configuration of the semiconductor integrated circuit device according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a non-overlap circuit. FIGS. 3A and 3B are diagrams showing the configuration in the delay circuits 35 and 36 in FIG. FIG. 4 is a table showing the correlation between the power supply voltage and the reference current value. 5A and 5B show the configuration of the delay circuit shown in FIG. FIG. 6 is a block diagram illustrating the configuration of the semiconductor integrated circuit device according to the third embodiment. FIG. 7A is a block diagram showing the configuration of the semiconductor integrated circuit device according to the fourth embodiment. FIG. 7B is a flowchart showing the operation of the semiconductor integrated circuit device according to the fourth embodiment. FIG. 8 is a diagram showing a system which is an application example of the present invention. FIG. 9 is a block diagram showing the configuration of the semiconductor integrated circuit device according to the sixth embodiment. FIG. 10 is a block diagram illustrating a configuration of the semiconductor integrated circuit device according to the seventh embodiment. FIG. 11 is a block diagram illustrating a configuration of a semiconductor integrated circuit device according to the eighth embodiment.

Explanation of symbols

1, 2, 19, 316, 330 Input terminal 3 Non-overlap circuit 5, 318, 338 Output terminal 7 P-type transistor 8 N-type transistor 9 Current detection circuit 10 Counter 11 Sample circuit 12, 13 Output node 20, 20 ′ Current Comparison circuit 31, 34 Buffer 35, 36 Delay circuit 37a, 37b NAND circuit 38 NOR circuit 39a, 39b INV circuit 41, 41 'Replica circuit 42 Internal circuit 43 Wiring 51 Non-volatile memory 52 Register 62 System 63 System controller 64 System operation Mode input terminal 71 Phase difference comparison circuit 72 Selector 73 Limiter setting circuit 100, 400, 500, 600 Semiconductor integrated circuit device 200, 300 Semiconductor integrated circuit system 311, 335 delay unit 312 N-type select transistor 313, 32 N-type transistors 314,331 P-type transistor 315 P-type select transistor 336, 337 nodes 514, 518 selector

Claims (14)

A sample circuit to be monitored for through current at the time of transistor switching, a non-overlap circuit that outputs an output signal for switching the sample circuit, and a through current at the time of switching of the sample circuit are detected. A current detection circuit;
Are set reference current value of the through current, compares the current value and the reference current value detected by the current detection known circuits, and a current comparison circuit for outputting a comparison result to the non-overlap circuit Prepared ,
The non-overlap circuit includes a delay circuit that sets a delay time for the output signal for switching based on the comparison result output from the current comparison circuit, and a transition time of the output signal for switching. A semiconductor integrated circuit device including a buffer to be set . The semiconductor integrated circuit device according to claim 1 ,
Upper SL delay circuit and the buffer, so that the power supply current value of the average is minimized when the supply current is supplied to set a delay time of the output signal and the transition time for the switching, the semiconductor integrated circuit apparatus. The semiconductor integrated circuit device according to claim 1 ,
Each of the delay circuit and the buffer includes a plurality of transistors connected in parallel, and the channel widths and channel lengths of the plurality of transistors are different from each other, and by selecting at least one of the plurality of transistors A semiconductor integrated circuit device that adjusts the delay time or transition time of the output signal for the switching of the sample circuit by changing the capability. The semiconductor integrated circuit device according to claim 1 ,
Each of the delay circuit and the buffer includes a transistor, and adjusts a delay time or a transition time of an output signal by changing a substrate potential of the transistor. In the semiconductor integrated circuit device according to any one of claims 1 to 4 ,
The semiconductor integrated circuit device, wherein the reference current value is set according to a power supply voltage, a temperature condition, and a frequency of an input signal to the non-overlap circuit. The semiconductor integrated circuit device according to claim 1,
A semiconductor integrated circuit device comprising storage means for storing a delay time or transition time of an output signal for switching. The semiconductor integrated circuit device according to claim 1,
The reference phase difference of the input signal to the sample circuit is set, further comprising a phase difference comparison circuit for detecting the phase difference of the input signal to the sample circuit,
The semiconductor integrated circuit device, wherein the phase difference comparison circuit adjusts so that a phase difference of an input signal to the sample circuit is the same as the reference phase difference. The semiconductor integrated circuit device according to claim 7 ,
In the phase difference comparison circuit, the reference phase difference is set from the outside. The semiconductor integrated circuit device according to claim 1,
The current sensing circuit calculates the difference between the current value detected by the current detection latch circuit and the reference current value, adjusting the phase difference between the input signal to the sampling circuit in accordance with the difference, a semiconductor integrated Circuit device. The semiconductor integrated circuit device according to claim 9 ,
The semiconductor integrated circuit device, wherein the current detection circuit has the reference current amount set from the outside. The semiconductor integrated circuit device according to claim 7 ,
A semiconductor integrated circuit device further comprising a limiter circuit for limiting the phase difference comparison circuit so that a phase difference of an input signal to the inverter circuit does not exceed a set value. In the semiconductor integrated circuit device according to claim 1 to 11,
An internal circuit to which the output signal of the non-overlap circuit is input;
A semiconductor integrated circuit system. The semiconductor integrated circuit system according to claim 12 , wherein
A semiconductor integrated circuit system, further comprising a monitor for any one of power consumption, work load, and average current value of the semiconductor integrated circuit system. The semiconductor integrated circuit system according to claim 12 , wherein
The semiconductor integrated circuit system operates according to an operation mode of the semiconductor integrated circuit system.

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