KR20130112520A - Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for a fringe field switching mode liquid crystal display device and a method for fabricating the same are provided to improve display quality by preventing spots. CONSTITUTION: A common line is parallel to a gate line. A data line (130) defines a pixel region. A thin film transistor is adjacent to each pixel region. A pixel electrode (150) is in contact with the drain electrode of a thin film transistor. A common electrode (160) comprises a first opening part that is shaped like a bar.

Description

Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, to improve display quality by suppressing color shift generation by allowing a pixel region to have a multi-domain structure, and to apply a common voltage evenly to the entire display region. The present invention relates to an array substrate for a fringe field switching mode liquid crystal display device and a method of manufacturing the same.

Generally, a liquid crystal display device is driven by using optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

At present, an active matrix liquid crystal display (AM-LCD: hereinafter referred to as liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and video realization capability, It is attracting attention.

The liquid crystal display device includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display device, The liquid crystal is driven to have excellent properties such as transmittance and aperture ratio.

However, liquid crystal driving by an electric field which is applied to the upper and lower sides has a disadvantage that the viewing angle characteristic is not excellent.

Accordingly, a fringe field switching mode liquid crystal display (LCD) has been proposed in which a liquid crystal is operated by a fringe field to overcome the disadvantages.

1 is a plan view of one pixel area in an array substrate of a conventional fringe field switching mode liquid crystal display device.

As illustrated, a plurality of gate wires 43 extend in one direction on the array substrate 41 of the conventional fringe field switching mode liquid crystal display device, and a plurality of gate wires 43 intersect with the plurality of gate wires 43. The pixel region P is defined, and a plurality of data lines 51 are formed.

In addition, each of the plurality of pixel regions P is connected to the data line 51 and the gate line 43 defining the gate electrode 45, the gate insulating layer (not shown), the semiconductor layer (not shown), and the like. The thin film transistor Tr, which is a switching element including the source and drain electrodes 55 and 58, is formed.

In addition, each pixel region P is formed with a plate-shaped pixel electrode 60 electrically connected to the drain electrode 58 of the thin film transistor Tr through the drain contact hole 59.

In addition, a common electrode 75 is formed on the entire display area in which the plurality of pixel areas P is formed to overlap the plate-shaped pixel electrode 60 corresponding to each pixel area P. A plurality of openings op has a straight bar shape corresponding to each of the pixel areas.

In this case, the common electrode 75 is formed on the entire surface of the display area, but a portion corresponding to one pixel area P is indicated by a dotted line.

In the conventional fringe field switching mode liquid crystal display array substrate 41 having such a configuration, the pixel electrode 60 having the plate shape and the front surface of the display area are provided for each pixel area P and each pixel area. A voltage is applied to the common electrode 75 having a plurality of openings in the shape of a straight bar to form a fringe field.

However, in the liquid crystal display device (not shown) having the array substrate 41 for a fringe field switching mode liquid crystal display device having the above-described structure, each pixel region P forms a single domain so that the user Due to the change in the azimuth angle toward (not shown), a color shift phenomenon occurs in which color inversion occurs near a specific azimuth angle, for example, 0 °, 90 °, 180 °, and 270 °, which is a factor that degrades display quality. .

In addition, in the liquid crystal display device (not shown) having the array substrate 41 for a fringe field switching mode liquid crystal display device having the above-described structure, a common electrode 75 made of a transparent conductive material is formed on the entire display area. Is formed.

Therefore, when a common voltage is input from the driving circuit board (not shown) mounted in the non-display area by contacting the common electrode through an FPC or the like, the common voltage is normally applied to a portion adjacent to the driving circuit board (not shown). Although a voltage drop is generated due to the internal resistance of the common electrode 75 made of a transparent conductive material, a common voltage having a magnitude smaller than the applied common voltage is applied to the center portion of the display area, thereby causing a driving error or crossover. There is a problem in that torque is generated and display quality is degraded.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional array substrate for fringe field switching mode liquid crystal display devices. The present invention improves display quality by suppressing color shift, and furthermore, the common voltage at the center and the edge of the display area is improved. It is an object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device having a structure capable of reducing the occurrence of deviation and improving the aperture ratio.

In an array substrate for a fringe field switching mode liquid crystal display according to the present invention for achieving the above object, an odd-numbered line and an even-numbered line are first spaced apart from each other on a substrate on which a display area for displaying an image is defined. A gate wiring having a spacing and formed in pairs and having a second spacing larger than the first spacing; A common wiring formed in parallel with the gate wiring at a central portion of the second spacing; A data line formed to define a pixel area intersecting the gate line and the common line; A thin film transistor provided adjacent to each pixel area at the first spacing interval; A pixel electrode formed in contact with the drain electrode of the thin film transistor for each pixel region; A plurality of bars having a bar shape formed on an entire surface of the display area with an insulating layer on the pixel area and having a bent portion at the center of each pixel area for each pixel area to be symmetrically bent up and down; And a common electrode having an opening, wherein one end of the common electrode and the common wire contact each other in a non-display area outside the display area.

In this case, the common wiring is 1/2 of the number of gate wirings.

The plurality of first openings positioned in adjacent pixel regions positioned above and below the common wiring may be disposed in opposite directions.

The data line may have a zigzag shape in the display area, and a portion corresponding to the first opening may be formed in parallel with the first opening, wherein the bent portion is one or three in each pixel area. When the bent portion is three, the angles of the second bent portion is greater than the angles of the first and third bent portions when the first, second, and third bent portions are sequentially defined. It is characterized in that the up and down symmetry based on the second bent portion.

The common electrode may have a second opening removed corresponding to each of the thin film transistors.

In addition, a first passivation layer is provided between the thin film transistor, the data line, and the pixel electrode, and includes a contact hole for exposing the thin film transistor. The source electrode of the thin film transistor exposed through the contact hole is provided. An island-shaped transparent conductive pattern and the pixel electrode are respectively formed on the drain electrode and the drain electrode, and the island-shaped transparent conductive pattern and the pixel electrode are spaced apart from each other in the contact hole.

In a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention, an odd-numbered line and an even-numbered line adjacent to each other on a substrate on which a display area for displaying an image is defined have a first spacing. And forming a pair of gate wirings so as to be arranged in pairs and having a second spacing interval larger than the first spacing interval, and simultaneously forming a common wiring parallel to the gate wiring in a central portion of the second spacing interval; Forming a gate electrode branched from the gate wiring at a spacing interval; Forming a data line on the gate line, the common line, and the gate electrode to intersect the gate line and the common line to define a pixel region through a gate insulating layer; Forming a first passivation layer on the front surface of the data line, the first passivation layer having a contact hole corresponding to the gate electrode; Forming a pixel electrode for each pixel region on the first passivation layer, and successively forming a source electrode and a drain electrode spaced apart from each other in the contact hole; A plurality of bars are formed on the front surface of the display area by interposing a second passivation layer on the pixel electrode, and having a bent portion at the center of each pixel area. And forming a common electrode having a first opening, wherein one end of the common electrode and the common wiring are in contact with each other in a non-display area outside the display area.

In this case, before the data line is formed, forming an active layer and an impurity amorphous silicon pattern on the gate insulating layer corresponding to each gate electrode, and the forming the data line may be formed on the impurity amorphous silicon pattern. And forming a metal pattern in a form branched from the data line, wherein forming the pixel electrode includes forming a transparent conductive pattern spaced apart from the pixel electrode on the metal pattern. And removing the metal pattern exposed between the conductive pattern and the pixel electrode and an impurity amorphous silicon pattern thereunder to form an ohmic contact layer below the source electrode and the drain electrode and the two electrodes.

The plurality of first openings positioned in adjacent pixel areas positioned above and below the common wiring may be formed such that the bent portions are located in opposite directions.

The data line may be formed to have a zigzag shape in the display area, and a portion corresponding to the first opening may be formed to be parallel to the first opening, and the bent portion may be formed within each pixel area. It is made of one or three, when the three bent portion, when sequentially defined as the first, second, third bent, the angle of the second bent portion is larger than the angle of the first and third bent portion, The first opening may be formed to be symmetrical with respect to the second bent portion.

The forming of the common electrode having the first opening may include forming a second opening removed corresponding to each of the thin film transistors.

The array substrate for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention has a shape in which a plurality of first openings provided in the common electrode corresponding to each pixel area are symmetrically bent with respect to the center of each pixel area. Each pixel area is formed to have a dual domain, thereby preventing color shift from a specific angle. Furthermore, the pixel areas are configured to be bent in a symmetrical direction between pixel areas adjacent to each other up and down. Different domains are formed not only inside but also between up and down neighboring pixel regions, thereby further preventing color shift.

In addition, by having three bent portions having different bend angles in each pixel area, and having the angle of the second bent portion positioned at the center thereof to be greater than the first and third bent portions positioned at both sides thereof, an external pressure can be applied. In this case, there is an effect of improving display quality by preventing uneven defects caused by collapse of domain boundaries and decreasing luminance.

In addition, the common wiring is formed of a low resistance metal material constituting the gate wiring, thereby minimizing the change of the common voltage at the center and the edge of the display area to suppress the crosstalk phenomenon, thereby improving display quality.

In addition, the common wirings are not formed for each pixel line, but are formed to be spaced apart by two pixel line distances, and are formed in pairs adjacent to each other in odd-numbered and even-numbered neighbors, and formed in the upper and lower pixel regions. The formation on the same line has the effect of improving the aperture ratio while forming common wiring.

1 is a plan view of one pixel area of an array substrate of a conventional fringe field switching mode liquid crystal display device;
FIG. 2 is a plan view of two pixel regions vertically positioned in an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.
3 is a cross-sectional view of a portion cut along the cutting line III-III of FIG.
FIG. 4 is a cross-sectional view of a portion cut along the line IV-IV of FIG. 2; FIG.
Figures 5a to 5i is a cross-sectional view of the manufacturing step for the part cut along the cutting line III-III of FIG.
6A to 6I are cross-sectional views of manufacturing steps for a portion cut along the cutting line IV-IV of FIG. 2.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a plan view of two pixel regions vertically positioned in an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. For convenience of description, an area in which a plurality of pixel areas P is formed is defined as a display area, and an area outside the display area is defined as a non-display area. In addition, a portion in which a thin film transistor, which is connected to each pixel region and controls a pixel electrode included in each pixel region, is formed is defined as a switching region.

As shown, a plurality of gate wirings 103 are formed extending in the first direction, and common wirings 108 are formed to be spaced apart from the gate wirings 103 in parallel with each other, and extend in the second direction. As a result, a plurality of data lines 130 are formed to define the plurality of pixel regions P by crossing the plurality of gate lines 103 and the common lines 108.

At this time, one of the most characteristic configurations of the array substrate 101 for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention is an even number adjacent to the odd-numbered gate wiring 103a of the gate wiring 103. The first gate lines 103b have a separation width smaller than the width in the longitudinal direction of the one pixel region P1 and P2 and are disposed adjacent to each other in pairs.

The common wiring 108 has a gap between the adjacent gate lines 103 in the longitudinal direction of the pixel regions P1 and P2 and corresponds to the boundary of the pixel regions P1 and P2. This feature is arranged.

Therefore, the common wiring 108 provided in the display area is 1/2 of the total number of gate wirings 103.

On the other hand, the array substrate 101 for a fringe field switching mode liquid crystal display according to an embodiment of the present invention is one by the arrangement structure of the gate wiring 103, the common wiring 108 and the data wiring 130 as described above The pixel regions P1 and P2 of each of the gate lines 103a or 103b and one common wiring 108 and the two wiring lines 103a or 103b and 108 that are arranged next to each other next to each other intersect with each other. It is defined as an area surrounded by two neighboring data lines 130.

On the other hand, in the array substrate 101 for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention, the data line 130 has a straight form in the display area in the straight down direction Instead of forming a zigzag shape, the curved portion BA is provided so as to be symmetrical at the center of each pixel region P1 and P2.

In this case, the bent portion BA provided in each of the pixel areas P1 and P2 has a sharp configuration to the left of the odd pixel line PL1 and a sharp configuration to the right of the even pixel line PL2. It is characterized by being. On the other hand, the configuration of the bent portion BA in the odd-numbered and even-numbered pixel lines PL2 and PL1 may be opposite to each other.

Further, the bent portion BA provided in each pixel region P1 and P2 may be formed of only one bent portion (not shown), or as shown in the drawing, the three bent portions BA (a1 and a2). , a3)).

On the other hand, when three bent portions a1, a2, and a3 are configured to correspond to the pixel regions P1 and P2, the first and third bent portions a1 and a3 are arranged in the first angle rather than the angle of bend. And an angle of the second bent portion a2 positioned between the third bent portions a1 and a3 has a larger value and has a larger angle corresponding to the central portion of each pixel region P1 and P2. May be achieved.

The configuration of the bent portion BA provided in the data line will be described in more detail when the planar shape of the first opening op1 provided in the common electrode 160 will be described later.

The gate line 103 and the data line 130 are adjacent to each of the pixel areas P1 and P2 and are connected to the gate electrode 105, the gate insulating layer (not shown), and the active of pure amorphous silicon. A thin film transistor Tr including a semiconductor layer (not shown) including a layer (not shown), an ohmic contact layer (not shown) of impurity amorphous silicon, and source and drain electrodes 133 and 136 spaced apart from each other are formed. .

At this time, in the array substrate 101 for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention, the thin film transistor Tr formed adjacent to each of the pixel regions P1 and p2 may be formed. Each pixel region connected to the odd-numbered gate line 103a (hereinafter referred to as odd pixel line PL1) and each pixel region connected to the even-numbered gate line 103b adjacent thereto (hereinafter, even-numbered pixel line PL2). Is spaced apart from the odd-numbered and even-numbered gate lines 103a and 103b by forming a first spacing that is smaller than the width of one pixel region P1 or P2 in the longitudinal direction. It is characterized by a configuration arranged alternately in the area CPLA.

Accordingly, the array substrate 101 for the fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention may correspond to the spaced area CPLA between the odd-numbered gate line 103a and the even-numbered gate line 103b. It is characterized in that a switching region associated with the vertically adjacent pixel regions P1 and P2 is provided.

In more detail, in the region surrounded by the two data lines 130 adjacent to each other and the odd-numbered and even-numbered gate lines 103a and 103b adjacent to each other, the pixel areas P1 and P2 respectively positioned on the upper side and the lower side. ) And the first and second thin film transistors Tr1 and Tr2 connected to each other are alternately provided. At this time, the first and second thin film transistor (Tr1, Tr2) adjacent to each other, the semiconductor layer more accurately the active layer (120a) is characterized in that formed in the form of islands.

Thus, the thin film transistors Tr1 and Tr2 are not provided inside the pixel areas P1 and P2, but are configured in the same line adjacent to each other between the pixel areas P1 and P2 that are adjacent to each other up and down. It has the effect of improving the aperture ratio.

On the other hand, inside the pixel regions P1 and P2 surrounded by the gate wiring 103, the common wiring 108, and the data wiring 130, a plate-shaped pixel electrode 150 of the thin film transistors Tr1 and Tr2 is formed. It is formed in contact with the drain electrode 136.

In addition, a plurality of first openings having a bar shape that is bent in correspondence with the plate-shaped pixel electrodes 150 formed in the pixel areas P may be formed in front of the display area including the plurality of pixel areas P. The common electrode 160 having op1) is formed. Although not shown in the drawing, the common electrode 160 extends to a part of the non-display area, and is electrically connected to the common wire 108 through a common contact hole (not shown) in the non-display area.

In this case, the common electrode 160 is formed in front of the display area, and the boundary is not shown in FIG. 2, in which only the planar shape of one pixel area P1 or P2 is shown. The pixel area P is denoted by the reference numeral 160 in the form of a dotted line.

At this time, as one of the most characteristic features of the present invention, a plurality of bar-shaped first openings formed corresponding to the plate-shaped pixel electrodes 150 formed in the pixel areas P1 and P2, respectively. (op) has a structure in which a virtual line is symmetrically bent with respect to the virtual line when a virtual line is drawn in parallel with the gate line 103 at a central portion of each pixel region P1 and P2. That is, the plurality of first openings op1 are formed to be parallel to the data lines 130 defining the pixel areas P1 and P2. Each of the plurality of first openings op1 provided in each pixel area is formed such that the ends thereof overlap the gate lines 105a and 105b and the common wiring 108, respectively.

Meanwhile, when the plurality of first openings op1 in the common electrode 160 are symmetrically bent in the pixel region P with respect to the central portion of the pixel regions P1 and P2, Since the directions of the main fringe fields at the upper and lower portions of the pixel regions P1 and P2 are different from each other, two domains D1 and D2 are formed in one pixel region P1 and P2.

In this case, the fringe field switching mode liquid crystal display (not shown) completed with the array substrate 101 having such a structure is located in different domains D1 and D2 in one pixel region P1 and P2. The movement of the liquid crystal is different, and finally, the arrangement of the long axes of the liquid crystal molecules is changed, thereby reducing the color shift phenomenon at a specific azimuth angle.

That is, for convenience of description, the domain region formed in the upper portion of the pixel regions P1 and P2 based on the center portion thereof is referred to as the first domain region D1 and the domain region formed in the lower portion is referred to as the second domain region D2. If defined, the azimuth angle at which color shift occurs in the first domain region D1 and the azimuth angle at which color shift occurs in the second domain region D2 are different, so that the respective domain regions D1 and D2 are color shifted. By developing compensation, the color shift phenomenon can be finally reduced.

Furthermore, the array substrate 101 for a fringe field switching mode liquid crystal display device according to an exemplary embodiment of the present invention includes data lines 130 defining respective pixel regions P1 and P2 provided with each of the plurality of first openings op1. ) Are formed to be parallel to each other, and the two domain regions D1 and D2 are provided in each of the pixel regions P1 and P2, and the pixel regions P1 and N that are adjacent to each other along the shape of the data line 130 are positioned. Another feature is that the directions of the bent portions of the first openings op1 in P2 are opposite to each other.

That is, for the pixel region P1 connected to the odd-numbered gate lines 103a, the bent portion BA in the center of each of the first openings op1 has a sharp shape to the left (or right), and the even-numbered gate lines ( Regarding the pixel region P2 connected to 103b, the bent portion BA at the center of the first opening op1 has a sharp shape to the right (or left), so that the pixel regions P1 and P2 are positioned up and down. In addition, it forms a different domain area, which further suppresses color inversion according to the position viewed by the user.

On the other hand, in the array substrate 101 for a fringe field switching mode liquid crystal display according to the embodiment of the present invention having such a configuration, a plurality of first openings op1 provided in each pixel region P1 and P2 are provided. Only one bent part (not shown) is provided in the center part BA, or three bent parts corresponding to the center part of each pixel area P1 and P2, that is, the first to third bent parts a1, a2, a3).

In this case, when the bent portion BA is formed of three bent portions a1, a2, and a3 in each of the pixel regions P1 and P2, the first and third bent portions a1 and a3 may be formed. It is characterized in that the bending angle of the second bending portion a2 positioned between the first and third bending portions a1 and a3 is larger, and between and between the first bending portion a1 and the second bending portion a2. The distance w1 between the two bent portions a2 and the third bent portion a3 is preferably about 10 µm to 20 µm.

In this case, the substantially first domain region D1 in each pixel region P becomes the region located above the second bent portion a1, and the second domain region D2 is the third bent portion a3. It is characterized by being a location area at the bottom. In this case, the area between the second bent portion a2 and the third bent portion a3 becomes a domain boundary region CA.

On the other hand, forming the first opening op1 so as to have three bent portions a1, a2 and a3 with respect to the center of each pixel region P1 and P2 in this way is an array having a single bent portion (not shown). In the case of a liquid crystal display device having a substrate, when external pressure is applied, the domain boundary in each of the pixel regions P1 and P2 collapses, thereby partially arranging the liquid crystals in the first domain region D1 and the second domain region D2. This can be done in the same direction. In this case, a partial luminance decrease occurs and is represented as a stain in the display area, and the stain caused by the external pressure may not be restored to its normal state even after the external pressure disappears, and may remain for a long time, resulting in poor image quality. In order to solve this problem, the angular difference between the domain boundaries within each pixel region P1 and P2 has a larger angular difference so that even if an external pressure occurs, unevenness is caused by the same initial arrangement of liquid crystal molecules due to the collapse of the domain boundary CA. This is to suppress the.

On the other hand, the first openings op1 formed in the first and second domain regions D1 and D2 are 7 degrees to 10 degrees in the clockwise or counterclockwise direction with respect to the normal line perpendicular to the gate wiring 103, respectively. It is preferable to form a first angle of the degree, and the domain boundary area CA, that is, between the first bend a1 and the second bend a2 and the second bend a2 and the third bend. Each first opening op located between (a3) preferably has a second angle of 15 to 30 degrees greater than the first angle.

Each of the first openings op may draw a virtual line parallel to the gate line 103 to penetrate the second bent portion a2 positioned at the center of each pixel area P. It is characterized by being formed to form a symmetrical structure as a reference.

In this case, a second opening op2 may be formed in the common electrode 160 so as not to overlap the thin film transistors Tr1 and Tr2 provided in each switching region. This is because the characteristics of the thin film transistors Tr1 and Tr2 may be degraded due to parasitic capacitance that may occur due to overlap of the thin film transistors Tr1 and Tr2 and the common electrode 160.

The array substrate 101 for the fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention having the planar configuration as described above is provided in the common electrode 160 corresponding to each pixel region P1 and P2. Each of the pixel regions P1 and P2 may implement the dual domain regions D1 and D2 by forming the first opening op1 of the pixel region P1 and P2 so as to be symmetrically bent with respect to the central portion of the pixel regions P1 and P2. There is an effect to prevent the color shift phenomenon at a specific angle, and furthermore, bent parts in the symmetrical direction between the pixel areas (P1, P2) adjacent to each other up and down, so that not only inside each pixel area (P1, P2) In addition, different domains are formed between the pixel areas P1 and P2 adjacent to each other up and down, thereby further preventing color shift.

In addition, each of the pixel regions P1 and P2 has three bent portions a1, a2 and a3 having different bend angles, and the angles of the second bent portions a2 positioned at the center thereof are located at both sides thereof. By having an angle greater than the first and third bent portions a1 and a3, the domain boundary CA is collapsed when an external pressure is applied, thereby preventing unevenness caused by a decrease in luminance, thereby improving display quality.

In addition, the common wiring 108 is formed of a low resistance metal material constituting the gate wiring 103, thereby minimizing the change of the common voltage at the center and the edge of the display area to suppress the crosstalk phenomenon, thereby improving display quality. There is.

Further, the common wiring 108 is not formed for each pixel line PL1 and PL2, but is formed by being spaced apart by two pixel lines and adjacent neighboring odd-numbered and even-numbered gate lines 103a and 103b are adjacent to each other. By forming a pair and forming the thin film transistors Tr1 and Tr2 provided in the upper and lower pixel regions P1 and P2 on the same line, it is possible to form the common wiring 108 while improving the aperture ratio.

Hereinafter, the cross-sectional structure of the array substrate for the fringe field switching mode liquid crystal display according to the embodiment of the present invention will be described.

FIG. 3 is a cross-sectional view of a portion taken along the cutting line III-III of FIG. 2, and FIG. 4 is a cross-sectional view of a portion taken along the cutting line IV-IV of FIG. 2. For convenience of description, a portion in which a thin film transistor, which is a switching element, is formed is defined as a switching region TrA.

As shown, the array substrate 101 for fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention is a metal material having low resistance on the transparent insulating substrate 101, for example, aluminum (Al). , One of aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi), extending in one direction and having a first spacing interval and odd and even gates A plurality of wirings (103a and 103b of FIG. 2) are formed in pairs and have a plurality of second intervals larger than the first spaced interval, and pass through the center portion between the pair of gate wirings (103a and 103b of FIG. 2). The common wiring 108 is formed in parallel with the gate wirings 103a and 103b of FIG. 2.

In addition, each odd area and the odd numbered gate wirings 103a and 103b adjacent to each other and having the first spacing interval on the insulating substrate 101 are disposed in each of the switching regions TrA. The gate electrode 105 is formed in a branched manner from the gate wiring 103a in FIG. 2 and the even-numbered gate wiring 103b in FIG.

Next, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is formed on the entire surface of the substrate 101 over the gate wiring 103, the common wiring 108, and the gate electrode 105. The gate insulating layer 110 is formed.

On the gate insulating layer 110, any one or two or more of a low resistance metal material, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi) The data line 130 is formed of a material, intersects with the gate line 103 in FIG. 2, and has a zigzag shape in front of the display area, and has one or three bent portions at the center of each pixel area P1 or P2. Formed. Since the specific form of the data line 130 has been described with reference to FIG. 2, which is a plan view, it will be omitted.

In addition, a semiconductor including an active layer 120a of pure amorphous silicon and an ohmic contact layer 120b of impurity amorphous silicon in the switching region TrA on the gate insulating layer 110, corresponding to the gate electrode 105. A layer 120 is formed, and a source electrode 133 connected to the data line 130 and a drain electrode 136 are spaced apart from the source layer 133 on the semiconductor layer 120.

In this case, the active layer 120a is exposed between the source and drain electrodes 133 and 136 spaced apart from each other, and the gate electrode 105 and the gate insulating layer 110 sequentially stacked in the switching regions TrA. ), The semiconductor layer 120, and the source and drain electrodes 133 and 136 form a thin film transistor Tr1 as a switching element.

An organic insulating material, for example, photo acryl having photosensitive properties, is formed on the entire surface of the substrate 101 on the data line 130 and the thin film transistor Tr1 to form a first protective layer 140 having a flat surface. It is. In this case, the first passivation layer 140 includes source and drain electrodes 133 and 136 spaced apart from each other in correspondence with the gate electrode 105 in the switching regions TrA, and the two electrodes 133 and 136. A contact hole 143 is formed to expose the active layer 120a exposed therebetween.

Next, each of the pixel areas P1 and P2 is in contact with the drain electrode 136 of the thin film transistor Tr1 on the first passivation layer 140 to form a transparent conductive material, for example, indium tin oxide (ITO). Or an indium-zinc-oxide (IZO), a plate-shaped pixel electrode 150 is formed.

In this case, the pixel electrode 150 and the drain electrode 136 are in direct contact with each other through the contact hole 143 provided in the first passivation layer 140. The pixel electrode 150 is made of the same material as the pixel electrode 150. An island-like transparent conductive pattern 152 is formed corresponding to the source electrode 133. The transparent conductive pattern 152 formed of the same material forming the pixel electrode 150 on the source electrode 133 is due to a manufacturing method, which will be described later.

Next, a second protective layer 155 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is disposed on the entire surface of the substrate 101 on the pixel electrode 150 and the transparent conductive pattern 152. It is being formed.

A common electrode 160 made of a transparent conductive material is formed on the entire surface of the display area on the second passivation layer 155. In this case, the common electrode 160 is provided with a plurality of first openings op1 having a bar shape that is bent to correspond to the pixel areas P1 and P2. One or three bent portions (not shown) are formed at the center of each of the pixel areas P1 and P2 in the plurality of bar-shaped first openings op1 formed for each pixel area P1 and P2. It is characterized in that it is provided, the configuration features of such a first opening (op1) has been described with reference to FIG. In addition, a second opening op2 may be further formed in the common electrode 160 to correspond to each of the switching regions TrA.

On the other hand, in the case of the array substrate 101 for a fringe field switching mode liquid crystal display device according to an embodiment of the present invention having the cross-sectional structure described above, in the common electrode 160 for each pixel region P1 and P2 in the drawing. The first openings op1 having a bar shape symmetrically bent at the center thereof are shown to be spaced apart from each other at equal intervals, but each pixel area P1, The first opening op1 corresponding to P2) may be variously modified and formed in an appropriate number within a range of about 2 to about 10.

Hereinafter, a method of manufacturing an array substrate for a fringe field switching mode liquid crystal display according to an embodiment of the present invention will be described.

FIGS. 5A to 5I are cross-sectional views illustrating manufacturing steps taken along the cutting line III-III of FIG. 2, and FIGS. 6A to 6I are manufacturing steps of the cutting parts taken along the cutting line IV-IV of FIG. 2. It is a process cross section.

First, as shown in FIGS. 5A and 6A, a metal material having low resistance on the transparent insulating substrate 101, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, A first metal layer (not shown) having a single layer or a multi-layer structure is formed by continuously depositing one or two or more materials of molybdenum (Mo) and molybdenum (MoTi).

Subsequently, patterning is performed by performing a mask process including photoresist coating, exposure using an exposure mask, development of the exposed photoresist, etching of the first metal layer (not shown), and a series of unit processes of strips of the photoresist. As a result, a plurality of gate wires 103a and 103b extending in one direction and having a first spacing interval and an odd-numbered and even-numbered line are paired and arranged at a second spacing interval larger than the first spacing interval are formed. And at the same time passing through a central portion of the separation region having the second separation interval between the pair of gate wirings 103a and 103b of FIG. 2 and paralleling the gate wirings 103a and 103b of FIG. 108). With this arrangement structure, the common wiring 108 is formed every two pixel regions P1 and P2 in the vertical direction, and the pair of gate wirings 103a and 103b of FIG. 2 are also formed every two pixel regions. It is a composition.

In addition to forming the common wiring 108 with the gate wirings 103a and 103b of FIG. 2, the adjacent odd-numbered and even-numbered gate wirings having the first spacing on the insulating substrate 101 and adjacent to each other are illustrated. Each of the switching regions TrA provided in the separation regions 103a and 103b of the second gate electrode in a form branched from the odd-numbered gate lines 103a in FIG. 2 and the even-numbered gate lines 103b in FIG. Form 105.

Next, as shown in FIGS. 5B and 6B, for example, an inorganic insulating material may be formed on the entire surface of the substrate 101 over the gate wirings 103a and 103b, the common wiring 108, and the gate electrode 105. The gate insulating layer 110 is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx).

5C and 6C, the pure amorphous silicon layer and the impurity amorphous silicon layer (not shown) are successively deposited by depositing pure amorphous silicon and impurity amorphous silicon on the gate insulating layer 110. The patterning process is performed by successive patterning to form an island-like active layer 120a in each of the switching regions TrA and an impurity amorphous silicon pattern having the same planar shape as the active layer 120b. 121).

In this case, the active layer 120a and the impurity amorphous silicon pattern 121 may be formed for each switching region TrA, or as shown in the drawing, or are adjacent to each other at odd intervals having a first spacing therebetween. The gate electrodes 105 branched from the gate lines 103a of FIG. 2 and the even-numbered gate lines 103b of FIG. 2 may be formed to be connected to the two adjacent switching regions TrA. have.

Next, as shown in FIGS. 5D and 6D, low-resistance metal materials such as aluminum (Al), aluminum alloy (AlNd), and copper are formed on the island-like active layer 120a and the impurity amorphous silicon pattern 121. (Cu), copper alloy, molybdenum (Mo), molybdenum (MoTi) by depositing any one or two or more materials to form a second metal layer (not shown) of a single layer or multi-layer structure, and proceeds to the mask process By patterning to form a data line 130 having a zigzag shape defining pixel areas P1 and P2 by crossing the gate lines 103a and 103b and the common line 108. In this case, since the planar shape of the data line 130 has been described above, it will be omitted.

At the same time, the metal pattern 132 is formed on the impurity amorphous silicon pattern 121 in each of the switching regions TrA in a form branched from the data line 130.

Next, as shown in FIGS. 5E and 6E, an organic insulating material, for example, photoacryl having photosensitive characteristics is coated on the entire surface of the data line 130 and the metal pattern 132, and the exposure is performed using an exposure mask. And developing and patterning the first protective layer 140 having a flat surface and a contact hole 143 exposing the metal pattern 132 in each of the switching regions TrA.

Next, as shown in FIGS. 5F and 6F, a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is disposed on the first protective layer including the contact hole. A layer of a transparent conductive material (not shown) is formed on the substrate to form a transparent conductive material layer, and a mask process is performed to pattern the pixel electrode 150 in each of the pixel regions P1 and P2. In this case, the pixel electrode 150 corresponds to the switching region TrA connected to each of the pixel regions P1 and P2 through the contact hole 143 provided in the first protective layer 140. It is characterized by contact with one end of the pattern 132.

At the same time, the transparent conductive material layer (not shown) is patterned so as to be spaced apart from the pixel electrode 150 in the upper portion of the metal pattern 132 in each switching region TrA, and more precisely the data line 130. The transparent conductive pattern 152 is formed in a portion adjacent to the feature. In this case, the pixel electrode 150 and the transparent conductive pattern 152 contacting the metal pattern 132 in the contact hole 143 may be spaced apart from each other.

Next, as illustrated in FIGS. 5G and 6G, the pixel electrode 150 formed spaced apart from each other on the metal pattern 132 of FIG. 5F in the contact hole 143 provided in the switching region TrA. ) And the metal pattern (132 in FIG. 5F) exposed between the transparent conductive pattern 152 and the transparent conductive pattern 152 by etching to expose the impurity amorphous silicon pattern (121 in FIG. 5F) and the source and drain electrodes 133 and 136 spaced apart from each other. ) In this case, the source electrode 133 is in a state of being connected to the data line 130.

Due to this process feature, in the fringe field switching mode liquid crystal display array substrate 101 according to the exemplary embodiment of the present invention, a transparent conductive pattern is formed on the source electrode 133 to be spaced apart from the pixel electrode 150. 152 is formed, and the pixel electrode 150 is formed on the drain electrode 136.

Next, in each switching region TrA, the impurity amorphous pattern (121 of FIG. 5F) exposed between the source electrode 133 and the drain electrode 136 is removed to expose the active layer 120a disposed under the impurity. Let's do it. In this case, the impurity amorphous pattern (not shown) forming a shape spaced apart from each other on the active layer 120a forms the ohmic contact layer 120b.

As a result of this process, the ohmic contact layer 120b spaced apart from the gate electrode 105, the gate insulating layer 110, and the active layer 120a of pure amorphous silicon in a stacked form in each of the switching regions TrA. The semiconductor layer 120, and the source electrode 133 and the drain electrode 136 spaced apart from each other form a thin film transistor Tr1 as a switching element.

Next, as shown in FIGS. 5H and 6H, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the pixel electrode 150 and the transparent conductive pattern 152. 101) The second protective layer 155 is formed on the entire surface.

In this case, although not shown in the drawing, the second protective layer 155 is patterned by a mask process to expose the ends of the gate lines 103a and 103b and the data lines 130 in the non-display area, respectively. A contact hole (not shown) is formed.

Next, as shown in FIGS. 5I and 6I, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the second protective layer 155. In addition, a plurality of products having a plate shape in front of the display area by patterning the mask process and having a bar shape having one or three bent portions (not shown) corresponding to the pixel areas P1 and P2 are processed. By forming the common electrode 160 having one opening op1, the array substrate 101 for a fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention is completed.

In this case, since the planar shape of the plurality of first openings op1 having a bar shape provided in the common electrode 160 has been described above, it will be omitted.

Meanwhile, as shown in the drawing, the common electrode 160 may be formed to further have a second opening op2 corresponding to each of the switching regions TrA in the forming of the plurality of first openings op1. A part of the common electrode 160 having such a configuration may extend to a non-display area and be provided on the common wiring 108 and the first and second protective layers 140 and 155 in the non-display area. It is electrically connected by contacting through a common contact hole (not shown).

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: array substrate
103a and 103b: odd and even gate wirings
108: common wiring
120a: active layer
130: Data wiring
133: source electrode
136: drain electrode
150: pixel electrode
160: common electrode
a1, a2, a3: 1st, 2nd, 3nd bending part BA: bending part
CA: Domain boundary
CPLA: Spacing area between odd and even gate wirings (paired)
D1, D2: first and second domain regions
P1, P2: (first and second) pixel areas
PL1, PL2: first and second pixel lines
op1, op2: first and second opening
Tr1, Tr2: Thin Film Transistor

Claims (13)

An odd-numbered line and an even-numbered line adjacent to each other on a substrate on which a display area for displaying an image is defined are formed in pairs having a first spacing interval and having a second spacing interval greater than the first spacing interval; ;
A common wiring formed in parallel with the gate wiring at a central portion of the second spacing;
A data line formed to define a pixel area intersecting the gate line and the common line;
A thin film transistor provided adjacent to each pixel area at the first spacing interval;
A pixel electrode formed in contact with the drain electrode of the thin film transistor for each pixel region;
A plurality of bars having a bar shape formed on an entire surface of the display area with an insulating layer on the pixel area and having a bent portion at the center of each pixel area for each pixel area to be symmetrically bent up and down; Common electrode with opening
Wherein the common electrode and one end of the common wiring are in contact with each other in a non-display area outside the display area.
The method of claim 1,
And the common wiring is 1/2 of the number of gate wirings.
The method of claim 1,
The plurality of first openings positioned in adjacent pixel regions positioned above and below the common wiring with reference to the common wiring may have the bent portions located in opposite directions. .
The method according to claim 1 or 3,
And the data line has a zigzag shape in the display area, and a portion corresponding to the first opening is formed in parallel with the first opening.
5. The method of claim 4,
One or three bent portions are formed in each pixel area, and when the bent portions are three, the angles of the second bent portions are defined as the first, second, and third bent portions sequentially. An array substrate for a fringe field switching mode liquid crystal display device having a larger than a negative angle, wherein the first opening is vertically symmetric with respect to the second bent portion.
The method of claim 1,
And a second opening removed from the common electrode in correspondence with each of the thin film transistors.
The method of claim 1,
A first protective layer having a flat surface between the thin film transistor and the data line and the pixel electrode and having a contact hole exposing the thin film transistor;
An island-shaped transparent conductive pattern and the pixel electrode are respectively formed on the source electrode and the drain electrode of the thin film transistor exposed through the contact hole, and the island-shaped transparent conductive pattern and the pixel electrode are formed in the contact hole. An array substrate for a fringe field switching mode liquid crystal display, characterized in that spaced apart from each other.
The gate lines are arranged such that adjacent odd-numbered lines and even-numbered lines are formed in pairs with a first spacing interval and have a second spacing interval greater than the first spacing interval on a substrate on which a display area for displaying an image is defined. Forming a common wiring parallel to the gate wiring at a central portion of the second spacing, and forming a gate electrode in a form branched from the gate wiring at the first spacing;
Forming a data line on the gate line, the common line, and the gate electrode to intersect the gate line and the common line to define a pixel region through a gate insulating layer;
Forming a first passivation layer on the front surface of the data line, the first passivation layer having a contact hole corresponding to the gate electrode;
Forming a pixel electrode for each pixel region on the first passivation layer, and successively forming a source electrode and a drain electrode spaced apart from each other in the contact hole;
A plurality of bars are formed on the front surface of the display area by interposing a second passivation layer on the pixel electrode, and having a bent portion at the center of each pixel area. Forming a common electrode having a first opening
Wherein the common electrode and one end of the common wiring are formed to be in contact with each other in the non-display area outside the display area.
The method of claim 8,
Forming an active layer and an impurity amorphous silicon pattern on each of the gate electrodes over the gate insulating layer prior to forming the data line;
The forming of the data line may include forming a metal pattern on the impurity amorphous silicon pattern in a form branched from the data line,
The forming of the pixel electrode may include forming a transparent conductive pattern spaced apart from the pixel electrode on the metal pattern.
A fringe field switching method may include forming an ohmic contact layer under the source electrode and the drain electrode and the two electrodes by removing the metal pattern exposed between the transparent conductive pattern and the pixel electrode and an impurity amorphous silicon pattern thereunder. A method of manufacturing an array substrate for a mode liquid crystal display device.
The method of claim 8,
For the fringe field switching mode liquid crystal display device, wherein the plurality of first openings positioned in adjacent pixel areas positioned above and below the common wiring are formed in opposite directions to each other. Method of manufacturing an array substrate.
11. The method according to claim 8 or 10,
The data line may be formed to have a zigzag shape in the display area, and a portion corresponding to the first opening may be formed to be parallel to the first opening. .
The method of claim 11,
One or three bent portions are formed in each pixel area, and when the bent portions are three, the angles of the second bent portions are defined as the first, second, and third bent portions sequentially. The first opening is larger than a negative angle, and the first opening is formed to be symmetrical with respect to the second bent portion characterized in that the manufacturing method of the array substrate for a fringe field switching mode liquid crystal display device.
The method of claim 8,
The forming of the common electrode having the first opening may include forming a second opening removed corresponding to each of the thin film transistors.

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