KR20130033695A - Method for fabricating semiconductor device using single-side-contact - Google Patents

Method for fabricating semiconductor device using single-side-contact Download PDF

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Publication number
KR20130033695A
KR20130033695A KR1020110097526A KR20110097526A KR20130033695A KR 20130033695 A KR20130033695 A KR 20130033695A KR 1020110097526 A KR1020110097526 A KR 1020110097526A KR 20110097526 A KR20110097526 A KR 20110097526A KR 20130033695 A KR20130033695 A KR 20130033695A
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KR
South Korea
Prior art keywords
film
forming
liner
layer
diffusion barrier
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KR1020110097526A
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Korean (ko)
Inventor
이보미
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에스케이하이닉스 주식회사
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Priority to KR1020110097526A priority Critical patent/KR20130033695A/en
Publication of KR20130033695A publication Critical patent/KR20130033695A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045—Field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention relates to a method of manufacturing a semiconductor device capable of minimizing the loss of a lower liner oxide film while removing silicon oxide on the side of a dopant diffusion barrier during a single-side contact process. Forming pillars separated by; Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar; Forming a metal silicide layer on the open portion; Forming a protective film partially filling the trench to expose the metal silicide film; Forming a liner layer exposing the metal silicide layer on the passivation layer; And cleaning the surface of the metal silicide film exposed by the liner film, and forming a protective film to prevent loss of the liner oxide film during the single-side contact process, thereby reducing silicon oxide without losing the liner oxide film during the dopant barrier film surface cleaning process. Can be easily removed.

Description

Method of manufacturing semiconductor device using single side contact {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING SINGLE―SIDE―CONTACT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a single side contact.

As the design rule of the semiconductor device decreases, the cell size decreases, thereby increasing the process difficulty in the 8F 2 or 6F 2 (F is a minimun feature) cell structure. In addition, the short channel margin characteristic is degraded due to the reduction of the gate length.

In order to solve this problem, a method of three-dimensionally processing a semiconductor substrate and thereby three-dimensionally forming a transistor has been proposed. For example, a vertical transistor having a pillar extending in a direction perpendicular to the surface of a semiconductor substrate is used as a channel. Vertical transistors can reduce the footprint and contribute to a reduction in cell size. In addition, the vertical transistor can realize a 4F 2 cell structure by forming the gate and the channel in the vertical direction.

When a vertical transistor using a pillar is used as a cell transistor of a memory device, one side (eg, a source) of a junction that becomes a source or a drain is a bitline. ), And the other side of the junction (eg, drain) is connected to a capacitor. In general, since the capacitor is disposed above the cell transistor, the capacitor is connected to the upper part of the pillar and the bit line is connected to the lower part of the pillar.

A portion of the sidewall of either pillar must be exposed to connect the bitline and one side junction. This is called a SSC (Single-Side-Contact) process or an OSC (One-Side-Contact) OSC process. Hereinafter, it is abbreviated as "singleside contact process." The source formed inside the pillar is exposed by the single side contact process, and the buried bit line is electrically connected to the exposed source.

In the vertical transistor using a pillar as described above, metal silicide is used as a dopant diffusion barrier to form a junction connected to a bit line.

1A and 1B illustrate a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a plurality of pillars 12 separated by a plurality of trenches are formed on the substrate 11. The hard mask film 13 is formed on the pillar 12. An insulating film is coated on both sidewalls of the pillars 12, the trench surface between the pillars 12, and the sidewalls of the hard mask film 13. The insulating film includes a liner oxide film 14 and a liner nitride film 15.

An open portion 16 is formed to expose a portion of the sidewall of the pillar 12 to a portion of the liner oxide layer 14. Such an open portion 16 is called a single side contact.

A metal silicide film is formed in the open portion 16 as the dopant diffusion barrier 17.

As shown in FIG. 1B, a cleaning process is performed to remove the silicon oxide 18 remaining on the surface of the dopant diffusion barrier 17.

According to the above-described prior art, the metal silicide film used as the dopant diffusion barrier 17 is formed through the process of metal film deposition, annealing and unreacted metal film strips. Silicon oxide (SiO x , 18) is formed on the surface of the metal silicide by H 2 O 2 used in the unreacted metal film strip.

When the silicon oxide 18 is present on the open portion 16, that is, on the side of the single side contact, it may cause deterioration of electrical characteristics such as contact resistance. Therefore, the silicon oxide 18 needs to be removed. To this end, the silicon oxide 18 is removed using a hydrofluoric acid solution and ammonium hydroxide.

However, as the silicon oxide 18 is removed, a large amount of the liner oxide film 14 is lost (see reference numeral '19'), thereby preventing insulation between buried bit lines.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of minimizing loss of a lower liner oxide layer while removing silicon oxide on the side of a dopant diffusion barrier during a single-side contact process.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a pillar separated by a trench by etching the substrate; Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar; Forming a dopant diffusion barrier layer on the open portion; Forming a protective film partially filling the trench to expose the dopant diffusion barrier film; Forming a liner layer exposing the dopant diffusion barrier layer on the passivation layer; And cleaning the surface of the dopant diffusion barrier film exposed by the liner film.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form a pillar separated by a trench; Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar; Forming a dopant diffusion barrier layer on the open portion; Forming a protective film partially filling the trench to expose the dopant diffusion barrier film; Forming a liner film on the entire surface including the protective film; And implanting impurities into the liner layer in any one sidewall direction of the pillar; Removing the ion implantation region of the liner layer remaining on the other sidewall of the pillar; And cleaning the surface of the dopant diffusion barrier film exposed by the non-ion implantation region of the liner film.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of etching the substrate to form a pillar separated by a trench; Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar; Forming a metal silicide layer on the open portion; Forming a protective film partially filling the trench to expose the metal silicide film; Forming a liner layer exposing the metal silicide layer on the passivation layer; And cleaning the surface of the metal silicide film exposed by the liner film.

In the present invention described above, since the protective film is formed to prevent loss of the liner oxide film during the single-side contact process, the silicon oxide may be easily removed without losing the liner oxide film during the metal silicide film surface cleaning process. As a result, the contact resistance and insulation characteristics between the buried bit lines are improved, which can be expected to increase the reliability of the device.

1A and 1B illustrate a method of manufacturing a semiconductor device according to the prior art.
2A to 2I illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2I illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a plurality of bodies 204 separated by a plurality of trenches 203 are formed on the substrate 201. The substrate 201 includes a silicon substrate. The substrate 201 is etched to a predetermined depth to form a plurality of trenches 203. The body 204 is formed by the trench 203. Since the substrate 201 includes a silicon substrate, the body 204 becomes a silicon body. Body 204 extends vertically from the surface of substrate 201. The body 204 is used as an active region. As is well known, the active region is the region where the channel, source and drain of the transistor are formed. Body 204 has a sidewall. It is a line type body having at least two transverse sidewalls. The body 204 is also referred to as an 'active body'.

The hard mask film 202 is formed on the body 204. The hard mask layer 202 serves as an etch barrier when etching the substrate 201 for forming the trench 203. The hard mask layer 202 may include an insulating material such as an oxide, a nitride, or the like. In an embodiment, a nitride film is used as the hard mask film 202. The hard mask layer 202 includes a silicon nitride layer.

An insulating film is formed on both sidewalls of the body 204, the surface of the trench 203 between the body 204, and the sidewalls of the hard mask film 202. The insulating layer includes a liner oxide 205 and a liner nitride 206. The liner oxide film 205 is formed on both sidewalls of the body 204 and the surface of the substrate 201. The liner nitride film 206 is formed on a portion of the surface of the liner oxide film 205. The liner oxide film 205 is formed using a silicon oxide film such as LPCVD Tetra-ethyl-ortho-silicate (LPTEOS). The liner nitride film 206 is formed using a silicon nitride film.

A portion of the insulating film is removed to form an open portion 207. The open portion 207 is a single-side contact (SSC) or one-side-contact (OSC) structure that selectively exposes a portion of one sidewall of the body 204. The open portion 207 has a line shape along the extending direction of the body 204 and opens a portion of the sidewall of the body 204.

An open portion 207 is provided that exposes a portion of the sidewall of the body 204 by the insulating film described above. The open portion 207 is a single side contact.

As shown in FIG. 2B, a metal silicide film is formed as the dopant diffusion barrier film 208 in the open portion 207. For example, the metal silicide film includes a cobalt silicide film. Cobalt film deposition, primary anneal, unreacted cobalt film strip and secondary anneal may be performed to form the cobalt silicide film. The unreacted cobalt film strip is wet cleaned using a solution containing H 2 O 2 . As described above, the silicon oxide 209 is formed on the surface of the dopant diffusion barrier film 208 during the unreacted cobalt film strip during the series of processes for forming the metal silicide film.

As shown in FIG. 2C, the protective film 210 is coated and then heat treated. Here, the protective film 210 is a material for preventing the loss of the liner oxide film 205 in a subsequent process. The passivation layer 210 includes an insulating layer, and preferably includes a spin-on insulating layer SOD.

As shown in FIG. 2D, the protective film 210 is planarized using chemical mechanical polishing or the like. The polishing is stopped in the hard mask film 202 and subsequently recessed. As a result, the protective film 210A has a height that exposes the dopant diffusion barrier film 208. That is, the dopant diffusion barrier film 208 and the silicon oxide 209 of the open portion 207 are exposed again by the protective film 210A.

As shown in FIG. 2E, a liner film 211 is formed. The liner film 211 includes polysilicon. Hereinafter, the liner film 211 is referred to as a 'liner polysilicon film 211'. The liner polysilicon film 211 may be formed of undoped polysilicon free of impurities.

As shown in FIG. 2F, tilt ion implantation 212 is performed. The tilt ion implantation 212 is ion implanted by giving a tilt at a predetermined angle. Accordingly, some of the liner polysilicon film 211 is doped with dopants.

The tilt ion implantation 212 process is performed at a predetermined angle. The predetermined angle includes about 5-30 degrees. The ion beam is partially shadowed by the hard mask film 202. Thus, part of the liner polysilicon film 211 is doped but the remainder remains undoped. For example, the dopant to be ion implanted is a P-type dopant, preferably Boron, and the dopant source uses BF 2 to ion implant boron. As a result, a part of the liner polysilicon film 211 remains undoped, which is a portion adjacent to the right side of the hard mask film 202.

The portion of the liner polysilicon film formed on the upper surface of the hard mask film 202 and the portion adjacent to the left side of the hard mask film 202 by the tilt ion implantation 212 of the dopant are doped with ion implantation regions. It becomes (211A). The liner polysilicon film to which the dopant is not implanted becomes the nonion implantation region 211B. The liner polysilicon 211 is divided into an ion implantation region 211A and a nonion implantation region 211B, thereby giving a difference in wet etching rate.

As shown in FIG. 2G, any one of the ion implantation region 211A and the nonion implantation region 211B is selectively removed. In the present embodiment, the ion implantation region 211A is selectively removed. Herein, the polysilicon used as the liner polysilicon film has a difference in etching speed depending on whether dopants are doped or not. The ion implantation region 211A is removed by wet etching or wet cleaning. Wet etching or wet cleaning may use a solution such as potassium hydroxide (KOH).

When the ion implantation region 211A is removed as described above, only the non-ion implantation region 211B remains, thereby exposing the silicon oxide 209 on the surface of the dopant diffusion barrier layer 208.

As shown in FIG. 2H, the surface of the dopant diffusion barrier film 208 is cleaned. Accordingly, the silicon oxide 209 exposed by the nonion implantation region 211B is selectively removed. Silicon oxide 209 is removed using a mixed solution of BOE and NH 4 OH.

In this case, since the non-ion implantation region 211B and the protection film 210A protect the liner oxide film 205 at the bottom of the trench, the liner oxide film 205 may be prevented from being damaged when the silicon oxide 209 is removed. In addition, the non-ion implantation region 211B prevents the liner oxide layer from being etched from the other sidewall of the pillar 204.

As shown in FIG. 2I, the nonion implantation region 211B is removed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.

201: semiconductor substrate 202: hard mask film
203: trench 204: pillar
205: liner oxide film 206: liner nitride film
207: open portion 208: dopant diffusion barrier film
209: silicon oxide 210A: protective film
211: liner polysilicon film

Claims (5)

Etching the substrate to form pillars separated by trenches;
Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar;
Forming a dopant diffusion barrier layer on the open portion;
Forming a protective film partially filling the trench to expose the dopant diffusion barrier film;
Forming a liner layer exposing the dopant diffusion barrier layer on the passivation layer; And
Cleaning the surface of the dopant diffusion barrier film exposed by the liner film
≪ / RTI >
Etching the substrate to form pillars separated by trenches;
Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar;
Forming a dopant diffusion barrier layer on the open portion;
Forming a protective film partially filling the trench to expose the dopant diffusion barrier film;
Forming a liner film on the entire surface including the protective film; And
Ion implanting impurities into the liner film in any one sidewall direction of the pillar;
Removing the ion implantation region of the liner layer remaining on the other sidewall of the pillar; And
Cleaning the surface of the dopant diffusion barrier film exposed by the non-ion implantation region of the liner film
≪ / RTI >
Etching the substrate to form pillars separated by trenches;
Forming an insulating film having an open portion exposing a portion of one sidewall of the pillar;
Forming a metal silicide layer on the open portion;
Forming a protective film partially filling the trench to expose the metal silicide film;
Forming a liner layer exposing the metal silicide layer on the passivation layer; And
Cleaning the surface of the metal silicide film exposed by the liner film
≪ / RTI > 4. The method according to any one of claims 1 to 3,
Forming the protective film,
Forming a spin-on insulating film over the trench to gap gap the trench;
Annealing the spin-on insulating film;
Planarizing the spin-on insulating film; And
Recessing the spin-on insulating film
≪ / RTI >
4. The method according to any one of claims 1 to 3,
And the liner layer is made of polysilicon.
KR1020110097526A 2011-09-27 2011-09-27 Method for fabricating semiconductor device using single-side-contact KR20130033695A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269746B2 (en) 2013-11-12 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9269746B2 (en) 2013-11-12 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US9431458B2 (en) 2013-11-12 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same

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