KR20130022337A - Method for fabricating semiconductor device using single-side-contact - Google Patents
Method for fabricating semiconductor device using single-side-contact Download PDFInfo
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- KR20130022337A KR20130022337A KR1020110085877A KR20110085877A KR20130022337A KR 20130022337 A KR20130022337 A KR 20130022337A KR 1020110085877 A KR1020110085877 A KR 1020110085877A KR 20110085877 A KR20110085877 A KR 20110085877A KR 20130022337 A KR20130022337 A KR 20130022337A
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- Prior art keywords
- side wall
- trench
- region
- film
- liner
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- 238000000034 method Methods 0.000 title abstract description 49
- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 30
- 238000005468 ion implantation Methods 0.000 claims abstract description 25
- 241000047703 Nonion Species 0.000 claims abstract description 11
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 239000003112 inhibitor Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 24
- 229920005591 polysilicon Polymers 0.000 abstract description 24
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 230000009977 dual effect Effects 0.000 abstract description 5
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 14
- 150000004767 nitrides Chemical class 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 10
- 238000005530 etching Methods 0.000 description 10
- 229910017464 nitrogen compound Inorganic materials 0.000 description 10
- 150000002830 nitrogen compounds Chemical class 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- -1 nitrogen ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
- H01L21/423—Bombardment with radiation with high-energy radiation
- H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L2029/7857—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET of the accumulation type
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a single side contact.
As the design rule of the semiconductor device decreases, the cell size decreases, thereby increasing the process difficulty in the 8F 2 or 6F 2 (F is a minimun feature) cell structure. In addition, the short channel margin characteristic is degraded due to the reduction of the gate length.
In order to solve this problem, a method of three-dimensionally processing a semiconductor substrate and thereby three-dimensionally forming a transistor has been proposed. For example, a vertical transistor having a pillar extending in a direction perpendicular to the surface of a semiconductor substrate is used as a channel. Vertical transistors can reduce the footprint and contribute to a reduction in cell size. In addition, the vertical transistor can realize a 4F 2 cell structure by forming the gate and the channel in the vertical direction.
When a vertical transistor using a pillar is used as a cell transistor of a memory device, one side (eg, a source) of a junction that becomes a source or a drain is a bitline. ), And the other side of the junction (eg, drain) is connected to a capacitor. In general, since the capacitor is disposed above the cell transistor, the capacitor is connected to the upper part of the pillar and the bit line is connected to the lower part of the pillar.
A portion of the sidewall of either pillar must be exposed to connect the bitline and one side junction. This is called a SSC (Single-Side-Contact) process or an OSC (One-Side-Contact) OSC process. Hereinafter, it is abbreviated as "singleside contact process." The source formed inside the pillar is exposed by the single side contact process, and the buried bit line is electrically connected to the exposed source.
A memory device using a vertical transistor is disclosed in Patent Document 1 below.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the dual opening phenomenon in the single-side contact process.
A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a liner film adjacent the upper region of the trench on the sacrificial film; Ion implanting oxide inhibitor ions into the liner film in the first side wall direction; Oxidizing a non-ion implantation region of the liner layer remaining on the second side wall; And selectively removing the oxidized non-ion implantation region.
In addition, the semiconductor device manufacturing method of the present invention includes the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a silicon film on the sacrificial layer adjacent to the upper region of the trench; Implanting ionization inhibitor ions into the silicon film in the direction of the first side walls; Oxidizing a non-ion implantation region of the silicon film remaining on the second side wall; And selectively removing the oxidized non-ion implantation region.
In addition, the semiconductor device manufacturing method of the present invention includes the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a silicon film on the sacrificial layer, the silicon film having an oxide region adjacent to an upper portion of the first side wall and a non-oxidation region adjacent to an upper portion of the second side wall; And selectively removing the oxidation region.
In addition, the semiconductor device manufacturing method of the present invention includes the steps of providing a substrate having a trench having a first side wall and a second side wall is coated with an insulating film; Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench; Forming a liner film on the sacrificial layer, the liner layer having an oxide region adjacent to an upper portion of the first side wall and a non-oxidation region adjacent to an upper portion of the second side wall; Selectively removing the oxidation region; And selectively removing the sacrificial film and the insulating film adjacent to the first side wall to form an open portion exposing a portion of the first side wall.
In addition, the semiconductor device manufacturing method of the present invention comprises the steps of: providing a substrate having a plurality of active bodies having a first side wall and a second side wall coated with an insulating film; Forming a sacrificial layer gap-filling the active bodies while exposing an upper region of the active bodies; Forming a silicon film on the sacrificial layer, the silicon film having an oxide region adjacent to an upper portion of the first side wall and a non-oxidation region adjacent to an upper portion of the second side wall; Selectively removing the oxidation region; Selectively removing the sacrificial layer and the insulating layer adjacent to the first side wall to form an open portion exposing a portion of the first side wall; And forming a bit line connected to the first side wall through the open part and partially filling the active body.
The present invention described above has a selectivity ratio between the ion implantation region and the nonion implantation region through nitrogen tilt ion implantation, and the loss of the polysilicon liner by selectively removing the nonionic implantation region through the subsequent annealing and oxidation process. Dual open phenomenon can be prevented. As a result, shorts between neighboring bit lines can be suppressed.
1A and 1B illustrate a semiconductor device according to an embodiment of the present invention.
2A to 2L are cross-sectional views illustrating a method of forming an open part by a single side contact process according to an exemplary embodiment of the present invention.
3A to 3C are diagrams illustrating a method of manufacturing a semiconductor device using an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .
1A and 1B illustrate a semiconductor device according to an embodiment of the present invention.
Referring to FIG. 1A, a plurality of
The
As shown in FIG. 1B, a
The semiconductor device of FIGS. 1A and 1B forms an
2A to 2L are cross-sectional views illustrating a method of forming an open part by a single side contact process according to an exemplary embodiment of the present invention.
As shown in FIG. 2A, a
Next, a trench etch process is performed using the
The
A first
As shown in FIG. 2B, the first
Subsequently, the first
As shown in FIG. 2C, the
As shown in FIG. 2D, the
Subsequently, the first
As shown in FIG. 2E, a metal nitride film is conformally formed on the entire surface including the second recess R2. Thereafter, the spacer etching is performed to form the
Subsequently, the second recess R2 on which the
As shown in FIG. 2F, the
As shown in FIG. 2G, the
The
Preferably, the
Preferably, the
As shown in FIG. 2H, an
As shown in FIG. 2I, an
As described above, when the
As shown in Fig. 2J, the
When the oxidized
As shown in Fig. 2K, any one of the
Next, a cleaning process is performed to expose a portion of the lower sidewall of the
The cleaning process includes wet cleaning. Wet cleaning uses hydrofluoric acid (HF) and BOE (Buffered Oxide Etchant). By using wet cleaning, the first
The
As shown in FIG. 2L, the doped
Next, the
The
3A to 3C are diagrams illustrating a method of manufacturing a semiconductor device using an embodiment of the present invention.
As shown in FIG. 3A, a
As shown in FIG. 3B, the
As shown in FIG. 3C, the planarization and etch back processes are sequentially performed on the
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined by the appended claims. Will be clear to those who have knowledge of.
21: semiconductor substrate 22: hard mask film
23: trench 24: body
25: first liner film pattern 27: second liner film pattern
30:
30B:
30D:
34: open section
Claims (5)
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a liner film adjacent the upper region of the trench on the sacrificial film;
Ion implanting oxide inhibitor ions into the liner film in the first side wall direction;
Oxidizing a non-ion implantation region of the liner layer remaining on the second side wall; And
Selectively removing the oxidized non-ion implantation region
≪ / RTI >
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a silicon film on the sacrificial layer adjacent to the upper region of the trench;
Implanting ionization inhibitor ions into the silicon film in the direction of the first side walls;
Oxidizing a non-ion implantation region of the silicon film remaining on the second side wall; And
Selectively removing the oxidized non-ion implantation region
≪ / RTI >
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a silicon film on the sacrificial layer, the silicon film having an oxide region adjacent to an upper portion of the first side wall and a non-oxidation region adjacent to an upper portion of the second side wall; And
Selectively removing the oxidation region
≪ / RTI >
Forming a sacrificial layer gap-filling the trench while exposing an upper region of the trench;
Forming a liner film on the sacrificial layer, the liner layer having an oxide region adjacent to an upper portion of the first side wall and a non-oxidation region adjacent to an upper portion of the second side wall;
Selectively removing the oxidation region; And
Selectively removing the sacrificial layer and the insulating layer adjacent to the first side wall to form an open portion exposing a portion of the first side wall;
≪ / RTI >
Forming a sacrificial layer gap-filling the active bodies while exposing an upper region of the active bodies;
Forming a silicon film on the sacrificial layer, the silicon film having an oxide region adjacent to an upper portion of the first side wall and a non-oxidation region adjacent to an upper portion of the second side wall;
Selectively removing the oxidation region;
Selectively removing the sacrificial layer and the insulating layer adjacent to the first side wall to form an open portion exposing a portion of the first side wall; And
Forming a bit line connected to the first side wall through the open part and partially filling the active body
≪ / RTI >
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KR1020110085877A KR20130022337A (en) | 2011-08-26 | 2011-08-26 | Method for fabricating semiconductor device using single-side-contact |
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KR1020110085877A KR20130022337A (en) | 2011-08-26 | 2011-08-26 | Method for fabricating semiconductor device using single-side-contact |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9269746B2 (en) | 2013-11-12 | 2016-02-23 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
-
2011
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9269746B2 (en) | 2013-11-12 | 2016-02-23 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
US9431458B2 (en) | 2013-11-12 | 2016-08-30 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
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