KR20130024070A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20130024070A
KR20130024070A KR1020110087296A KR20110087296A KR20130024070A KR 20130024070 A KR20130024070 A KR 20130024070A KR 1020110087296 A KR1020110087296 A KR 1020110087296A KR 20110087296 A KR20110087296 A KR 20110087296A KR 20130024070 A KR20130024070 A KR 20130024070A
Authority
KR
South Korea
Prior art keywords
dielectric constant
high dielectric
constant material
semiconductor device
film
Prior art date
Application number
KR1020110087296A
Other languages
Korean (ko)
Inventor
한지혜
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110087296A priority Critical patent/KR20130024070A/en
Publication of KR20130024070A publication Critical patent/KR20130024070A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02697—Forming conducting materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to easily remove etching residue to by using a SPM(sulfuric acid and hydrogen peroxide mixture) and DHF(diluted hydrogen fluoride). CONSTITUTION: A high-k dielectric material film(210) is formed on a substrate(100). The high-k dielectric material film includes hafnium oxide and lanthanum oxide. The high-k dielectric material film is etched. The etching residue due to etching is cleaned with a mixture of SPM and HF.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a high-k material film.

As the degree of integration of semiconductor devices increases, the thickness of the silicon oxide film (SiO 2 ) forming the gate dielectric film becomes gradually thinner. Since the silicon oxide film has a small dielectric constant, the thinner the thickness, the more difficult it is to obtain sufficient charge, and the gate leakage current increases. A high-k material film is used instead of the silicon oxide film to prevent current leakage and improve performance of the gate dielectric film.

According to the prior art, the gate dielectric film and the conductive film for the gate electrode are sequentially formed on the substrate, and then the gate dielectric film and the conductive film for the gate electrode are selectively etched to form a gate structure. In this case, the gate dielectric layer includes a high dielectric constant material layer.

1 to 3 are photographs for explaining a problem of a method of manufacturing a gate structure including a high dielectric constant material film according to the prior art.

1 is a plan view and a cross-sectional view of a substrate 10 on which a gate structure 20 is formed.

Referring to FIG. 1, contaminants (see A in cross section) are formed on the exposed substrate 10 as a result of the etching process for forming the gate structure 20. The contaminant (A) is an etching residue generated by the reaction between the etching gas and the high dielectric constant material film used in the etching process. In addition, since the high dielectric constant material layer forming the gate dielectric layer 21 is less etched and remains in a protruding form (see B in the cross-sectional view), the gate structure 20 having a vertical profile cannot be formed, and a plurality of gate structures ( 20) The spacing between them is uneven.

Referring to FIG. 2, when the high dielectric constant material layer B protruding from FIG. 1 is vertically etched and the exposure time to the etching gas is increased in order to remove the etching residue, the etching target is excessively etched. To damage the silicon forming the substrate 10 (see C).

Referring to FIG. 3, it can be seen that more contaminants are formed on the substrate 10 due to the reaction between the cleaning material used in the cleaning process for removing the etching residue and the high dielectric constant material film forming the gate dielectric layer 21.

In addition, in the case of using the batch equipment, it is difficult to shorten the cleaning time, and thus, the cleaning material removes even the high dielectric constant material film forming the gate dielectric film 21, so that the gate structure 20 is separated from the substrate 10 in severe cases. there is a problem.

In summary, when the gate dielectric layer 21 is less etched through a general etching process, it is difficult to secure a CD (critical dimension) margin between the gate structures 20. In case of excessive etching, the substrate is damaged. In addition, contaminants generated during the etching and cleaning processes of the gate structure including the high dielectric constant material film have a problem of affecting semiconductor characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device that can easily remove contaminants generated during an etching process for forming a gate structure including a high dielectric constant material film.

According to one or more exemplary embodiments, a method of manufacturing a semiconductor device includes: forming a high dielectric constant material film on a substrate; Etching the high dielectric constant material film; And washing the etching residue generated in the etching process with a mixture of sulfuric acid hydrogen peroxide mixed solution (SPM) and diluted hydrogen fluoride solution (HF).

According to the method of manufacturing a semiconductor device of the present invention, contaminants generated during an etching process for forming a gate structure including a high dielectric constant material film can be easily removed.

1 to 3 are photographs for explaining a problem of a method of manufacturing a gate structure including a high dielectric constant material film according to the prior art.
4 to 6 are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and specifically, a method for forming a gate structure.
7 is a photograph showing a semiconductor device manufactured according to an embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and spacing are expressed for convenience of description and may be exaggerated compared to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

4 to 6 are diagrams for describing a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and specifically, a method for forming a gate structure.

Referring to FIG. 4, a substrate 100 including an active region 120 and an isolation layer 110 defining an active region 120 is provided.

Subsequently, a gate dielectric film 211 is formed on the substrate 100. For example, after forming the hafnium oxide film HfO 2 , the gate dielectric film 211 may be formed of the hafnium silicon oxynitride film HfSiON formed by heat treatment of the hafnium oxide film in a nitrogen (N) atmosphere.

Subsequently, a capping layer 212, for example, a lanthanum oxide layer La 2 O 3 , is formed on the gate dielectric layer 211. By forming the capping layer 212, the high threshold voltage V TH of the gate dielectric layer 211 formed of the high dielectric constant material may be effectively reduced. In the present exemplary embodiment, the capping layer 212 is formed on the gate dielectric layer 211. However, in another embodiment, the capping layer 212 may be formed under the gate dielectric layer 211.

Hafnium (Hf) and lanthanum (La) are high dielectric constant materials, hereinafter referred to as gate dielectric layer 211 and capping layer 212, and are referred to as high dielectric constant material layer 210.

Referring to FIG. 5, the first conductive layer 220, the second conductive layer 230, and the gate hard mask layer 240 are sequentially formed on the high dielectric constant material layer 210. The first conductive film 220 and the second conductive film 230 form a gate electrode, the first conductive film 220 may include, for example, a polysilicon film, and the second conductive film 230 may, for example, It may include tungsten (W). The gate hard mask layer 240 may include, for example, an oxide layer or a nitride layer.

Referring to FIG. 6, after forming a photoresist pattern (not shown) for forming the gate structure 200 on the gate hard mask layer 240, the gate hard mask layer 240 using the photoresist pattern as an etching mask. ), The second conductive layer 230, the first conductive layer 220, and the high dielectric constant material layer 210 are etched to form the gate structure 200.

In the process of etching the high dielectric constant material film 210, contaminants including hafnium and contaminants including lanthanum are generated. Contaminants including lanthanum include, for example, lanthanum fluoride (LaF) generated by reacting a lanthanum oxide film included in the high dielectric constant material film 210 with a CF 4 gas used in an etching process.

Subsequently, a cleaning process is performed to remove contaminants generated during the etching process. As a result of the etching process, a mixture of hafnium-containing contaminants and lanthanum-containing contaminants remains, so that a cleaning process using a mixed solution of a plurality of cleaning solutions, for example, a SPM solution and a DHF solution is performed.

SPM as a mixture of (Sulfuric acid and Hydro-Peroxide Mixture ) solution of sulfuric acid (H 2 SO 4) and hydrogen peroxide (H 2 O 2), the proportion of sulfuric acid (H 2 SO 4) and hydrogen peroxide (H 2 O 2) Contaminants including lanthanum can be removed using SPM solutions at concentrations of 4: 1 to 100: 1 and at 25 ° C to 120 ° C.

Diluted HF (DHF) solution is a solution of dilute hydrogen fluoride (HF) in ultrapure water (Diluted HF). Can be removed.

However, the SPM solution can remove not only contaminant lanthanum fluoride, but also lanthanum oxide film included in the high dielectric constant material film. Therefore, the cleaning process is performed in a short time in the sheet type equipment so that the cleaning process can be completed before the lanthanum oxide film is removed. If the cleaning process is performed in the batch type equipment, the semiconductor device may be exposed to the SPM solution for a long time, and thus, the lanthanum oxide film forming the high dielectric constant material film 210 may be gradually removed by the SPM solution, thereby forming the gate structure 200. This is because the phenomenon of falling away from this substrate occurs.

If the mixed solution of the SPM solution and the DHF solution is not used as in the embodiment of the present invention, the first cleaning process using the SPM solution is performed, and the second cleaning process using the DHF solution is performed. In the case of performing the cleaning process, since the contaminants may be left without being removed as a result of each cleaning process, or more contaminants may be generated, one washing process is performed using the mixed solution as in the present embodiment.

Specifically, the DHF solution not only removes contaminants containing hafnium, but also fluorine contained in the DHF solution reacts with the lanthanum oxide film included in the high-k material film 210 to generate lanthanum fluoride. Therefore, if the secondary cleaning process using the DHF solution is performed after the primary cleaning process using the SPM solution, lanthanum fluoride, that is, contaminants, is newly generated during the secondary cleaning process and it is not removed. Therefore, when the cleaning process is performed with the mixture of the SPM solution and the DHF solution as in the present invention, it is possible to remove even the lanthanum fluoride generated by the reaction of the DHF solution with the lanthanum oxide film. I never do that

The cleaning process using the mixed cleaning solution is not limited to cleaning the gate structure. It should be noted that the present invention can be applied to both the cleaning process after the etching process of the pattern including the high dielectric constant material.

7 is a photograph showing a semiconductor device manufactured according to an embodiment of the present invention.

Referring to FIG. 7, as a result of performing a single cleaning process using a mixed solution of SPM solution and DHF solution, contaminants found in the etching and cleaning processes according to the prior art are removed, and the etching residue on the substrate 100 is removed. does not exist. Since the substrate 100 or the like does not need to be exposed to the etching gas for a long time due to excessive etching, the substrate 100 is not damaged. In addition, since the less etched portion of the dielectric layer 210 is removed, a vertical profile of the gate structure 200 can be secured, and the CD spacing between the gate structures 200 becomes uniform.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

100: substrate 110: element isolation film
120: active region 210: high dielectric constant material film
211: gate dielectric layer 212: capping layer
220: first conductive film 230: second conductive film
240: gate hard mask film 200: gate structure

Claims (5)

Forming a high dielectric constant material film on the substrate;
Etching the high dielectric constant material film; And
And washing the etching residue generated in the etching process with a solution containing a mixture of sulfuric acid hydrogen peroxide (SPM) and diluted hydrogen fluoride solution (HF).
The manufacturing method of a semiconductor device.
The method according to claim 1,
After forming the high dielectric constant material film,
Forming a gate electrode conductive layer and a gate hard mask layer on the high dielectric constant material layer; And
Selectively etching the conductive film for the gate electrode and the gate hard mask film;
A gate structure in which a high dielectric constant material film, a gate electrode, and a gate hard mask film are stacked.
The manufacturing method of a semiconductor device.
3. The method according to claim 1 or 2,
The high dielectric constant material film,
Containing hafnium oxide and lanthanum oxide
The manufacturing method of a semiconductor device.
3. The method according to claim 1 or 2,
The etching step,
Including a dry etching process using a gas containing fluorine (F)
The manufacturing method of a semiconductor device.
3. The method according to claim 1 or 2,
The cleaning step,
Dilute fluorine with a concentration of 0.015% to 4.9% of the sulfuric acid peroxide mixture (SPM) and hydrogen fluoride (HF) in which sulfuric acid and hydrogen peroxide are mixed at a ratio of 4: 1 to 100: 1 at a temperature of 25 degrees Celsius to 120 degrees Celsius. Washing with hydrogen hydrogen solution (DHF)
The manufacturing method of a semiconductor device.
KR1020110087296A 2011-08-30 2011-08-30 Method for manufacturing semiconductor device KR20130024070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110087296A KR20130024070A (en) 2011-08-30 2011-08-30 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110087296A KR20130024070A (en) 2011-08-30 2011-08-30 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20130024070A true KR20130024070A (en) 2013-03-08

Family

ID=48176204

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110087296A KR20130024070A (en) 2011-08-30 2011-08-30 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20130024070A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109494184A (en) * 2017-09-11 2019-03-19 爱思开海力士有限公司 The method of manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109494184A (en) * 2017-09-11 2019-03-19 爱思开海力士有限公司 The method of manufacturing semiconductor devices

Similar Documents

Publication Publication Date Title
TWI608543B (en) Semiconductor device and manufacturing method thereof
US9070635B2 (en) Removing method
US9048087B2 (en) Methods for wet clean of oxide layers over epitaxial layers
US11101178B2 (en) Semiconductor integrated circuit
US8329547B2 (en) Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide
JP4229762B2 (en) Manufacturing method of semiconductor device
JP2006066726A (en) Manufacturing method of semiconductor device and semiconductor substrate
KR100732591B1 (en) Method for manufacturing semiconductor device
JP2010021200A (en) Method for manufacturing semiconductor device
KR20070056749A (en) Manufacturing method for recess channel transistor with improved refresh characteristics
KR20130024070A (en) Method for manufacturing semiconductor device
CN113078209B (en) Semiconductor structure, manufacturing method thereof and peripheral circuit
JP2005057276A (en) Method for selectively removing high-k material
CN105990234B (en) The forming method of semiconductor devices
JP4902888B2 (en) Semiconductor device and manufacturing method thereof
TWI697031B (en) Patterning method
CN112652518A (en) Method for forming semiconductor device
TW201926431A (en) Method for making a semiconductor device
US11373912B2 (en) Semiconductor structure and method for forming the same
KR101016351B1 (en) Method for forming recess gate of semiconductor device
JP2008135765A (en) Semiconductor device
US20120115321A1 (en) Method for removing polymer after etching gate stack structure of high-k gate dielectric/metal gate
KR101008985B1 (en) Method for forming recess gate
KR20090027105A (en) Method for forming dual gate dielectrics
JP2010056189A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination