JP2010056189A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device that can round off corners of an active region top edge without generating irregularity on the surface of the active region. <P>SOLUTION: The method for manufacturing a semiconductor device has processes of forming an element isolation insulating film for demarcating an active region, forming a natural oxide film with a film thickness of ≥0.1 nm and <0.7 nm, annealing at a temperature of >850°C and <950°C in an atmosphere including hydrogen, rounding off the corners of the active region, and reducing and removing the natural oxide film, and forming a gate insulating film on the active region from where the natural oxide film is removed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a process of rounding a corner of an upper end portion of an active region.

  Along with the miniaturization of MIS transistors due to high integration of semiconductor devices, the influence of variation in the shape of the upper end of the active region on transistor characteristics has become a problem.

As a means for suppressing variation in the shape of the upper end of the active region, there has been proposed a method of performing a process of rounding the corner at the upper end of the active region. As one of the methods, there is known a method of rounding the corners of the active region end by performing high temperature oxidation or radical oxidation after forming the element isolation trench. As a method of rounding corners without using an oxidation step, a method is known in which hydrogen atoms are annealed to migrate silicon atoms before forming a gate insulating film.
JP 09-115869 A JP 2002-289611 A JP 2004-087960 A Japanese Patent Laying-Open No. 2005-079215

  However, when the rounding process by oxidation is performed, the width of the active region is narrowed, so that it is difficult to miniaturize the transistor. In addition, the inventors of the present invention diligently studied the method using migration by hydrogen annealing. As a result, it was found that the surface of the active region was uneven depending on the conditions, and variation in the active region end shape could not be sufficiently suppressed. did.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of rounding the corner of the upper end of the active region without causing irregularities on the surface of the active region.

  According to one aspect of the embodiment, a step of forming an element isolation insulating film for defining an active region on a semiconductor substrate, and a natural oxide film having a thickness of 0.1 nm or more and less than 0.7 nm on the active region And a step of performing heat treatment at a temperature higher than 850 ° C. and lower than 950 ° C. in an atmosphere containing hydrogen, rounding corners of the active region, and reducing and removing the natural oxide film, There is provided a method of manufacturing a semiconductor device including a step of forming a gate insulating film on the active region from which a natural oxide film has been removed.

  According to another aspect of the embodiment, a step of forming an element isolation insulating film for defining a first active region and a second active region on a semiconductor substrate, and on the first active region and the first active region. Forming a first gate insulating film on the second active region, selectively removing the first gate insulating film on the second active region, and on the second active region In addition, a step of forming a natural oxide film having a thickness of 0.1 nm or more and less than 0.7 nm, and heat treatment at a temperature higher than 850 ° C. and lower than 950 ° C. in an atmosphere containing hydrogen, A step of rounding corners of the active region and reducing and removing the natural oxide film; and a second gate thinner than the first gate insulating film on the first active region from which the natural oxide film has been removed And a step of forming an insulating film. Manufacturing method.

  According to the disclosed method for manufacturing a semiconductor device, it is possible to reduce and remove a natural oxide film present on a semiconductor substrate when forming a gate insulating film, and to round the corner at the upper end of the active region. Thereby, the surface of the semiconductor substrate after the hydrogen annealing becomes flat, and the reliability of the gate insulating film to be formed later can be improved. In addition, variation in the shape of the corner at the upper end of the active region is reduced, and variation in characteristics of the MIS transistor can be suppressed.

  A method of manufacturing a semiconductor device according to one embodiment will be described with reference to FIGS.

  1 to 5 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment. FIG. 6 is a graph showing the relationship between the etching amount of the natural oxide film and the etching time. FIG. 7 is a cross-sectional TEM image showing a change in the shape of the upper end of the active region when the hydrogen annealing temperature is changed. FIG. 8 is an AFM image showing a change in the surface shape of the gate insulating film when the thickness of the natural oxide film during the hydrogen annealing is changed. FIG. 9 is a graph showing the relationship between surface irregularities after hydrogen annealing and hydrogen annealing conditions.

  First, the element isolation insulating film 12 that defines the active regions 14a and 14b is formed on the silicon substrate 10 by, for example, shallow trench isolation (STI) method (FIG. 1A). In the drawing, the active region 14a on the left side of the central element isolation insulating film 12 is a MIS transistor forming region having a thin gate insulating film. Further, the active region 14b on the right side of the central element isolation insulating film 12 is a MIS transistor forming region having a thick gate insulating film. The MIS transistor having a thin gate insulating film is not particularly limited, but is, for example, a low voltage transistor for a logic circuit. Further, the MIS transistor having a thick gate insulating film is not particularly limited, but is, for example, an intermediate voltage transistor for an input / output circuit.

  Next, a silicon oxide film is grown on the active regions 14a and 14b defined by the element isolation insulating film 12 by, for example, a thermal oxidation method, and a sacrificial oxide film 16 of a silicon oxide film is formed.

  Next, impurity ions are implanted into a predetermined region by photolithography ion implantation to form the wells 18 and 20 in the silicon substrate 10 (FIG. 1B).

  Next, the sacrificial oxide film 16 is removed by wet etching using, for example, a hydrofluoric acid aqueous solution.

  Next, a silicon oxide film 22 of, eg, a 7.5 nm-thickness is formed on the surfaces of the active regions 14a, 14b from which the sacrificial oxide film 16 has been removed by, eg, 800 ° C. water vapor (wet) oxidation (FIG. 2A). .

  Next, a photoresist film 24 that covers the active region 14b and exposes the active region 14a is formed by photolithography.

  Next, using the photoresist film 24 as a mask, wet etching is performed using, for example, a dilute hydrofluoric acid solution having a concentration of 0.25 wt% to selectively remove the silicon oxide film 22 on the active region 14a (FIG. 2B). ). At this time, the element isolation insulating film 12 is also etched together with the etching of the silicon oxide film 22, and the upper corner portion 44 of the active region 14a is exposed.

  Note that the corner 44 at the upper end of the active region 14a is a portion that appears as a corner when the cross-sectional shape is viewed. At the intersection of the surface of the active region 14a and the element isolation insulating film 12 in the active region 14a. It is a corner formed.

  Next, for example, ashing using oxygen plasma and chemical treatment using a mixed solution of sulfuric acid and hydrogen peroxide (SPM) are performed to remove the photoresist film 24.

  Next, a cleaning process (SC1 cleaning) using a mixed solution of ammonia water and hydrogen peroxide solution (APM: Ammonia hydrogen Peroxide Mixture) is performed to remove particles and organic substances on the silicon substrate 10.

  Next, a cleaning process (SC2 cleaning) using a mixed liquid of hydrochloric acid and hydrogen peroxide (HPM: Hydrochloric acid hydrogen Peroxide Mixture) is performed to remove metal impurities on the silicon substrate 10.

  As a result of these cleaning processes, a natural oxide film 26 of, eg, a 1.0 nm-thickness is formed on the surface of the active region 14a (FIG. 3A). In particular, the film thickness of the natural oxide film formed through the oxygen plasma process and the SPM process is thicker than when only the SC1 cleaning and the SC2 cleaning are performed.

  In this specification, the natural oxide film refers to an incomplete oxide film including an oxide film formed by leaving the wafer in the atmosphere and a chemical oxide film formed by chemical treatment. The natural oxide film has incomplete crystallinity, low density, and low characteristics as an insulating layer, as compared with a thermal oxide film excellent in film quality.

Next, a diluted hydrofluoric acid aqueous solution having a hydrofluoric acid concentration of about 0.25 wt% or less, for example, HF: H ₂ O = 1: 700 is used, and the film thickness of the natural oxide film 26 on the active region 14a is 0.1 nm or more, 0 The natural oxide film 26 is wet-etched so as to be less than 7 nm (FIG. 3B). In the wet etching of the natural oxide film 26, it is desirable to use a single wafer processing apparatus from the viewpoint of shortening the processing time, but an immersion batch processing apparatus may be used. The semiconductor substrate 10 after the wet etching is washed with water and dried.

  The film thickness of the natural oxide film 26 is set to 0.1 nm or more because when the natural oxide film 26 is completely removed, the active surface of the silicon substrate 10 is exposed, and particles are adhered by washing with water after washing. This is because it tends to occur. The reason why the thickness of the natural oxide film 26 is less than 0.7 nm will be described later. Note that this wet etching step is not necessarily required when the film thickness of the natural oxide film immediately after the cleaning treatment is 0.1 nm or more and less than 0.7 nm.

  Here, for example, the natural oxide film 26 is wet-etched by 0.5 nm, and the film thickness of the natural oxide film 26 is 0.5 nm. Along with this wet etching, the silicon oxide film 22 on the active region 14b is also wet etched, and the thickness of the silicon oxide film 22 becomes 7 nm.

  FIG. 6 is a graph showing the relationship between the etching amount of the natural oxide film and the etching time when a hydrofluoric acid aqueous solution having a hydrofluoric acid concentration of 0.25 wt% is used.

  As shown in FIG. 6, it can be seen that the relationship between the etching time and the etching amount of the natural oxide film is proportional, and its variation is very small. By setting the hydrofluoric acid concentration to a low concentration of about 0.25 wt% or less, the etching film thickness can be accurately controlled on the order of 0.1 nm by the etching time.

  The hydrofluoric acid concentration of the hydrofluoric acid aqueous solution is not particularly limited as long as the etching amount of the natural oxide film can be controlled on the order of 0.1 nm, and the hydrofluoric acid concentration is not necessarily lower than 0.25 wt%. Further, as the etching solution, a chemical solution other than the hydrofluoric acid aqueous solution may be used.

  Next, heat treatment (hereinafter referred to as “hydrogen annealing”) is performed in an atmosphere containing hydrogen at a temperature higher than 850 ° C. and lower than 950 ° C., for example, 900 ° C. for 10 seconds. By this hydrogen annealing, the natural oxide film 26 having a thickness of less than 0.7 nm is reduced and removed. Further, the corner 44 at the upper end of the active region 14a is rounded by migration of silicon atoms by heat treatment (FIG. 4A).

  The atmosphere of hydrogen annealing is not particularly limited as long as hydrogen is contained. When a hydrogen atmosphere is used, it can be performed at a pressure of 100 Torr or less, for example, a pressure of 20 Torr. In addition to a hydrogen atmosphere, a mixed gas atmosphere of hydrogen and an inert gas (for example, nitrogen or argon) may be used. In this case, it can be performed under normal pressure or reduced pressure.

  The reason why the hydrogen annealing temperature is higher than 850 ° C. is that the corner 44 at the end of the active region 14a cannot be sufficiently rounded at a temperature of 850 ° C. or lower. The reason why the temperature of hydrogen annealing is set to a temperature lower than 950 ° C. is that the migration of the end of the active region 14 a is too large at a temperature of 950 ° C. or higher so that the active region 14 a covers the element isolation insulating film 12. This is because it becomes a simple umbrella shape.

  FIG. 7 is a cross-sectional TEM image showing the shape of the element isolation insulating film and the active region after hydrogen annealing. FIG. 7A shows a case where the heat treatment temperature is 900 ° C., and FIG. 7B shows a case where the heat treatment temperature is 1000 ° C.

  When hydrogen annealing is performed at 900 ° C., as shown in FIG. 7B, the corner of the end of the active region is rounded, and no protrusion toward the element isolation insulating film is observed. On the other hand, when hydrogen annealing is performed at 1000 ° C., as shown in FIG. 7B, the upper end portion of the active region has an umbrella shape protruding toward the element isolation insulating film.

  In the process of FIG. 3B, the film thickness of the natural oxide film 26 is set to a film thickness of less than 0.7 nm when the natural oxide film 26 having a film thickness of 0.7 nm or more is formed. This is because the natural oxide film cannot be completely removed by annealing.

  In the semiconductor device manufacturing method according to the present embodiment, by setting the hydrogen annealing temperature to less than 950 ° C., the upper end portion of the active region is suppressed from projecting toward the element isolation insulating film and becoming an umbrella shape. However, when the heat treatment temperature is lowered, the reducing action of the natural oxide film is lowered, and thus the natural oxide film may not be completely removed. Specifically, when the thickness of the natural oxide film is 0.7 nm or more, the natural oxide film cannot be reduced and removed by hydrogen annealing at a temperature lower than 950 ° C. Therefore, in order to completely remove the natural oxide film while suppressing the upper end portion of the active region from becoming an umbrella shape, the thickness of the natural oxide film at the time of hydrogen annealing is set to a thickness of less than 0.7 nm.

  FIG. 8 is an AFM image showing the result of photographing the surface state of the active region after forming the gate insulating film with an atomic force microscope (AFM). 8A to 8E show the cases where the film thickness of the natural oxide film during hydrogen annealing is 0.8 nm, 0.7 nm, 0.55 nm, 0.35 nm, and 0.25 nm, respectively. The thickness of the gate insulating film in the sample used for imaging is 1 nm.

  When the thickness of the natural oxide film is 0.7 nm or more, as shown in FIGS. 8A and 8B, the surface of the gate insulating film is uneven. This is considered to occur because only part of the natural oxide film is removed by hydrogen annealing. It has also been found that when the natural oxide film has a thickness of 0.7 nm or more, variation in shape occurs due to insufficient migration at the edge of the active region.

  On the other hand, by setting the film thickness of the natural oxide film to less than 0.7 nm, as shown in FIGS. 8C to 8E, the formation of irregularities on the surface of the gate insulating film is prevented. And a good surface condition could be obtained. This is presumably because the natural oxide film was uniformly removed by hydrogen annealing.

  FIG. 9 is a graph showing the relationship between surface irregularities after hydrogen annealing and hydrogen annealing conditions. The vertical axis represents the unevenness of the surface irregularities in terms of root mean square (RMS). In the figure, A is the case where the thickness of the natural oxide film is 0.8 nm and the heat treatment temperature is 950 ° C. B is a case where the film thickness of the natural oxide film is 0.5 nm and the heat treatment temperature is 950 ° C. C is the case where the film thickness of the natural oxide film is 0.5 nm and the heat treatment temperature is 850 ° C.

  As shown in FIG. 9, the surface unevenness greatly depends on the film thickness of the natural oxide film. The surface roughness when the natural oxide film thickness is 0.8 nm is about 0.36 nm (see A in the figure), whereas the surface roughness when the natural oxide film thickness is 0.5 nm is It was about 0.12 nm (see B and C in the figure). Regarding the surface irregularities, no significant difference was observed between the case where the heat treatment temperature was 850 ° C and the case where it was 950 ° C.

  Next, a silicon oxide film 28 of, eg, a 1.2 nm-thickness is formed on the active region 14a from which the natural oxide film 26 has been removed by, eg, dry oxidation. By this heat treatment, the silicon oxide film 20 is also additionally oxidized to form a silicon oxide film 30 having a film thickness of about 7.1 nm (FIG. 4B).

  The surface of the silicon substrate 10 after hydrogen annealing is relatively stable because the dangling bonds of silicon are terminated with hydrogen. However, when exposed to the atmosphere after the hydrogen annealing and before the formation of the silicon oxide films 28 and 30, a natural oxide film may be newly grown. From the viewpoint of preventing this, it is desirable to form the silicon oxide films 28 and 30 in the same processing chamber as that in which the hydrogen annealing is performed, or in a processing chamber in which the substrate can be transferred without breaking the vacuum.

Next, if necessary, nitriding is performed in an atmosphere containing nitrogen, for example, in a gas atmosphere such as N ₂ O or NO, and nitrogen is introduced into the silicon oxide films 28 and 30. In the relatively thin silicon oxide film 28, the introduced nitrogen migrates, and a silicon oxynitride film or a silicon nitride film is formed in the vicinity of the interface with the silicon substrate. As a method for introducing nitrogen, in addition to thermal nitridation, nitrogen may be introduced into the silicon oxide films 28 and 30 using active nitrogen.

  Thus, the gate insulating film 32 formed of the silicon oxide film 28 into which nitrogen is introduced is formed on the active region 14a, and the gate insulating film formed of the silicon oxide film 30 into which nitrogen is introduced is formed on the active region 14b. A film 34 is formed.

  Next, a polysilicon film of, eg, a 150 nm-thickness is deposited on the entire surface by, eg, CVD.

  Next, the polysilicon film is patterned by photolithography and dry etching to form gate electrodes 36 and 38 of the polysilicon film on the gate insulating films 32 and 34, respectively (FIG. 5A).

  Next, in the same manner as in the ordinary MIS transistor manufacturing method, the sidewall insulating film 40, the source / drain regions 42, etc. are formed, the MIS transistor having the thin gate insulating film 32, and the MIS transistor having the thick gate insulating film 34. Is completed (FIG. 5B).

  As described above, according to the present embodiment, after the natural oxide film is formed to a thickness of 0.1 nm or more and less than 0.7 nm, hydrogen annealing is performed at a temperature higher than 850 ° C. and lower than 950 ° C. The film can be uniformly reduced and removed, and the upper end corner of the active region can be rounded into a good shape. Thereby, the surface of the semiconductor substrate after the hydrogen annealing becomes flat, and the reliability of the gate insulating film to be formed later can be improved. In addition, variation in the shape of the corner at the upper end of the active region is reduced, and variation in characteristics of the MIS transistor can be suppressed.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above-described embodiment, an example in which the thin gate insulating film is formed in a multi-gate structure device having two types of MIS transistors having different gate insulating film thicknesses is shown. However, the disclosed manufacturing method is applied. Possible processes are not limited to this. For example, in a multi-gate structure device having three or more types of MIS transistors having different gate insulating film thicknesses, the disclosed method can be applied to the formation process of other gate insulating films excluding the thickest gate insulating film. Further, the present invention may be applied not only to a multi-gate structure device but also to a semiconductor device having a single gate insulating film thickness.

  In the above embodiment, an example is shown in which the present invention is applied to the process of forming a gate insulating film of a normal MIS transistor having a single-layer gate electrode. However, the disclosed manufacturing method is applied to a transistor having a plurality of gate electrodes, for example, You may apply to the formation process of the tunnel gate insulating film of the non-volatile memory transistor of a stack gate structure.

  In the above embodiment, an example in which the disclosed manufacturing method is applied to a manufacturing process of a semiconductor device formed on a silicon substrate has been described. However, as a substrate, not only a bulk silicon substrate but also a silicon layer on at least a surface is provided. A substrate having an SOI substrate, for example, an SOI substrate can also be used.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1) Forming an element isolation insulating film for defining an active region on a semiconductor substrate;
Forming a natural oxide film having a thickness of 0.1 nm or more and less than 0.7 nm on the active region;
Performing a heat treatment at a temperature higher than 850 ° C. and lower than 950 ° C. in an atmosphere containing hydrogen, rounding corners of the active region, and reducing and removing the natural oxide film;
And a step of forming a gate insulating film on the active region from which the natural oxide film has been removed.

(Additional remark 2) In the manufacturing method of the semiconductor device of Additional remark 1,
After the natural oxide film is removed, the gate insulating film is formed without exposing the semiconductor substrate to the atmosphere.

(Additional remark 3) The process of forming the element isolation insulating film which defines a 1st active region and a 2nd active region in a semiconductor substrate,
Forming a first gate insulating film on the first active region and the second active region;
Selectively removing the first gate insulating film on the second active region;
Forming a natural oxide film having a thickness of 0.1 nm or more and less than 0.7 nm on the second active region;
Performing a heat treatment at a temperature higher than 850 ° C. and lower than 950 ° C. in an atmosphere containing hydrogen, rounding corners of the second active region, and reducing and removing the natural oxide film;
Forming a second gate insulating film thinner than the first gate insulating film on the first active region from which the natural oxide film has been removed.

(Additional remark 4) In the manufacturing method of the semiconductor device of Additional remark 3,
After the natural oxide film is removed, the second gate insulating film is formed without exposing the semiconductor substrate to the atmosphere. A method for manufacturing a semiconductor device, comprising:

(Appendix 5) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 4,
The step of forming the natural oxide film includes the step of forming the natural oxide film having a film thickness of 0.7 nm or more, the etching of the natural oxide film, and the natural oxide film being 0.1 nm or more and less than 0.7 nm. And a method of manufacturing the semiconductor device.

(Additional remark 6) In the manufacturing method of the semiconductor device of Additional remark 5,
In the step of etching the natural oxide film, the natural oxide film is etched using a hydrofluoric acid aqueous solution.

(Appendix 7) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 6,
The step of forming the natural oxide film includes a step of treating the semiconductor substrate with a mixed solution of sulfuric acid and hydrogen peroxide solution.

(Supplementary note 8) In the method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 7,
The method for manufacturing a semiconductor device, wherein the atmosphere containing hydrogen is a hydrogen atmosphere or an atmosphere containing a mixed gas of hydrogen and an inert gas.

(Supplementary note 9) In the method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 8,
The method for manufacturing a semiconductor device, wherein the semiconductor substrate is a substrate having at least a silicon surface layer.

(Appendix 10) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 9,
The method for manufacturing a semiconductor device, wherein the gate insulating film is a silicon oxide film.

(Appendix 11) In the method for manufacturing a semiconductor device according to any one of appendices 1 to 10,
In the step of forming the element isolation insulating film, the element isolation insulating film is formed by a shallow trench isolation method.

FIG. 1 is a process cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 2 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 3 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 4 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 5 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 6 is a graph showing the relationship between the etching amount of the natural oxide film and the etching time. FIG. 7 is a cross-sectional TEM image showing a change in the shape of the upper end of the active region when the hydrogen annealing temperature is changed. FIG. 8 is an AFM image showing a change in the surface shape of the gate insulating film when the thickness of the natural oxide film during the hydrogen annealing is changed. FIG. 9 is a graph showing the relationship between surface irregularities after hydrogen annealing and hydrogen annealing conditions.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Element isolation insulating film 14 ... Active region 16 ... Sacrificial oxide film 18, 20 ... Well 22, 28, 30 ... Silicon oxide film 24 ... Photoresist film 26 ... Natural oxide film 32, 34 ... Gate insulating film 36, 38 ... Gate electrode 40 ... Side wall insulating film 42 ... Source / drain region 44 ... Corner of active region

Claims (6)

Forming an element isolation insulating film for defining an active region on a semiconductor substrate;
Forming a natural oxide film having a thickness of 0.1 nm or more and less than 0.7 nm on the active region;
Performing a heat treatment at a temperature higher than 850 ° C. and lower than 950 ° C. in an atmosphere containing hydrogen, rounding corners of the active region, and reducing and removing the natural oxide film;
And a step of forming a gate insulating film on the active region from which the natural oxide film has been removed. Forming an element isolation insulating film for defining a first active region and a second active region on a semiconductor substrate;
Forming a first gate insulating film on the first active region and the second active region;
Selectively removing the first gate insulating film on the second active region;
Forming a natural oxide film having a thickness of 0.1 nm or more and less than 0.7 nm on the second active region;
Performing a heat treatment at a temperature higher than 850 ° C. and lower than 950 ° C. in an atmosphere containing hydrogen, rounding corners of the second active region, and reducing and removing the natural oxide film;
Forming a second gate insulating film thinner than the first gate insulating film on the first active region from which the natural oxide film has been removed. The method of manufacturing a semiconductor device according to claim 2.
After the natural oxide film is removed, the second gate insulating film is formed without exposing the semiconductor substrate to the atmosphere. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The step of forming the natural oxide film includes the step of forming the natural oxide film having a film thickness of 0.7 nm or more, the etching of the natural oxide film, and the natural oxide film being 0.1 nm or more and less than 0.7 nm. And a method of manufacturing the semiconductor device. In the manufacturing method of the semiconductor device of any one of Claims 1 thru / or 4,
The step of forming the natural oxide film includes a step of treating the semiconductor substrate with a mixed solution of sulfuric acid and hydrogen peroxide solution. In the manufacturing method of the semiconductor device according to any one of claims 1 to 5,
The method for manufacturing a semiconductor device, wherein the atmosphere containing hydrogen is a hydrogen atmosphere or an atmosphere containing a mixed gas of hydrogen and an inert gas.