KR20070056749A - Manufacturing method for recess channel transistor with improved refresh characteristics - Google Patents

Abstract

A method for manufacturing a recess channel transistor is provided to prevent the generation of leakage current by preventing the concentration of electric field on an edge portion of a recess groove using a wet etching process capable of forming roundly the edge portion of the recess groove. A recess groove is formed on a semiconductor substrate(100) by using a selective etching process. A wet etching process is performed on the recess groove to prevent the damage due to the recess groove forming process and to form roundly an edge portion of the recess groove. A gate(440) for filling the recess groove is formed on the resultant structure via a gate dielectric film. Source/drain junction regions(490) are formed at predetermined portions adjacent to the gate in the substrate.

Description

Manufacturing method for recess channel transistor with improved refresh characteristics

1 is a cross-sectional view schematically illustrating a conventional recess channel transistor.

2 to 8 are cross-sectional views schematically illustrating a method of manufacturing a recess channel transistor according to an exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a recess channel transistor having improved refresh characteristics.

In order to overcome the deterioration of characteristics due to the high integration of semiconductor devices, the introduction of transistors having a three-dimensional structure has been proposed. For example, a recess channel transistor is introduced, which secures an effective channel length by introducing a recess channel for eliminating short channel effects.

1 is a cross-sectional view schematically illustrating a conventional recess channel transistor.

Referring to FIG. 1, a recess channel transistor includes a recess groove 12 for a recess channel in an active region 11 of the semiconductor substrate 10, and includes the recess groove 12. It can be configured to include a gate 44 to fill. In this case, the active region 11 is set by an isolation region including an insulating layer 15 and a buffer layer 16, and the recess groove 12 selectively selects a part of the active region 11. It is implemented by forming a groove by etching.

In this case, the gate 44 may be formed along with the gate dielectric layer 30, and may include a polysilicon layer 41 and a tungsten silicide layer (WSi _X : 43). A capping layer 45 may be introduced above the gate 44, and a spacer 47 may be introduced on the sidewalls of the gates 44. In addition, a junction region 49 for source / drain is formed in a portion of the active region 11 adjacent to the gate 44.

However, as the recess groove 12 is formed by selective etching, the profile of the inlet edge of the recess groove 12, ie, the upper edge portion 50 of the groove, is very sharp edge angle. It is to be formed in the shape having. By the way, the junction region 49 is formed in the very sharp edge portion 50, and at this time, the edge shape 50 between the gate 44 and the junction region 49 is formed by the sharp shape of the edge portion 50. The electric field is very concentrated. Accordingly, the dopant in the edge portion 50 is subjected to very concentrated electrical stress, and accordingly, the refresh characteristic of the transistor is greatly deteriorated.

An object of the present invention is to provide a transistor manufacturing method capable of improving the refresh characteristics of the recess channel transistor.

One aspect of the present invention for achieving the above technical problem, the step of selectively etching the semiconductor substrate to form a recess (recess) groove, the wet cleaning of the surface of the semiconductor substrate in which the recess groove is formed by the etching Rounding the inlet edge of the recess groove to mitigate damage, forming a gate filling the recess groove with a gate dielectric layer, and in the portion of the semiconductor substrate adjacent to the gate. A method of manufacturing a recess channel transistor including forming a junction region for a source / drain is provided.

Or forming a hard mask on the semiconductor substrate, selectively etching the portion of the semiconductor substrate exposed by the hard mask to form a recess groove, removing the hard mask, and the recess groove Wet cleaning the surface of the formed semiconductor substrate to mitigate damage due to the etching and rounding an inlet edge of the recess groove, and forming a gate filling the recess groove with a gate dielectric layer And forming a junction region for a source / drain in the portion of the semiconductor substrate adjacent to the gate.

The wet cleaning may include a first washing step using a wet solution containing sulfuric acid and hydrogen peroxide, a second washing step using a wet solution including a buffer oxide etchant (BOE), and a standard cleaning solution 1 (SC-1). A third cleaning step using a wet liquid is performed, and the first cleaning may be performed before the second cleaning or after the second cleaning.

Before or after the wet cleaning, the method may further include forming a screen oxide film for ion implantation on the surface of the semiconductor substrate, and performing ion implantation on the semiconductor substrate on which the screen oxide film is formed.

The ion implantation may include forming an ion implantation mask that exposes a region for deep N wells, cell wells or N wells in the semiconductor substrate, and performing ion implantation on a portion of the semiconductor substrate exposed to the ion implantation mask. And removing the ion implantation mask, wherein the wet cleaning may be performed subsequent to the removal of any one of the ion implantation masks.

According to the present invention, a transistor manufacturing method capable of improving the refresh characteristics of a recess channel transistor can be provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it should not be construed that the scope of the present invention is limited by the embodiments described below. Embodiments of the invention are preferably interpreted to be provided to those skilled in the art to more fully describe the invention.

According to an embodiment of the present invention, a recess groove for a recess channel is formed by partially etching an active region of a semiconductor substrate, and then, by relieving the sharp angle of the upper edge portion of the inlet of the recess groove, the technique is to round the recess groove. To present. As a result, the sharp angle of the inlet edge portion can be alleviated to induce a smooth profile, whereby the electric field is concentrated on the inlet edge portion, thereby effectively preventing the refresh characteristic from deteriorating.

This rounding of the recess groove inlet edge portion removes a poly silicon hard mask, which is preferably introduced into the etch mask when forming the recess groove, and then oxides the active region of the semiconductor surface. It may be performed by washing using a wet liquid containing a buffer oxide etchant (BOE) exhibiting etching characteristics.

The wet cleaning step for rounding may be performed before the ion implantation process for forming a transistor, for example, a process of forming a deep N well, a cell well or an N well. In this case, the wet cleaning may be introduced after the pad oxide layer or the screen oxide layer is formed to protect the surface of the semiconductor substrate during ion implantation. Alternatively, after performing the ion implantation process, the wet cleaning may be performed subsequent to the process of removing any one of the photoresist ion implantation masks which are preferably introduced into these ion implantation processes.

Such wet cleaning may also be understood as a process of lightly etching the surface of the semiconductor substrate to simultaneously alleviate or cure the damage caused to the surface of the semiconductor substrate in the grooves generated during the recess groove etching. Can be. Thus, the cleaning step to mitigate the damage that was performed prior to stripping off the hard mask introduced for etching the groove can be preferably omitted. Of course, a cleaning step for alleviating such damage may be performed separately before or after removing the hard mask.

2 to 8 are cross-sectional views schematically illustrating a method of manufacturing a recess channel transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the device isolation region 150 for setting the active region 101 is formed on the semiconductor substrate 100 using a shallow device isolation (STI) method. In this case, the device isolation region 150 may be formed of an insulating layer including a silicon oxide layer, and a buffer layer 151 may be introduced at an interface.

A hard mask layer 210 for a hard mask to be used as an etch mask is formed in the recess groove etching for inducing the recess channel in the semiconductor substrate 100. The hard mask layer 210 may include a polysilicon layer. A photoresist pattern 250 for patterning the hard mask layer 210 is formed on the hard mask layer 210.

Referring to FIG. 3, the hard mask layer 210 is selectively etched using the photoresist pattern 250 as an etch mask to form a hard mask 211 exposing a portion of the active region 101.

Referring to FIG. 4, a portion of the active region 101 exposed by the hard mask 211 is selectively etched to form a recess groove 110 in the semiconductor substrate 100. In this case, the etching may be performed including anisotropic dry etching. Accordingly, the profile of the inlet edge of the recess groove 110 formed may have a very sharp angle according to the characteristics of the etching process.

Referring to FIG. 5, the hard mask 211 is selectively removed. As a result, both the surface of the active region 101 and the side and bottom surfaces of the recess groove 110 are exposed.

Referring to FIG. 6, the screen oxide layer 300 is formed on the surface of the active region 101. After the screen oxide film 300 is formed, the entire surface of the active region 101 is wet-cleaned. This wet cleaning may be performed by cleaning with a wet liquid comprising a buffer oxide etchant (BOE) that performs at least an etching effect on the oxide. It can be understood that BOE is a wet liquid in which ammonium fluoride (NH ₄ F): HF is mixed in an amount of approximately 20-300: 1 and mainly performs etching on an oxide.

In addition, this wet cleaning may be performed in a multistage wet cleaning process. For example, a wet solution comprising BOE, a first wash for particle removal, preferably using a wet solution containing about 4: 1 sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). A second cleaning for the oxide etch to be used, and a second cleaning solution for removing organic contaminants using a wet cleaning solution comprising standard cleaning solution 1 (SC-1), i. It can be performed including three washing steps. The order of performing these first, second and third cleanings may be combined differently as the case may be. For example, the first wash may be performed before or after the second wash.

The wet cleaning process may serve to etch some or all of the oxide layer on the surface of the active region 101, for example, a screen oxide film or a natural oxide film, and may also remove a particle or an organic material. . At this time, the inlet edge portion 105 of the recess groove 110 may be etched to reduce the angle in a round (round).

This may be understood that the etching angle of the inlet edge portion 105 is partially etched away by etching to an oxide such as BOE. Thus, as shown in FIG. 6, the profile of the inlet edge of the recess groove 110 is rounded to have a gentler profile.

Meanwhile, the wet cleaning process may be performed before the screen oxide film (or pad oxide film 300) is formed, or may be performed after the screen oxide film 300 is formed. When the wet cleaning process is performed immediately after removal of the hard mask 250 before the screen oxide film 300 is formed, the inlet edge portion 105 of the recess groove 110 is formed by a wet liquid such as BOE. It can be etched and rounded by geometric influences.

In addition, after the screen oxide film 300 is formed on the active region 101 immediately after the hard mask 250 is removed, the screen oxide film 300 is preferably formed by a thermal oxidation method when performing a wet cleaning process. As part and / or all may be removed during the wet cleaning process, the inlet edge portion 105 of the recess groove 110 may be etched and rounded by structural geometric effects.

When the wet cleaning process is performed after the screen oxide layer 300 is formed, the wet cleaning process may be performed before or after the ion implantation process introduced into the transistor formation process. For example, ion implantation processes for forming various types of wells may be performed in a process of forming a transistor, and an ion implantation mask including a photoresist pattern (not shown) may be introduced into each ion implantation process. Can be. Therefore, the wet cleaning procedure described above may be performed after the removal of this ion implantation mask.

The wells may be deep N wells, cell wells or N wells, the process of removing the ion implantation mask of any one of the ion implantation masks introduced in each process of forming these wells. In addition, the wet cleaning process may be performed immediately after the PR strip to round the inlet edge portion 105 of the recess groove 110.

As such, after performing the wet cleaning process of rounding the inlet edge portion 105 of the recess groove 110, subsequent transistor formation processes may be performed.

Referring to FIG. 7, after rounding the inlet edge portion 105 of the recess groove 110, a gate dielectric layer 350 is formed on the exposed surface of the active region 101. The gate dielectric layer 350 may include a silicon oxide layer by thermal oxidation or the like, or may include an oxide layer by CVD or the like. Before the gate dielectric layer 350 is formed, the screen oxide film 300 or the natural oxide film may be removed. Alternatively, the screen oxide film 300 may be removed by a wet cleaning process for rounding. The gate dielectric layer 350 may be formed.

Referring to FIG. 8, the gate 440 may be formed by forming and patterning a layer for the gate filling the recess groove 110. In this case, the gate 440 may preferably be formed to include the conductive polysilicon layer 410 and the tungsten silicide layer 430, and the gate 440 may be formed on the upper side of the gate 440 to protect the gate 400 in a subsequent process. The cap layer 450 may be formed including silicon nitride. In addition, when the junction region 490 for source and drain is formed using a lightly doped drain (LDD) structure, the sidewall spacer 470 preferably includes silicon nitride on the sidewall of the gate 440. Can be formed.

The transistor structure formed as described above may have a structure in which the effective effective channel length is further extended by the introduction of the recess groove 110. At this time, the inlet edge portion 105 of the recess groove 110 has a round profile, so that an electric field between the junction region 490 and the gate 440 is concentrated on the inlet edge portion 105. Can be prevented. Therefore, it is possible to prevent the electrical stress of the dopant ion-implanted into the junction region 490 by the concentration of the electric field undesirably increased.

Accordingly, large leakage of current in the inlet edge portion 105 can be effectively prevented, thereby improving the refresh characteristics of the memory device including the transistor. For example, about 10 to 20% of the refresh characteristic improvement can be realized as compared to the conventional case. This may be understood to mean a refresh characteristic or time improvement of about 550 to 600 ms compared to the existing 500 ms, that is, an improvement of refresh time of about 50 to 100 ms.

According to the present invention described above, by rounding the profile of the inlet edge portion of the recess groove formed to induce the recess channel to have a gentle profile, the electric field is concentrated on this edge portion so that the current leakage of the transistor is achieved. This can be effectively prevented from occurring.

This rounding of the inlet edge portion may be achieved by a wet cleaning process which is preferably performed after the formation of the screen oxide film after removal of the hard mask for forming the recess groove. Accordingly, it is possible to realize improvement of the refresh characteristics of the transistor by electric field concentration simply without combining a complicated process.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

Claims (5)

Selectively etching the semiconductor substrate to form a recess groove; Wet cleaning the surface of the semiconductor substrate on which the recess groove is formed to mitigate damage due to the etching and to round the inlet edge of the recess groove; Forming a gate filling the recess groove with a gate dielectric layer; And Forming a junction region for a source / drain in the portion of the semiconductor substrate adjacent to the gate. Forming a hard mask on the semiconductor substrate; Selectively etching a portion of the semiconductor substrate exposed by the hard mask to form a recess groove; Removing the hard mask; Wet cleaning the surface of the semiconductor substrate on which the recess groove is formed to mitigate damage due to the etching and to round the inlet edge of the recess groove; Forming a gate filling the recess groove with a gate dielectric layer; And Forming a junction region for a source / drain in the portion of the semiconductor substrate adjacent to the gate. The method of claim 2, The wet cleaning is A first washing step using a wet liquid containing sulfuric acid and hydrogen peroxide; A second washing step using a wet liquid including a buffer oxide etchant (BOE); A third wash step using a wet liquid comprising standard wash solution 1 (SC-1); And the first cleaning is performed before the second cleaning or after the second cleaning. The method of claim 2, Before or after the wet cleaning Forming a screen oxide film for ion implantation on a surface of the semiconductor substrate; And And performing ion implantation into the semiconductor substrate on which the screen oxide film is formed. The method of claim 4, wherein The ion implantation Forming an ion implantation mask in the semiconductor substrate that exposes a region for a deep N well, cell well or N well; Performing ion implantation into a portion of the semiconductor substrate exposed to the ion implantation mask; And Removing the ion implantation mask, And wherein said wet cleaning is performed following removal of any one of said ion implantation masks.

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