KR20130017463A - Growth substrate, nitride semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A substrate for growing a semiconductor, a nitride semiconductor device, and a manufacturing method thereof are provided to reduce a crystal defect due to lattice constant mismatch between a first GaN semiconductor layer and a silicon substrate by forming a buffer layer made of aluminum nitride between the first GaN semiconductor layer and the silicon substrate. CONSTITUTION: A buffer layer(113) is formed on a silicon substrate(111). A diffusion preventing layer(115) is formed on the buffer layer. A first GaN semiconductor layer(117) is formed on the diffusion preventing layer. An AlN semiconductor layer(119) is formed on the first GaN semiconductor layer. A second GaN semiconductor layer(120) is formed on the AlN semiconductor layer.

Description

Substrate for semiconductor growth, nitride semiconductor device and manufacturing method thereof {GROWTH SUBSTRATE, NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

Embodiments relate to a growth substrate, a nitride semiconductor device, and a method of manufacturing the same.

Gallium nitride (GaN) is a semiconductor material with a direct transition bandgap of 3.4 eV at room temperature, and when combined with other semiconductor materials such as indium nitride (InN) or aluminum nitride (AlN), 1.9 eV ( InN) has an energy band gap of 3.4 eV (GaN) or 6.2.eV (AlN). Therefore, gallium nitride has a great potential as an optical device in a wide wavelength range from the visible region to the ultraviolet region. Recently, the market for lighting fixtures by full color display boards or white light emitting devices by red, green and blue light emitting devices is rapidly growing. As a result, much research is being conducted on gallium nitride. In particular, gallium nitride has attracted great attention as an optical device material of a blue light emitting diode (LED) and a blue laser diode (LD) in a short wavelength band.

In order to fabricate an optical device using gallium nitride, a technique for thickly growing a gallium nitride thin film without crystal defects such as dislocations is important. For thick film growth of a gallium nitride thin film, it is important to select a substrate on which a gallium nitride and a lattice constant match. This is because when the degree of lattice constant mismatch between the gallium nitride and the substrate is large, there is a limit to growing gallium nitride of good quality due to the difference in the coefficient of thermal expansion.

In general, substrates that can be used for growing a gallium nitride thin film include a silicon carbide (SiC) substrate and a sapphire (Al ₂ O ₃ ) substrate. Among these, silicon carbide substrates have a small lattice constant difference with gallium nitride, and have excellent high temperature characteristics and chemical stability. However, since the substrate price is high and the production volume is low, there is a problem in smooth substrate supply and the nitride grown on the substrate compared to the efficiency of optical device manufacturing. There is a disadvantage that the quality of the gallium thin film is not excellent. For this reason, sapphire substrates are mainly used for growth of gallium nitride thin films rather than silicon carbide substrates.

However, since the a-axis lattice constant of sapphire (hexagonal system) is 4.758Å and the a-axis lattice constant of gallium nitride (hexagonal) is 3.186Å, gallium nitride and sapphire show a lattice constant mismatch of about 30% or more. Therefore, when the gallium nitride thin film is grown on the sapphire substrate, tensile stress may be caused by a-axis lattice constant mismatch. However, when the gallium nitride thin film is actually grown on the sapphire substrate, compressive strain occurs because the effective lattice constant of sapphire is about 14% smaller than the effective lattice constant of gallium nitride. In addition, sapphire and gallium nitride have a thermal expansion coefficient of about 25%, which causes stress at the boundary between the sapphire substrate and the gallium nitride thin film. As a result, 10 ¹⁴ / cm ² Dislocation defects having a high density of degree have been introduced, which is an obstacle to high quality single crystal growth. In addition, when the gallium nitride thin film is grown to a thickness of 10 μm or more, cracks are more likely to occur in the gallium nitride thin film due to excessive stress generated due to mismatch in crystal lattice constant and difference in coefficient of thermal expansion.

In order to solve the above problems, research on the growth of a gallium nitride thin film using a silicon substrate as an alternative to a sapphire substrate and a silicon carbide substrate is being actively conducted.

The embodiment provides a nitride semiconductor device having a new buffer structure layer and a method of manufacturing the same.

The embodiment provides a nitride semiconductor device including a diffusion barrier layer between a silicon substrate and a gallium nitride-based semiconductor layer, and a method of manufacturing the same.

The embodiment provides a nitride semiconductor device including a diffusion barrier layer formed on a region thinner than other regions of a portion of a buffer layer, and a method of manufacturing the same.

The embodiment provides a growth substrate having a buffer layer having roughness on top of a silicon substrate and a diffusion barrier layer on a portion thereof.

According to an embodiment, a nitride semiconductor device may include a silicon substrate; A buffer layer having an upper surface roughened on the silicon substrate; A diffusion barrier layer on a portion of the roughness of the buffer layer; And a first gallium nitride based semiconductor layer on the diffusion barrier layer.

According to an embodiment, a method of manufacturing a nitride semiconductor device may include forming a buffer layer including a first aluminum nitride layer on a silicon substrate; Forming an amorphous diffusion barrier layer on the first aluminum nitride layer; And forming a first gallium nitride based semiconductor layer on the buffer layer and the diffusion barrier layer.

Growth substrate according to the embodiment, a silicon substrate; A buffer layer including roughness on an upper surface of the silicon substrate; And a diffusion barrier layer on a portion of the roughness.

The embodiment can relieve stress caused by crystal lattice mismatch and thermal expansion difference between the silicon substrate and the gallium nitride based semiconductor layer.

The embodiment can effectively block crystal defects such as dislocations propagating over the silicon substrate, thereby improving the crystal quality of the semiconductor layer.

The embodiment can provide a substrate for crack growth.

The embodiment can improve the reliability of the nitride semiconductor device and the package or lighting system including the same.

1 illustrates a nitride semiconductor device according to an embodiment.
FIG. 2 is a partially enlarged view of the buffer layer and the diffusion barrier layer of FIG. 1.
3 to 7 illustrate a method of manufacturing the nitride semiconductor device according to the embodiment.
8 is a diagram illustrating another example of the nitride semiconductor device of FIG. 1.
9 is a view illustrating a light emitting device package having the light emitting device of FIG. 8.
10 to 12 illustrate a lighting system having the light emitting device package of FIG. 9.

In the description of an embodiment, each layer (film), region, pattern or structure is formed to be "on" or "under" the substrate, each layer (film), region, pad or pattern. In the case described, "on" and "under" include both the meanings of "directly" and "indirectly". In addition, the criteria for above or below each layer will be described with reference to the drawings.

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. The thickness and size of each layer in the drawings are exaggerated, omitted, or schematically shown for convenience and clarity of explanation. Also, the size of each component does not entirely reflect the actual size.

1 is a view illustrating a nitride semiconductor device according to an embodiment, and FIG. 2 is a partially enlarged view of a buffer layer and a diffusion barrier layer of FIG. 1.

1 and 2, the nitride semiconductor device 100 includes a substrate 111, a buffer layer 113, a diffusion barrier layer 115, a first gallium nitride based semiconductor layer 117, and an aluminum nitride based semiconductor layer 119. ), And the second gallium nitride based semiconductor layer 120.

The substrate 111 includes a silicon-based substrate, for example, a silicon substrate, and the thermal expansion coefficient and lattice constant of the silicon substrate are 3.7 × 10 ⁻⁶ / K and 3.8403 Å, respectively. The thermal expansion coefficient of the gallium nitride layer (GaN) formed on the silicon substrate is 5.59 × 10 ⁻⁶ / K, and the lattice constant is 3.1891 Å. This silicon substrate has a difference in coefficient of thermal expansion of about 53.6% and a lattice constant of about 16.9% compared to the gallium nitride layer. The crystal structures of silicon and gallium nitride are cubic and hexagonal, respectively, and the basic crystal structures are different. Therefore, dislocation defects having a density of about 10 ¹⁰ / cm ² exist in the second gallium nitride based semiconductor layer 120 formed on the silicon substrate, and when the second gallium nitride based semiconductor layer 120 is formed thick, a thin film Stresses above the limit may be generated within the cracks. A buffer structure layer 110 is required between the silicon substrate 111 and the second gallium nitride based semiconductor layer 120 to prevent crystal defects and prevent cracking. Hereinafter, for convenience of description, the substrate 111 will be described as a silicon substrate.

In an embodiment, a buffer layer 113 is formed on the silicon substrate 111, and the buffer layer 113 may be formed of an aluminum nitride based semiconductor layer, for example, AlN. The buffer layer 113 functions as a blocking layer to block a reaction between the silicon substrate 111 and gallium (ie, TMGa), so that Ga atoms included in the first gallium nitride based semiconductor layer 117 are separated from the silicon substrate. Penetration into the (111) to block the melt back (melt back) phenomenon.

In addition, the buffer layer 113 reduces crystal defects caused by lattice constant mismatch between the first gallium nitride based semiconductor layer 117 and the silicon substrate 111 and prevents crack generation. The buffer layer 113 may be formed to a thickness of 30nm ~ 200nm.

As shown in FIG. 2, an upper surface of the buffer layer 113 is formed of roughness 114, and the roughness 114 includes a recess A1 and a convex A2, and the recess A1. And the convex part A2 is formed in an irregular shape and space | interval. Conventionally, the recess A1 of the roughness 114 is formed to have a thickness D1 thinner than other regions with respect to the upper surface of the silicon substrate 111 to form the first gallium nitride based semiconductor layer 117. As part of this easily penetrating area, there is a problem vulnerable to melt bags. The diffusion barrier layer 115 is formed in a region lower than the convex portion A1 of the buffer layer 113, that is, the upper surface of the buffer layer 113, thereby improving crystallinity of the semiconductor layer. The convex portion A2 may be defined as a valley portion, a convex portion or a recess portion, and the concave portion A2 may be defined as a floor portion, a recess portion or a groove portion.

In an embodiment, the diffusion barrier layer 115 is formed in a portion of the roughness 114 of the buffer layer 113 to block the first gallium nitride based semiconductor layer 117 from penetrating. The diffusion barrier layer 115 serves as a mask in a region A1 that is vulnerable in a junction region with the first gallium nitride based semiconductor layer 117.

The diffusion barrier layer 115 may be formed to a thickness thinner than the thickness of the buffer layer 113, for example, 0.5 to 10 nm. The diffusion barrier layer 115 is formed on the recess A1 at the roughness 114 of the buffer layer 113, and the Ga element of the first gallium nitride based semiconductor layer 117 is formed through the recess A1. And the silicon substrate 111 may be prevented from coupling. The diffusion barrier layer 115 may be formed of an amorphous material. For example, the nitride may include a SiN material. The diffusion barrier layer 115 includes an oxide material, for example, SiO ₂ . As another example, the diffusion barrier layer 115 may be formed of photoresist (PR).

The silicon substrate 111, the buffer layer 113, and the diffusion barrier layer 115 may be provided as a growth substrate, and a light emitting structure including an active layer formed of a nitride semiconductor layer or a ZnO layer may be formed on the growth substrate. It may be formed, but not limited thereto. Hereinafter, an example in which a nitride semiconductor layer is disposed on a growth substrate will be described for convenience of description.

A first gallium nitride based semiconductor layer 117 is formed on the buffer layer 113 and the diffusion barrier layer 115, and the first gallium nitride based semiconductor layer 117 includes GaN or AlGaN. The first gallium nitride based semiconductor layer 117 improves the quality of the second gallium nitride based semiconductor layer 120 by controlling crystal defects of the second gallium nitride based semiconductor layer 120 formed thereon. In addition, since the first gallium nitride based semiconductor layer 117 is formed to be close to the lower silicon substrate 111, Ga atoms included in the first gallium nitride based semiconductor layer 117 may be formed on the silicon substrate 111. There is a risk of penetration. Accordingly, the thickness of the first gallium nitride based semiconductor layer 117 may be, for example, about 30 to 200 nm, such that the Ga atom does not cause penetration into the silicon substrate 111. According to the embodiment, by forming the diffusion barrier layer 115 on the buffer layer 113, Ga atoms can be prevented from penetrating, so that the thickness of the first gallium nitride based semiconductor layer 117 can be formed to a thickness of about 30 to 600 nm. This thickness can further improve crystal defects. An upper surface of the first gallium nitride based semiconductor layer 117 may be formed as a flat or rough surface, but is not limited thereto.

The aluminum nitride based semiconductor layer 119 directly controls the defect density of the second gallium nitride based semiconductor layer 120 formed thereon to determine the quality of the second gallium nitride based semiconductor layer 120. The first aluminum nitride-based semiconductor layer 119 reduces the melt back phenomenon with the second gallium nitride-based semiconductor layer 120, and determines the crystal between the second gallium nitride-based semiconductor layer 120 and the silicon substrate 111. The stress generated due to the difference between the lattice mismatch and the coefficient of thermal expansion is alleviated to prevent cracks in the second gallium nitride based semiconductor layer 120. The aluminum nitride based semiconductor layer 119 may be formed to have a thickness of 30 to 200 nm, and may include AlN.

The second gallium nitride based semiconductor layer 120 formed on the aluminum nitride based semiconductor layer 119 may be formed of an undoped semiconductor layer or a first conductive semiconductor layer, and the undoped semiconductor layer may be a GaN based As a semiconductor layer of, it can be formed as a low conductive layer having an n-type dopant even without doping the dopant. The first conductive semiconductor layer includes an n-type semiconductor layer or a p-type semiconductor layer.

The buffer layer 113, the diffusion barrier layer 115, the first gallium nitride based semiconductor layer 117, and the aluminum nitride based semiconductor layer 119 formed on the silicon substrate 111 may emit light to be formed on the silicon substrate 111. It may be used as the buffer structure layer 120 for the compound semiconductor layer of the device, semiconductor device, light receiving device.

3 to 7 are views illustrating a manufacturing process of the nitride semiconductor device according to the embodiment.

Referring to FIG. 3, the silicon substrate 111 may be loaded into growth equipment, and may be formed in a layer or pattern form using a compound semiconductor thereon.

The growth equipment may be an electron beam evaporator, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporator sputtering, metal organic chemical vapor (MOCVD) deposition) and the like, and the like is not limited to such equipment.

After the silicon substrate 111 is loaded into the growth equipment, a thermal cleaning process using hydrogen is performed at a high temperature of 1000 to 1200 ° C. Subsequently, an Al coating layer 112 may be formed on the upper surface of the silicon substrate 111 by performing an Al coating process using a TriMethlyAlluminum (TMAl) source under the temperature condition where the thermal cleaning process is performed. The reason for forming the Al coating layer 112 is to prevent the Si atoms of the upper surface of the silicon substrate 111 from meeting with the N atoms of NH _{3 in} a subsequent buffer layer forming step.

Referring to FIG. 4, the AlN buffer layer is then reacted by flowing NH ₃ to the upper surface of the silicon substrate 111 under a hydrogen atmosphere at a growth temperature of 1000 to 1300 ° C. to react the Al coating layer 112 with NH ₃ . And form 113. Since the buffer layer 113 is formed under the same temperature condition as that of forming the Al coating layer 112, the difference in thermal expansion coefficient between the second gallium nitride based semiconductor layer and the silicon substrate 111 to be formed on the buffer structure layer. It serves to relieve the stress caused by. The buffer layer 113 may be formed to a thickness of 30 nm to 200 nm to prevent Ga atoms of the first gallium nitride based semiconductor layer formed in a subsequent process from penetrating into the silicon substrate 111.

The upper surface of the buffer layer 113 is formed of roughness 114, and the roughness 114 is formed of an irregular surface having a concave portion A1 and a convex portion A2. The recess A1 of the roughness 114 may be a portion vulnerable to the melt back phenomenon. In order to prevent this, the diffusion barrier layer 115 is formed as shown in FIG. 5.

Referring to FIG. 5, a diffusion barrier layer 115 is formed on the buffer layer 113, and the diffusion barrier layer 115 may be formed of amorphous nitride, for example, SiN. The diffusion barrier layer 115 forms SiN by flowing NH ₃ and silane (SiH ₄ ) gas to the upper surface of the silicon substrate 111 at a temperature of 1000 to 1200 ° C. and a nitrogen or / and hydrogen atmosphere. The diffusion barrier layer 115 may be grown to a predetermined thickness in the recess A1 of the buffer layer 113, and the thickness may include about 0.5 nm to about 10 nm. As the diffusion barrier layer 115 is formed in the recess A1 of the buffer layer 113, the contact between the first gallium nitride based semiconductor layer and the silicon substrate 111 may be blocked. The diffusion barrier layer 115 may be formed of an oxide such as SiO ₂ or a photoresist.

The diffusion barrier layer 115 is formed in a region lower than the convex portion A1 of the buffer layer 113, thereby forming a lateral over-growth when the first gallium nitride based semiconductor layer is grown. It can be induced to improve crystallinity.

6 and 7, when the diffusion barrier layer 115 is formed, a first gallium nitride based semiconductor layer 117 is formed on the buffer layer 113 and the diffusion barrier layer 115, and the first nitride is formed. The gallium-based semiconductor layer 117 forms a first gallium nitride-based semiconductor layer 117 by flowing TMGa (TriMethlyGalium) and NH ₃ at a temperature of 1000 to 1300 ° C. and a hydrogen atmosphere. The first gallium nitride based semiconductor layer 117 improves the quality of the second gallium nitride based semiconductor layer 120 by controlling crystal defects of the second gallium nitride based semiconductor layer 120 formed thereon. On the other hand, the first gallium nitride based semiconductor layer 117 is close to the lower silicon substrate 111, but is blocked by the buffer layer 113 and the diffusion barrier layer 115, the thickness of the melt back phenomenon does not occur As a range which does not, it can form in thickness of 30 nm-600 nm. Accordingly, Ga atoms of the first gallium nitride based semiconductor layer 117 can be prevented from penetrating into the lower silicon substrate 111.

As shown in FIG. 7, after forming the first gallium nitride based semiconductor layer 117, the aluminum nitride based semiconductor layer 119 may be formed. The aluminum nitride based semiconductor layer 119 may be formed of AlN, AlGaN, or AlGaN / AlN. TMAl and NH ₃ flow through the upper surface of the aluminum nitride semiconductor layer 119 to form the aluminum nitride semiconductor layer 119 thicker than the buffer layer 113 to complete the buffer structure layer 110.

The aluminum nitride based semiconductor layer 119 directly controls crystal defects of the second gallium nitride based semiconductor layer 120 formed thereon to determine the quality of the second gallium nitride based semiconductor layer 120. In addition, the aluminum nitride-based semiconductor layer 119 may relieve stress caused by a mismatch between crystal lattice mismatch and thermal expansion coefficient between the second gallium nitride-based semiconductor layer 120 formed on the upper side and the silicon substrate 111 on the lower side. Cracks are prevented from occurring in the gallium nitride based semiconductor layer 120. In view of this point, the aluminum nitride-based semiconductor layer 119 is preferably formed to a thickness of several tens to 100 nm.

The second gallium nitride based semiconductor layer 120 may be formed on the aluminum nitride based semiconductor layer 119. The second gallium nitride based semiconductor layer 120 may be formed of an undoped semiconductor layer or a first conductive semiconductor layer, and the undoped semiconductor layer is a GaN-based semiconductor layer, even though the dopant is not doped. It can be formed of a low conductive layer having a type dopant. The first conductive semiconductor layer includes an n-type semiconductor layer or a p-type semiconductor layer.

8 is a diagram illustrating another example of the nitride semiconductor device of FIG. 1.

Referring to FIG. 8, the light emitting device 101 includes a silicon substrate 111, a buffer structure layer 110, a second gallium nitride based semiconductor layer 120, a light emitting structure 127, an electrode layer 131, and a first electrode. And a second electrode 137.

The light emitting structure 127 includes a first conductive semiconductor layer 121, an active layer 123, and a second conductive semiconductor layer 125.

The first conductive semiconductor layer 121 is formed of a group III-V compound semiconductor doped with a first conductive dopant, for example, In _x Al _y Ga _{1 -x- y} N (0 _{≦ x ≦} 1, 0 Y? 1, 0? X + y? 1). When the first conductive semiconductor layer 121 is an n-type semiconductor layer, the dopant of the first conductive type is an n-type dopant and includes Si, Ge, Sn, Se, and Te.

The first conductive semiconductor layer 121 may be formed in a superlattice structure in which different first and second layers are alternately arranged, and the thickness of the first and second layers is formed to be several A or more. Can be.

A first cladding layer (not shown) may be formed between the first conductive semiconductor layer 121 and the active layer 123, and the first cladding layer may be formed of a GaN-based semiconductor. The first cladding layer serves to restrain the carrier. As another example, the first cladding layer (not shown) may be formed of an InGaN layer or an InGaN / GaN superlattice structure, but is not limited thereto. The first cladding layer may include an n-type and / or p-type dopant, and may be formed of, for example, a first conductive type or low conductivity semiconductor layer.

An active layer 123 is formed on the first conductive semiconductor layer 121. The active layer 123 may be formed of at least one of a single well, a single quantum well, a multi well, a multi quantum well (MQW), a quantum line, and a quantum dot structure. The active layer 123 may be alternately disposed with a well layer and a barrier layer, and the well layer may be a well layer having a continuous energy level. In addition, the well layer may be a quantum well in which the energy level is quantized. The well layer may be defined as a quantum well layer, and the barrier layer may be defined as a quantum barrier layer. The pair of the well layer and the barrier layer may be formed in 2 to 30 cycles. The well layer is, for example, may be formed of a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). The barrier layer is a semiconductor layer having a band gap wider than the band gap of the well layer. For example, In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + It can be formed from a semiconductor material having a compositional formula of y≤1). The pair of the well layer and the barrier layer includes, for example, at least one of InGaN / GaN, AlGaN / GaN, InGaN / AlGaN, InGaN / InGaN.

The active layer 123 may selectively emit light in the wavelength range of the ultraviolet band to the visible light band, for example, may emit a peak wavelength in the range of 420nm to 450nm.

A second cladding layer may be formed on the active layer 123, and the second cladding layer has a higher band gap than the band gap of the barrier layer of the active layer 123. It may be formed of a GaN-based semiconductor. For example, the second cladding layer may include GaN, AlGaN, InAlGaN, InAlGaN superlattice structure, or the like. The second clad layer may include an n-type and / or p-type dopant, and may be formed of, for example, a second conductive or low conductivity semiconductor layer.

A second conductive semiconductor layer 125 is formed on the active layer 123, and the second conductive semiconductor layer 125 includes a dopant of a second conductive type. The second conductive semiconductor layer 125 may be formed of at least one of a group III-V group compound semiconductor, for example, a compound semiconductor such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, etc., and may include a single layer or a multilayer. . When the second conductive semiconductor layer 125 is a p-type semiconductor layer, the second conductive dopant may be a p-type dopant and may include Mg, Zn, Ca, Sr, and Ba.

The conductive types of the layers of the light emitting structure 127 may be formed to be opposite to each other. For example, the second conductive semiconductor layer 125 may be an n-type semiconductor layer, and the first conductive semiconductor layer 121 may be a p-type semiconductor layer. It can be implemented as. In addition, an n-type semiconductor layer, which is a third conductive semiconductor layer having a polarity opposite to that of the second conductive type, may be further formed on the second conductive semiconductor layer 125. The semiconductor light emitting device 101 may define the first conductive semiconductor layer 121, the active layer 123, and the second conductive semiconductor layer 123 as a light emitting structure 127. 127) may include at least one of an np junction structure, a pn junction structure, an npn junction structure, and a pnp junction structure. In the n-p and p-n junctions, an active layer is disposed between two layers, and an n-p-n junction or a p-n-p junction includes at least one active layer between three layers.

An electrode layer 131 and a second electrode 137 are formed on the light emitting structure 127, and a first electrode 135 is formed on the first conductive semiconductor layer 121.

The electrode layer 131 is a current spreading layer and may be formed of a material having transparency and electrical conductivity. The electrode layer 131 may be formed at a refractive index lower than that of the compound semiconductor layer.

The electrode layer 131 is formed on an upper surface of the second conductive semiconductor layer 125, and the material is indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), or indium aluminum zinc oxide (IGZO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), ZnO, IrOx, RuOx, NiO, etc. Selected, and may be formed of at least one layer. The electrode layer 131 may be formed as a reflective electrode layer, and the material may be selectively formed among, for example, Al, Ag, Pd, Rh, Pt, Ir, and two or more alloys thereof.

The second electrode 137 may be formed on the second conductive semiconductor layer 125 and / or the electrode layer 131, and may include an electrode pad. The second electrode 137 may further include a current diffusion pattern having an arm structure or a finger structure. The second electrode 137 may be made of a non-transmissive metal having a characteristic of an ohmic contact, an adhesive layer, and a bonding layer, but is not limited thereto.

A first electrode 135 is formed on a portion of the first conductive semiconductor layer 121. The first electrode 135 and the second electrode 137 are Ti, Ru, Rh, Ir, Mg, Zn, Al, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Au, and their It can be chosen from the optional alloys. The first electrode 135 may be connected through the inside of the silicon substrate 111 through a via structure, but is not limited thereto.

An insulating layer may be further formed on the surface of the light emitting device 101, and the insulating layer may prevent an interlayer short of the light emitting structure 127 and prevent moisture penetration.

9 is a view illustrating a light emitting device package having the light emitting device of FIG. 8.

Referring to FIG. 9, the light emitting device package 200 may include a body 210, a first lead electrode 211 and a second lead electrode 212 at least partially disposed on the body 210, and the body ( The light emitting device 101 electrically connected to the first lead electrode 211 and the second lead electrode 212 on the 210 and a molding surrounding the light emitting device 101 on the body 210. The member 220 is included.

The body 210 may include a silicon material, a synthetic resin material, or a metal material. The body 210 includes a reflector 215 having a cavity therein and an inclined surface around the cavity 210 when viewed from above.

The first lead electrode 211 and the second lead electrode 212 are electrically separated from each other, and may be formed to penetrate the inside of the body 210. That is, some of the first lead electrode 211 and the second lead electrode 212 may be disposed inside the cavity, and the other part may be disposed outside the body 210.

The first lead electrode 211 and the second lead electrode 212 may supply power to the light emitting device 101, and may reflect light generated from the light emitting device 101 to increase light efficiency. It may also function to discharge the heat generated by the light emitting device 101 to the outside.

The light emitting device 101 may be installed on the body 210 or on the first lead electrode 211 or / and the second lead electrode 212.

The wire 216 of the light emitting device 101 may be electrically connected to either the first lead electrode 211 or the second lead electrode 212, but is not limited thereto.

The molding member 220 may surround the light emitting device 101 to protect the light emitting device 101. In addition, the molding member 220 may include a phosphor, and the wavelength of light emitted from the light emitting device 101 may be changed by the phosphor.

The light emitting device or the light emitting device package according to the embodiment can be applied to the illumination system. The lighting system includes a structure in which a plurality of light emitting devices or light emitting device packages are arranged, and includes a display device as shown in FIGS. 10 and 11 and a lighting device as shown in FIG. 12. Etc. may be included.

10 is an exploded perspective view of a display device according to an embodiment.

Referring to FIG. 10, the display apparatus 1000 includes a light guide plate 1041, a light emitting module 1031 providing light to the light guide plate 1041, a reflective member 1022 under the light guide plate 1041, and A bottom cover 1011 that houses an optical sheet 1051 on the light guide plate 1041, a display panel 1061 on the optical sheet 1051, the light guide plate 1041, a light emitting module 1031, and a reflective member 1022. ), But is not limited thereto.

The bottom cover 1011, the reflective sheet 1022, the light guide plate 1041, and the optical sheet 1051 can be defined as a light unit 1050.

The light guide plate 1041 serves to diffuse the light provided from the light emitting module 1031 to make a surface light source. The light guide plate 1041 is made of a transparent material, for example, acrylic resin-based such as polymethyl metaacrylate (PMMA), polyethylene terephthlate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate (PEN). It may include one of the resins.

The light emitting module 1031 is disposed on at least one side of the light guide plate 1041 to provide light to at least one side of the light guide plate 1041, and ultimately serves as a light source of the display device.

The light emitting module 1031 may include at least one, and may provide light directly or indirectly at one side of the light guide plate 1041. The light emitting module 1031 may include a board 1033 and a light emitting device package 200 according to the above-described embodiment, and the light emitting device package 200 may be arranged on the board 1033 at predetermined intervals. have. The board may be a printed circuit board, but is not limited thereto. In addition, the board 1033 may include a metal core PCB (MCPCB, Metal Core PCB), flexible PCB (FPCB, Flexible PCB) and the like, but is not limited thereto. When the light emitting device package 200 is mounted on the side surface of the bottom cover 1011 or the heat dissipation plate, the board 1033 may be removed. A part of the heat radiation plate may be in contact with the upper surface of the bottom cover 1011. Therefore, heat generated in the light emitting device package 200 may be discharged to the bottom cover 1011 via the heat dissipation plate.

The plurality of light emitting device packages 200 may be mounted on the board 1033 such that an emission surface on which light is emitted is spaced apart from the light guide plate 1041 by a predetermined distance, but is not limited thereto. The light emitting device package 200 may directly or indirectly provide light to a light incident portion, which is one side of the light guide plate 1041, but is not limited thereto.

The reflective member 1022 may be disposed under the light guide plate 1041. The reflective member 1022 reflects the light incident on the lower surface of the light guide plate 1041 and supplies the reflected light to the display panel 1061 to improve the brightness of the display panel 1061. The reflective member 1022 may be formed of, for example, PET, PC, or PVC resin, but is not limited thereto. The reflective member 1022 may be an upper surface of the bottom cover 1011, but is not limited thereto.

The bottom cover 1011 may house the light guide plate 1041, the light emitting module 1031, the reflective member 1022, and the like. To this end, the bottom cover 1011 may be provided with a housing portion 1012 having a box-like shape with an opened upper surface, but the present invention is not limited thereto. The bottom cover 1011 may be coupled to a top cover (not shown), but is not limited thereto.

The bottom cover 1011 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding. In addition, the bottom cover 1011 may include a metal or a non-metal material having good thermal conductivity, but the present invention is not limited thereto.

The display panel 1061 is, for example, an LCD panel, and includes a first and second substrates of transparent materials facing each other, and a liquid crystal layer interposed between the first and second substrates. A polarizing plate may be attached to at least one surface of the display panel 1061, but the present invention is not limited thereto. The display panel 1061 displays information by transmitting or blocking light provided from the light emitting module 1031. The display device 1000 can be applied to video display devices such as portable terminals, monitors of notebook computers, monitors of laptop computers, and televisions.

The optical sheet 1051 is disposed between the display panel 1061 and the light guide plate 1041 and includes at least one light-transmitting sheet. The optical sheet 1051 may include at least one of a sheet such as a diffusion sheet, a horizontal / vertical prism sheet, a brightness enhanced sheet, and the like. The diffusion sheet diffuses incident light, and the horizontal and / or vertical prism sheet concentrates incident light on the display panel 1061. The brightness enhancing sheet reuses the lost light to improve the brightness I will. A protective sheet may be disposed on the display panel 1061, but the present invention is not limited thereto.

The light guide plate 1041 and the optical sheet 1051 may be included as an optical member on the optical path of the light emitting module 1031, but are not limited thereto.

11 is a diagram illustrating a display device having a light emitting device package according to an exemplary embodiment.

Referring to FIG. 11, the display device 1100 includes a bottom cover 1152, a board 1120 on which the light emitting device package 200 disclosed above is arranged, an optical member 1154, and a display panel 1155. .

The board 1120 and the light emitting device package 200 may be defined as a light emitting module 1060. The bottom cover 1152, at least one light emitting module 1060, and the optical member 1154 may be defined as a light unit (not shown).

The bottom cover 1152 may include an accommodating part 1153, but is not limited thereto.

The optical member 1154 may include at least one of a lens, a light guide plate, a diffusion sheet, a horizontal and vertical prism sheet, and a brightness enhancement sheet. The light guide plate may be made of a PC material or a poly methy methacrylate (PMMA) material, and the light guide plate may be removed. The diffusion sheet diffuses the incident light, and the horizontal and vertical prism sheets condense the incident light onto the display panel 1155. The brightness enhancing sheet reuses the lost light to improve the brightness .

The optical member 1154 is disposed on the light emitting module 1060, and performs surface light source, diffusion, condensing, etc. of the light emitted from the light emitting module 1060.

12 is a perspective view of a lighting apparatus according to an embodiment.

Referring to FIG. 12, the lighting device 1500 includes a case 1510, a light emitting module 1530 installed in the case 1510, and a connection terminal installed in the case 1510 and receiving power from an external power source. 1520).

The case 1510 may be formed of a material having good heat dissipation, for example, may be formed of a metal material or a resin material.

The light emitting module 1530 may include a board 1532 and a light emitting device package 200 according to an embodiment mounted on the board 1532. The plurality of light emitting device packages 200 may be arranged in a matrix form or spaced apart at predetermined intervals.

The board 1532 may be a circuit pattern printed on an insulator, and for example, a general printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, FR-4 substrates and the like.

In addition, the board 1532 may be formed of a material that reflects light efficiently, or a surface may be coated with a color such as white, silver, etc., in which the light is efficiently reflected.

At least one light emitting device package 200 may be mounted on the board 1532. Each of the light emitting device packages 200 may include at least one light emitting diode (LED) chip. The LED chip may include a light emitting diode in a visible light band such as red, green, blue, or white, or a UV light emitting diode emitting ultraviolet (UV) light.

The light emitting module 1530 may be arranged to have a combination of various light emitting device packages 200 to obtain color and luminance. For example, a white light emitting diode, a red light emitting diode, and a green light emitting diode may be combined to secure high color rendering (CRI).

The connection terminal 1520 may be electrically connected to the light emitting module 1530 to supply power. The connection terminal 1520 is inserted into and coupled to an external power source in a socket manner, but is not limited thereto. For example, the connection terminal 1520 may be formed in a pin shape and inserted into an external power source, or may be connected to the external power source by a wire.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

111: substrate 113: buffer layer
115: diffusion barrier layer 117: first gallium nitride based semiconductor layer
119: aluminum nitride-based semiconductor layer 120: second gallium nitride-based semiconductor layer

Claims (17)

A silicon substrate;
A buffer layer having an upper surface roughened on the silicon substrate;
A diffusion barrier layer on a portion of the roughness of the buffer layer; And
A nitride semiconductor device comprising a first gallium nitride-based semiconductor layer on the diffusion barrier layer. The nitride semiconductor device of claim 1, wherein the buffer layer comprises AlN. The nitride semiconductor device of claim 2, wherein the diffusion barrier layer is formed on a roughness formed on the buffer layer. The nitride semiconductor device of claim 1, wherein the diffusion barrier layer comprises amorphous nitride or oxide. The nitride semiconductor device of claim 4, wherein the diffusion barrier layer comprises SiN. The nitride semiconductor device of claim 5, wherein the buffer layer has a thickness in a range of 30 nm to 200 nm. The nitride semiconductor device of claim 4, wherein the diffusion barrier layer has a thickness thinner than that of the buffer layer. The nitride semiconductor device of claim 4, wherein the diffusion barrier layer is formed to be lower than an upper surface of the buffer layer in a recess of the roughness of the buffer layer. The nitride semiconductor device of claim 5, wherein the diffusion barrier layer has a thickness of 0.5 to 10 nm. The semiconductor device of claim 4, further comprising: an aluminum nitride-based semiconductor layer on the first gallium nitride-based semiconductor layer; And a second gallium nitride based semiconductor layer on the aluminum nitride based semiconductor layer. The nitride semiconductor device of claim 10, comprising a stacked structure of at least one compound semiconductor layer of an n-p junction, a p-n junction, a p-n-p junction, and an n-p-n junction on the second gallium nitride based semiconductor layer. Forming a buffer layer comprising a first layer of aluminum nitride on a silicon substrate;
Forming an amorphous diffusion barrier layer on the first aluminum nitride layer; And
Forming a first gallium nitride based semiconductor layer on the buffer layer and the diffusion barrier layer. The method of claim 12, wherein the diffusion barrier layer is formed of SiN on the roughness of the buffer layer. A silicon substrate;
A buffer layer including roughness on an upper surface of the silicon substrate; And
A growth substrate comprising a diffusion barrier layer on a portion of the roughness. 15. The method of claim 14,
The buffer layer is a growth substrate containing AlN. 16. The method of claim 15,
The roughness includes a convex portion and a concave portion,
The diffusion barrier layer is formed to fill the recess. 17. The method of claim 16,
The diffusion barrier layer is a growth substrate containing SiN.

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