KR20130009389A - Nonvolatile memory device and driving method thereof - Google Patents

Abstract

PURPOSE: A nonvolatile memory device and a driving method thereof are provided to reduce erase time by using sub message data instead of message data and a sub parity bit instead of a parity bit in an erase operation. CONSTITUTION: A first inverting unit receives message data and inverts the message data. An encoder(110) encodes the inverted message data and generates a bit error correctible parity bit. A second inverting unit receives a parity bit and inverts the parity bit. A write circuit(180) writes the message data and the inverted parity bit in a memory core.

Description

Nonvolatile memory device and driving method

The present invention relates to a nonvolatile memory device and a driving method thereof.

A nonvolatile memory device using a resistance material includes a phase change random access memory (PRAM), a phase change memory (PCM), a resistive memory (RRAM), and a magnetic memory device (MRAM). ) Etc. Dynamic RAM (DRAM) or flash memory devices store data using charge, while non-volatile memory devices using resistors are used to store phase change material states such as chalcogenide alloys (PRAM), resistance change of variable resistance (RRAM), and resistance change (MRAM) of MTJ (Magnetic Tunnel Junction) thin film according to magnetization state of ferromagnetic material.

Here, referring to the phase change memory device as an example, the phase change material is changed into a crystalline state or an amorphous state while being cooled after heating. Phase change materials in the crystalline state have low resistance, and phase change materials in the amorphous state have high resistance. Accordingly, the decision state may be defined as a set state and the amorphous state may be defined as a reset state.

In addition, as the memory capacity of a nonvolatile memory device increases, it is necessary to use an error correction circuit for correcting an error of a defective memory cell. The error correction circuit includes, for example, a method using a redundant memory cell, an Error Correction Code (ECC) method, and the like.

An object of the present invention is to provide a nonvolatile memory device employing an ECC type error correction method.

Another object of the present invention is to provide a method of driving the nonvolatile memory device.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the nonvolatile memory device of the present invention for solving the above problems is a first inverting unit for receiving and inverting the message data, an encoder for encoding the inverted message data, generating a bit error correction parity bit, the A second inverting unit receives and inverts a parity bit, and a write circuit for writing the message data and the inverted parity bit to a memory core.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems is a memory core for storing message data and inverted parity bits, a read circuit for reading message data and inverted parity bits from the memory core, the read circuit A third inverter that receives the message data from the third inverter, a fourth inverter that receives the inverted parity bits from the read circuit and inverts again to generate the parity bits, and provides inverted message data from the third inverter And a syndrome generator configured to receive a parity bit from the fourth inverter and generate a syndrome.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems is provided with an input buffer for receiving message data, the message data and a predetermined auxiliary message data, and in response to a selection signal, the message data and the A first selector for selectively outputting any one of the auxiliary message data, and a write circuit for writing the message data or auxiliary message data output from the first selector to the memory core.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems includes a plurality of phase change memory cells, wherein the set state of the phase change memory cell corresponds to the first logic data, the reset state is the second A memory core corresponding to logic data, and a write circuit for writing a codeword to the memory core, wherein the group of codewords includes a vector in which all components are first logic data, and all components are second logic data. Phosphorus vector is not included.

One aspect of a method of driving a nonvolatile memory device of the present invention for solving the above other problem is to receive and invert the message data, to encode the inverted message data, to generate a bit error correctable parity bit, the parity Receiving and inverting bits, and writing the message data and the inverted parity bits to a memory core.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a nonvolatile memory device in accordance with a first embodiment of the present invention.
FIG. 2 is a diagram for describing an exemplary phase change memory cell in the memory core illustrated in FIG. 1.
3 is a block diagram illustrating a nonvolatile memory device in accordance with a second embodiment of the present invention.
4 is a block diagram illustrating a nonvolatile memory device in accordance with a third embodiment of the present invention.
5 is a block diagram illustrating a nonvolatile memory device in accordance with a fourth embodiment of the present invention.
6 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.
7 is a block diagram illustrating an application example of the memory system of FIG. 6.
FIG. 8 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 7.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described using a phase change random access memory (PRAM) or a phase change memory (PCM). However, it will be apparent to those skilled in the art that the present invention can be applied to both a nonvolatile memory device using a resistor, such as a resistive memory device (RRAM) and a ferroelectric RAM (FRAM).

1 is a block diagram illustrating a nonvolatile memory device in accordance with a first embodiment of the present invention. FIG. 2 is a diagram for describing an exemplary phase change memory cell in the memory core illustrated in FIG. 1.

Referring to FIG. 1, a nonvolatile memory device 1 according to an exemplary embodiment of the present invention may include an input buffer 105, a first inverter 106, an encoder 110, a second inverter 108, The write circuit 180, the memory core 190, the read circuit 210, the third inverter 216, the fourth inverter 218, the decoder 220, the output buffer 250, and the like are included. The decoder 220 may include a syndrome generator 222, an error position detector 224, an error corrector 226, and the like. Through such a configuration, the nonvolatile memory device 1 according to the first embodiment of the present invention can perform an error correction operation using ECC.

The memory core 190 may include a plurality of phase change memory cells (see MC of FIG. 2). As illustrated, the phase change memory cell MC may include a variable resistance element RC and an access element AC. The variable resistance element RC may include a phase change material. For example, the phase change material may be formed of GaSb, InSb, InSe. Sb2Te3, GeTe, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe, which combines three elements, AgInSbTe, which combines four elements, (GeSn) SbTe, GeSb (SeTe), Te81Ge15Sb2S2, etc. can be used. Of these, GeSbTe composed of germanium (Ge), antimony (Sb) and tellurium (Te) can be mainly used. In addition, the access element AC controls the current flowing through the variable resistance element RC. The access element AC may be a diode, a transistor, or the like coupled in series with the variable resistance element RC. In the figure, a diode is shown as a variable resistance element RC. On the other hand, the phase change material may have a crystalline state or an amorphous state. Here, the determination state may be defined as a set state, and the amorphous state may be defined as a reset state. In addition, the set state corresponds to the first logic data (eg, logic 1), and the reset state corresponds to the second logic data (eg, logic 0).

The input buffer 105 is provided with message data M_DATA.

The first inverting unit 106 inverts the message data M_DATA and outputs the inverted message data / M_DATA.

The encoder 110 receives the inverted message data / M_DATA and generates a parity bit (ECCP) capable of bit error correction. The encoder 110 may generate, for example, a parity bit (ECCP) capable of correcting an error of 1 bit, but is not limited thereto. The encoder 110 may be made using an XOR gate.

The second inverting unit 108 inverts the parity bit ECCP and outputs the inverted parity bit / ECCP.

The write circuit 180 writes the message data M_DATA and the inverted parity bits / ECCP to the memory core 190. Meanwhile, the codeword CW refers to a vector stored in the memory core 190 by the write circuit 180 in relation to the ECC operation. In Fig. 1, the codeword CW becomes " message data M_DATA + inverted parity bits / ECCP. &Quot; In addition, a codeword group means a set of all vectors that a codeword CW may have.

The read circuit 210 reads the parity bit (/ ECCP) inverted from the message data M_DATA stored in the memory core 190.

The third inverting unit 216 receives the message data M_DATA from the read circuit 210 and inverts it. That is, the third inverting unit 216 outputs inverted message data / M_DATA.

The fourth inverting unit 218 receives the inverted parity bit / ECCP from the read circuit 210 and inverts again to generate the parity bit ECCP.

The syndrome generator 222 receives and decodes the message data (/ M_DATA) inverted from the third inverter 216 and a parity bit (ECCP) from the fourth inverter 218. Through this process, syndrome (SDR) is generated.

The error location detector 224 uses the syndrome SDR to determine the error location of the message data M_DATA. For example, the error location detector 224 may use two or more syndromes (SDRs) to calculate the coefficients of the error location equation, and detect the error location based on the coefficients.

The error corrector 226 corrects an error of the message data M_DATA based on the detected error position. The corrected message data is called CORRECTED_DATA.

The output buffer 250 outputs the corrected message data CORRECTED_DATA to the outside.

Meanwhile, in the nonvolatile memory device according to the first embodiment of the present invention, the first inversion unit 106 and the second inversion unit 108 are disposed at the front and rear ends of the encoder 110, respectively. Accordingly, the encoder 110 encodes the inverted message data / M_DATA to generate a parity bit ECCP, and the inverted parity bit / ECCP is stored in the memory core 190. Using this method, the codeword CW can be made into a vector in which all components are the first logic data (logic 1). In particular, even in a nonvolatile memory device employing ECC, the codeword CW can be made a " vector in which all components are first logic data (logic 1) ".

It will be described in detail with reference to Table 1 below. As described above, the encoder 110 may be made using an XOR gate.

As in CASE1, if the message data M_DATA is a vector (1,1,1 ..., 1) with all components 1, that is, the inverted message data (/ M_DATA) is a vector (0, with all components zero) In the case of 0, 0..., 0), the encoder 110 may output the vectors 0,. Thus, the inverted parity bits / ECCP become vectors (1, 1, 1 ..., 1) in which all components are one. The codeword of CASE1 becomes a vector (1, 1, 1, ..., 1, 1, 1) in which all components are one.

On the other hand, as in CASE2, if the message data M_DATA is a vector (0,0,0 ..., 0) with all components 0, that is, the inverted message data (/ M_DATA) is a vector with all components 1 ( In the case of 1, 1, 1, ..., 1, the encoder 110 does not output a vector (1, ..., 1) in which all components are one. The encoder 110 may output a predetermined vector (eg, (1, 0,..., 1)). Therefore, the codeword of CASE2 does not become a vector (0, 0, 0, ..., 0, 0, 0) in which all components are zero.

M_DATA / M_DATA ECCP / ECCP Codeword
"M_DATA + / ECCP" CASE 1 (1,1,1…, 1) (0,0,0…, 0) (0,…, 0) (1,…, 1) (1,1,1,…, 1,1,1) CASE 2 (0,0,0…, 0) (1,1,1…, 1) Preset
vector Inverted
Preset vector

As a result, in the nonvolatile memory device 1 according to the first embodiment of the present invention, the codeword group includes the vectors (1, 1, 1,..., 1, ...) in which all components are first logic data (logic 1). 1,1, but does not include vectors (0,0,0,..., 0,0,0) in which all components are second logic data (logic 0). When the codeword group is C, it is expressed as Equation (1).

In the nonvolatile memory device according to the first embodiment of the present invention, since the codeword CW can be made into a vector in which all components are the first logic data (logic 1), the memory core 190 is erased from the memory core 190. The first logic data (logic 1) can be written in the entire area.

In addition, heat is applied to the nonvolatile memory device when the nonvolatile memory device (particularly, the memory chip or package) is bonded to the circuit board. After bonding, all phase change memory cells in the nonvolatile memory device may be in a set state. Typically, no heat is applied so high that the phase change memory cell is in a reset state upon bonding. As described above, when the set state of the phase change memory cell corresponds to the first logic data (logic 1), the first logic data is written to all the phase change memory cells after bonding. That is, all phase change memory cells after bonding may be in an erased state.

In some cases, manufacturers may need to program specific data directly into a nonvolatile memory device. In this case, data program time can have a significant impact on throughput. In particular, a memory device that needs to perform an erase operation before a program operation requires more "erase operation time" when programming specific data. However, as described above, when all the phase change memory cells after bonding are in an erased state, a separate erase operation time is unnecessary, so that the program can be advanced quickly.

3 is a block diagram illustrating a nonvolatile memory device in accordance with a second embodiment of the present invention. The following description focuses on differences from the nonvolatile memory device according to the first embodiment of the present invention.

Referring to FIG. 3, in the nonvolatile memory device 2 according to the second embodiment of the present invention, in an erase operation, the write circuit 180 may store preset auxiliary message data instead of the message data M_DATA in the memory core ( Light at 190). Here, the erase operation may include a normal erase operation and an inverse erase operation. Inverting erase is similar to the invert write operation, when the erase command is input, writing the second logic data (logic 0), not the first logic data (logic 1). Inverting write operation, if the first logic data (logic 1) / second logic data (logic 0) is input from the outside, on the contrary, the second logic data (logic 0) / first logic data (logic) to the memory core 190 It means to light 1).

In detail, the first selector 196 selects one of preset auxiliary message data instead of the message data M_DATA in response to the selection signal SEL_MODE. The first selector 196 communicates the selection to the write circuit 180. Here, the selection signal SEL_MODE is a signal for selecting one of the write PGM, the normal erase ERS, and the invert erase (inv. ERS). The auxiliary message data used in the normal erase (ERS) is a vector (1, 1, 1, ..., 1, 1, 1) in which all components are first logic data (logic 1), and inverse erase (inv.ERS). The auxiliary message data to be used for the vector) is a vector (0, 0, 0, ..., 0, 0, 0) in which all components are second logic data (logic 0).

In addition, during the erase operation, the write circuit 180 writes the auxiliary parity bit to the memory core 190 by applying a value corresponding to a preset encoder output without passing through the encoder 110.

In detail, the second selector 198 selects one of the preset auxiliary parity bits instead of the inverted parity bits / ECCP in response to the selection signal SEL_MODE. The second selector 198 communicates the selection to the write circuit 180. The auxiliary message data used in the normal erase (ERS) is a vector (1, 1, 1, ..., 1, 1, 1) in which all components are first logic data (logic 1), and inverse erase (inv.ERS). The auxiliary parity bit used in the case may be a predetermined vector (FCODE). In this case, all components of the preset vector FCODE may not be the second logic data (logic 0). As described with reference to FIG. 1, a codeword group includes vectors (1, 1, 1, ..., 1, 1, 1) in which all components are first logic data (logic 1), but all components are first. This is because the vector (0, 0, 0, ..., 0, 0, 0) that is the two logic data (logic 0) is not included.

In the erase operation, when the auxiliary message data is used instead of the message data M_DATA and the auxiliary parity bits are used instead of the inverted parity bits ECCP, the erase time can be shortened. In particular, since the auxiliary parity bits have not been read, combined with message data, and encoded, the erase time can be further shortened.

4 is a block diagram illustrating a nonvolatile memory device in accordance with a third embodiment of the present invention. The following description focuses on differences from the nonvolatile memory device according to the second embodiment of the present invention. Referring to Fig. 4, the nonvolatile memory device 3 according to the third embodiment of the present invention adopts only a normal erase operation and does not adopt an inverted erase operation. Therefore, the selection signal SEL_MODE is a signal for selecting one of the write PGM and the normal erase ERS.

5 is a block diagram illustrating a nonvolatile memory device in accordance with a fourth embodiment of the present invention. The following description focuses on differences from the nonvolatile memory device according to the first embodiment of the present invention.

Referring to FIG. 5, in the nonvolatile memory device 1 according to the first embodiment of the present invention, a set state of a phase change memory cell MC corresponds to first logic data (eg, logic 1). The reset state corresponds to second logic data (eg, logic 0).

On the other hand, in the nonvolatile memory device 4 according to the fourth embodiment of the present invention, the set state of the phase change memory cell MC corresponds to the second logic data (eg, logic 0), and the reset state is Corresponds to the first logic data (eg, logic 1).

Therefore, in the nonvolatile memory device 4 according to the fourth embodiment of the present invention, the codeword group is a vector (0, 0, 0, ..., 0, 0 in which all components are second logic data (logic 0). , 0), but does not include vectors (1, 1, 1, ..., 1, 1, 1) in which all components are first logic data (logic 1). When the codeword group is C, it is expressed as Equation (2).

In an erase operation, the write circuit 180 writes preset auxiliary message data to the memory core 190 instead of the message data M_DATA.

In detail, the first selector 196 selects one of preset auxiliary message data instead of the message data M_DATA in response to the selection signal SEL_MODE. The first selector 196 communicates the selection to the write circuit 180. The auxiliary message data used in the normal erase (ERS) is a vector (1, 1, 1, ..., 1, 1, 1) in which all components are first logic data (logic 1), and inverse erase (inv.ERS). The auxiliary message data to be used for the vector) is a vector (0, 0, 0, ..., 0, 0, 0) in which all components are second logic data (logic 0).

In addition, during the erase operation, the write circuit 180 writes the auxiliary parity bit to the memory core 190 by applying a value corresponding to a preset encoder output without passing through the encoder 110.

In detail, the second selector 198 selects one of the preset auxiliary parity bits instead of the parity bits ECCP in response to the selection signal SEL_MODE. The second selector 198 communicates the selection to the write circuit 180. The auxiliary message data used in the normal erase (ERS) may be a preset vector (FCODE). In this case, all components of the preset vector FCODE are not the first logic data (logic 1). Further, the auxiliary parity bits used in inversion erase (inv. ERS) are vectors (0, 0, 0, ..., 0, 0, 0) in which all components are second logic data (logic 0). As mentioned above, a codeword group includes a vector (0,0,0,..., 0,0,0) in which all components are second logic data (logic 0), but all components are first logic data ( This is because the vector 1, 1, 1, ..., 1, 1, 1, which is a logic 1), is not included.

In the erase operation, when the auxiliary message data is used instead of the message data M_DATA and the auxiliary parity bit is used instead of the parity bit ECCP, the erase time can be shortened. In particular, since the auxiliary parity bits have not been read, combined with message data, and encoded, the erase time can be further shortened.

As described above, after bonding a nonvolatile memory device (especially a memory chip or package) to a circuit board, all phase change memory cells in the nonvolatile memory device may be in a set state. In the nonvolatile memory device 4 according to the fourth embodiment of the present invention, the set state of the phase change memory cell MC corresponds to second logic data (eg, logic 0). Therefore, all phase change memory cells MC after bonding may be regarded as inverse erased. That is, all the phase change memory cells MC after bonding do not need to be inverse erased before inverted writing.

6 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.

Referring to FIG. 6, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

The nonvolatile memory device 1100 may be configured and operate in the same manner as described with reference to FIGS. 1 to 5.

The controller 1200 is connected to a host and the nonvolatile memory device 1100. In response to a request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the nonvolatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1100.

In exemplary embodiments, the controller 1200 may further include well-known components, such as random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operating memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls the overall operation of the controller 1200.

The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-express) protocol, an advanced technology attachment (ATA) protocol, External (host) through at least one of a variety of interface protocols, such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol. Are configured to communicate with each other. The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be configured to additionally include an error correction block. The error correction block is configured to detect and correct an error of data read from the nonvolatile memory device 1100 using an error correction code (ECC). By way of example, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device such that a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, Memory cards such as SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS) and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive SSD, an operation speed of a host connected to the memory system 1000 is significantly improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

In exemplary embodiments, the nonvolatile memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), and plastic dual in. Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer -Can be packaged and implemented in the same way as Level Processed Stack Package (WSP).

7 is a block diagram illustrating an application example of the memory system of FIG. 6.

Referring to FIG. 7, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of non-volatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. For example, the plurality of nonvolatile memory chips are shown to communicate with the controller 2200 through the first through kth channels CH1 through CHk.

Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS. 1 to 5.

In FIG. 7, a plurality of nonvolatile memory chips are connected to one channel. However, it will be understood that the memory system 2000 can be modified such that one non-volatile memory chip is connected to one channel.

FIG. 8 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 7.

Referring to FIG. 8, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, and a memory system 2000. .

The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power source 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 8, the nonvolatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the nonvolatile memory device 2100 may be configured to be directly connected to the system bus 3500.

In FIG. 8, the memory system 2000 described with reference to FIG. 7 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 6. In exemplary embodiments, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 6 and 7.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1 to 4: nonvolatile memory device 106: first inverting unit
108: second inversion unit 110: encoder
180: write circuit 190: memory core
196: first selector 198: second selector
210: lead circuit 216: third inverting portion
218: fourth inverting unit 220: decoder

Claims (10)

A first inverting unit receiving and inverting message data;
An encoder for encoding the inverted message data to produce a bit error correctable parity bit;
A second inversion unit receiving and inverting the parity bit; And
And a write circuit for writing the message data and the inverted parity bits to a memory core. The method of claim 1,
The memory core includes a plurality of phase change memory cells, wherein a set state of the phase change memory cell corresponds to first logic data, and a reset state of the phase change memory cell corresponds to second logic data. Device. The method of claim 2,
When the message data written to the memory core and the inverted parity bits are referred to as codewords,
The group of codewords includes a vector in which all components are first logic data, and a vector in which all components are second logic data. The method of claim 2,
The erase circuit writes an auxiliary parity bit to a memory core by applying a value corresponding to a preset encoder output without passing through the encoder during an erase operation. 5. The method of claim 4,
In the erase operation, the write circuit writes predetermined auxiliary message data to the message core instead of the message data. The method of claim 1,
A read circuit for reading the message data stored in the memory core and the inverted parity bits;
A third inverting unit receiving and inverting the message data from the read circuit;
A fourth inverting unit which receives the inverted parity bit from the read circuit and inverts again to generate the parity bit;
And a syndrome generator configured to receive the inverted message data from the third inverter and receive a parity bit from the fourth inverter to generate a syndrome. A memory core for storing message data and inverted parity bits;
A read circuit for reading message data and inverted parity bits from the memory core;
A third inverting unit receiving and inverting the message data from the read circuit;
A fourth inversion unit which receives the inverted parity bits from the read circuit and inverts them again to generate parity bits; And
And a syndrome generator configured to receive inverted message data from the third inverter and receive parity bits from the fourth inverter to generate a syndrome. An input buffer for receiving message data;
A first selector receiving the message data and predetermined auxiliary message data and selectively outputting any one of the message data and the auxiliary message data in response to a selection signal; And
And a write circuit configured to write message data or auxiliary message data output from the first selector to a memory core. A memory core including a plurality of phase change memory cells, wherein the set state of the phase change memory cell corresponds to first logic data and the reset state corresponds to second logic data; And
A write circuit for writing a codeword to the memory core,
The group of codewords includes a vector in which all components are first logic data and does not include a vector in which all components are second logic data. Receive and invert the message data,
Encoding the inverted message data to generate a bit error correctable parity bit,
Receive and invert the parity bit,
And writing the message data and the inverted parity bits to a memory core.

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