KR20130005499A - Nonvolatile memory device and driving method thereof - Google Patents

Nonvolatile memory device and driving method thereof Download PDF

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Publication number
KR20130005499A
KR20130005499A KR1020110066934A KR20110066934A KR20130005499A KR 20130005499 A KR20130005499 A KR 20130005499A KR 1020110066934 A KR1020110066934 A KR 1020110066934A KR 20110066934 A KR20110066934 A KR 20110066934A KR 20130005499 A KR20130005499 A KR 20130005499A
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South Korea
Prior art keywords
data
write data
inversion
flag
inversion flag
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KR1020110066934A
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Korean (ko)
Inventor
전성현
정회주
김서희
김성훈
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삼성전자주식회사
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Priority to KR1020110066934A priority Critical patent/KR20130005499A/en
Priority to US13/532,911 priority patent/US8848465B2/en
Publication of KR20130005499A publication Critical patent/KR20130005499A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: A nonvolatile memory device and a driving method thereof are provided to improve an endurance property of the nonvolatile memory cell by minimizing a write operation. CONSTITUTION: A first encoder matches a first write data(WR_DATA1) with read data(RD_DATA). The first encoder generates a second write data(WR_DATA2) by inverting or non-inverting the first write data according to a matching result and generates a first inversion flag(DCWF1) which shows the inversion of the first write data. A second encoder generates a first parity bit by the ECC coding of the first inversion flag and the second write data.

Description

Nonvolatile memory device and driving method

The present invention relates to a nonvolatile memory device and a driving method thereof.

As the memory capacity of a nonvolatile memory device increases, it is necessary to use an error correction circuit for correcting an error of a defective memory cell. The error correction circuit includes, for example, a method using a redundant memory cell, a method using an Error Correction Code (ECC), and the like.

Meanwhile, a nonvolatile memory device using a resistance material may include a phase change random access memory (PRAM), a phase change memory (PCM), a resistive memory (RRAM), and a magnetic memory device (MRAM). : Magnetic RAM). Dynamic RAM (DRAM) or flash memory devices store data using charge, while non-volatile memory devices using resistors are used to store phase change material states such as chalcogenide alloys (PRAM), resistance change of variable resistance (RRAM), and resistance change (MRAM) of MTJ (Magnetic Tunnel Junction) thin film according to magnetization state of ferromagnetic material.

Here, when the phase change memory device is described as an example, the phase change material is changed to a crystalline state or an amorphous state while being heated and cooled, and the phase change material in the crystalline state has a low resistance and the phase change material in the amorphous state has a high resistance. . Therefore, the determination state may be defined as set data and the amorphous state may be defined as reset data.

However, the write operation of the phase change memory device is very slow compared to the read operation. Therefore, in order to speed up the operation of the phase change memory device and to improve the endurance characteristic, it is necessary to reduce the number of physical write operations.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having a faster operation and an improved endurance characteristic.

Another object of the present invention is to provide a method of driving a nonvolatile memory device, which speeds up operation and improves endurance characteristics.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An aspect of a nonvolatile memory device of the present invention for solving the above problems is to match the first write data and the read data, and invert or non-invert the first write data according to the matching result to the second write. A first encoder for generating data and generating a first inversion flag indicating whether the first write data is inverted, and ECC coding the second write data and the first inversion flag to generate a first parity bit And a second encoder.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems includes a memory core including a plurality of nonvolatile memory cells, and a program circuit for programming codewords to the plurality of nonvolatile memory cells. The codeword may include: a first parity bit generated by ECC encoding the second write data, the first inversion flag indicating the inversion information associated with the second write data, and the second write data and the first inversion flag. It includes.

One aspect of a method of driving a nonvolatile memory device of the present invention for solving the other problem is to match the first write data and the read data, to generate a first inversion flag to determine whether to inversion (inversion), According to a first inversion flag, inverting or non-inverting the first write data to generate second write data, and ECC coding the second write data and the first inverted flag to generate a first parity bit. And storing the second write data, the first inversion flag, and the first parity bit in a memory core.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention. In FIG. 1, the write operation of the nonvolatile memory device will be described.
FIG. 2 is a conceptual diagram for describing an operation of the first encoder illustrated in FIG. 1.
FIG. 3 is a diagram for describing a codeword illustrated in FIG. 1.
FIG. 4 is a diagram for describing an exemplary nonvolatile memory cell in the memory core shown in FIG. 1.
FIG. 5 is a circuit diagram for describing the first encoder illustrated in FIG. 1.
FIG. 6 is a circuit diagram for describing the second encoder illustrated in FIG. 1.
7 is a block diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention. In FIG. 7, the read operation of the nonvolatile memory device will be described.
FIG. 8 is a block diagram illustrating the decoder shown in FIG. 7.
9 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.
FIG. 10 is a block diagram illustrating an application example of the memory system of FIG. 9.
FIG. 11 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 10.

Advantages and features of the present invention, and methods of achieving the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described using a phase change random access memory (PRAM) or a phase change memory (PCM). However, it will be apparent to those skilled in the art that the present invention can be applied to both a nonvolatile memory device using a resistor, such as a resistive memory device (RRAM) and a ferroelectric RAM (FRAM).

1 is a block diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention. In FIG. 1, the write operation of the nonvolatile memory device will be described. FIG. 2 is a conceptual diagram for describing an operation of the first encoder illustrated in FIG. 1. FIG. 3 is a diagram for describing the codeword CW shown in FIG. 1. FIG. 4 is a diagram for describing an exemplary nonvolatile memory cell in the memory core shown in FIG. 1.

First, referring to FIG. 1, a nonvolatile memory device 1 according to some embodiments of the present invention may include a first encoder 110, a second encoder 120, a write circuit 180, a memory core 190, and the like. It may include. Through such a configuration, the nonvolatile memory device 1 according to some embodiments of the present invention may perform a data comparative write with inversion flag (DCWIF) operation and an error correction operation using ECC.

In detail, the nonvolatile memory device 1 according to an exemplary embodiment of the present invention compares the first write data WR_DATA1 and the read data RD_DATA, and compares the first write data WR_DATA1 and the first write data WR_DATA1. The number of writes among the inverted data of the C1) is written to the memory core 190. This operation is called DCWIF (Data Comparative Write with Inversion Flag). In addition, in order to increase DCWIF operation reliability, an error correction operation using ECC is performed.

The first encoder 110 receives first write data WR_DATA1 and read data RD_DATA. Subsequently, the first write data WR_DATA1 and the read data RD_DATA are matched to generate the first inversion flag DCWIF1 and the second write data WR_DATA2 according to the matching result.

The read data RD_DATA may be data generated through the read process of FIGS. 7 and 8 to be described later. The read data RD_DATA may be data stored at an address to which the first write data WR_DATA1 is to be written.

For example, it is assumed that the first write data WR_DATA1 is "010 ... 000" and the read data RD_DATA is "000 ... 111", as shown in FIG. It is assumed that the first write data WR_DATA1 and the read data RD_DATA are each A bits, where A is a natural number of two or more.

The first write data WR_DATA1 and the read data RD_DATA may be matched with each other bit by bit. As illustrated, the number of bits matched with each other of the first write data WR_DATA1 and the read data RD_DATA may be B.

If the number of bits B matched with each other is larger than the predetermined reference C, the second write data WR_DATA2 output by the first encoder 110 may be non-inversiond data. That is, the second write data WR_DATA2 may be the same as the first write data WR_DATA1. In addition, since the first inversion flag DCWIF1 indicates whether the first write data WR_DATA1 is inverted, the first inversion flag DCWIF1 may be "0" indicating a non-inversion state.

When the number of bits B matched with each other is smaller than the predetermined reference C, the second write data WR_DATA2 output by the first encoder 110 may be inverted data. In addition, the first inversion flag DCWIF1 may be "1" indicating an inversion state.

In addition, when the number of bits B matched with each other and the predetermined reference C are the same, the second write data WR_DATA2 may be in a non-inverted state or in an inverted state. That is, in the same case, it may be determined as necessary or appropriate to the performance of the nonvolatile memory device.

Meanwhile, the reference C may be, for example, half of the number of bits A of the first write data WR_DATA1, but is not limited thereto. The reference C may be determined to an appropriate value through simulation or the like. In addition, the reference C may be a value predetermined by the manufacturer at the time of manufacture of the nonvolatile memory device, or may be a value determined by the user through setting as necessary.

As a result, when the number of bits B matched with each other is larger than the predetermined reference C (when the first write data WR_DATA1 and the read data RD_DATA are similar), the first write data WR_DATA1 remains in memory. Stored in core 190. When the number of bits B matched with each other is smaller than the predetermined reference C (when the inversion data of the first write data WR_DATA1 is similar to the read data RD_DATA), the inversion data of the first write data WR_DATA1 is used. Is stored in the memory core 190.

For convenience of description, the case where the first inversion flag DCWIF1 is 1 bit is exemplified, but the present invention is not limited thereto.

Referring back to FIG. 1, the second encoder 120 receives the second write data WR_DATA2 and the first inversion flag DCWIF1. Next, the second write data WR_DATA2 and the first inversion flag DCWIF1 are coded to generate a first parity bit ECCP. Here, the method coded by the second encoder 120 may be various, and is not limited to a specific method.

The first inversion flag DCWIF1 indicates whether the first write data WR_DATA1 is inverted. That is, the first inversion flag DCWF1 indicates inversion information related to the second write data WR_DATA2. The first inversion flag DCWF1 indicates whether the second write data WR_DATA2 is generated by inverting the first write data WR_DATA1. Therefore, when an error occurs in the first inversion flag DCWIF1, the second write data WR_DATA2 may not be trusted. Therefore, in the nonvolatile memory device according to some embodiments of the present invention, not only the second write data WR_DATA2 but also the first inversion flag DCWIF1 code error correcting code (ECC).

The first inversion flag DCWIF1, the second write data WR_DATA2, and the first parity bit ECCP1 generated in the same manner as described above are transferred to the write circuit 180. The write circuit 180 writes the first inversion flag DCWIF1, the second write data WR_DATA2, and the first parity bit ECCP1 to the memory core 190.

The first inversion flag DCWIF1 + second write data WR_DATA2 + first parity bit ECCP1 may be referred to as a "codeword" CW. Referring to FIG. 3, an exemplary code word CW will be described.

In detail, one bit may be allocated to the first inversion flag DCWIF1 for every 64 bits of the second write data WR_DATA2. The 1-bit first inversion flag DCWIF1 indicates that the 64-bit second write data WR_DATA2 is inverted. For example, whether WR_DATA2 [63: 0] is generated by inverting can be known through DCWP [0].

In addition, it is assumed that the first parity bit ECCP1 may correct an error of one bit of the second write data WR_DATA2 and the first inversion flag DCWIF1. Then, since the total number of bits of the second write data WR_DATA2 and the first inversion flag DCWIF1 is (64 + 1) * 4 = 260 and 2 8 <260 <2 9 , the first parity bit ECCP is 9. May be a bit.

The memory core 190 may include a plurality of nonvolatile memory cells (see MC of FIG. 4). The nonvolatile memory cell MC may write or read data using a resistor. The nonvolatile memory cell MC includes a variable resistance element RC having a phase change material whose resistance varies according to data stored therein, and an access element AC for controlling a current flowing through the variable resistance element RC. can do. The access element AC may be a diode, a transistor, or the like coupled in series with the variable resistance element RC. In the figure, a diode is shown as a variable resistance element RC. In addition, the phase change material is GaSb, InSb, InSe. Sb2Te3, GeTe, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe, which combines three elements, AgInSbTe, which combines four elements, (GeSn) SbTe, GeSb (SeTe), Te81Ge15Sb2S2, etc. can be used. Of these, GeSbTe composed of germanium (Ge), antimony (Sb) and tellurium (Te) can be mainly used.

On the other hand, the write operation of the nonvolatile memory cell MC is very slow compared to the read operation. In addition, since the write operation is performed using a high level of write current, the more the write operation is performed, the lower the endurance characteristic of the nonvolatile memory cell MC becomes.

However, as in the nonvolatile memory device 1 according to the exemplary embodiment of the present disclosure, when the data comparative write with inversion flag (DCWIF) operation is performed, the write operation may be minimized, and thus the nonvolatile memory cell MC may be used. The endurance characteristic of can be improved. In addition, since both the second write data WR_DATA2 and the first inverted flag DCWIF1 are ECC coded, stability of the DCWIF operation can be improved.

Hereinafter, the first encoder 110 and the second encoder 120 will be described in detail with reference to FIGS. 5 and 6. FIG. 5 is a circuit diagram for describing the first encoder illustrated in FIG. 1. FIG. 6 is a circuit diagram for describing the second encoder illustrated in FIG. 1.

Referring to FIG. 5, the first encoder 110 may include a first XOR gate 111, a second XOR gate 112, a first counter 114, a second counter 115, a flag generator 116, and a selector. (119) and the like.

The first XOR gate 111 receives the first write data WR_DATA1 and the read data RD_DATA, and outputs logic "0" whenever the first write data WR_DATA1 and the read data RD_DATA match each other. The inverter 111a inverts this and outputs a logic "1". The first counter 114 counts the number of logic "1s". That is, the first counter 114 counts the number of bits matched with each other of the first write data WR_DATA1 and the read data RD_DATA.

In addition, the second XOR gate 112 is provided with inverted data and read data RD_DATA of the first write data WR_DATA1, and the inverted data and read data RD_DATA of the first write data WR_DATA1 are matched with each other. Each time a logic "0" is output, the inverter 112a inverts it and outputs a logic "1". The second counter 115 counts the number of logic "1s". That is, the second counter 115 counts the number of bits matched with the inverted data of the first write data WR_DATA1 and the read data RD_DATA.

The flag generator 116 generates the first inverted flag DCWIF1 by comparing the number counted in the first counter 114 with the number counted in the second counter 115. For example, the flag generator 116 may be a subtracter. The subtractor may obtain the difference between the number counted at the first counter 114 and the count counted at the second counter 115, and generate the first inverted flag DCWIF1 according to the result. That is, when the number counted in the first counter 114 is greater than the number counted in the second counter, the first inverted flag DCWIF1 indicating non-inversion is generated. If the number counted in the second counter 115 is greater than the number counted in the first counter, a first inversion flag DCWIF1 indicating inversion is generated.

In addition, the selector 119 outputs the first write data WR_DATA1 as the second write data WR_DATA2 as it is, or inverts the first write data WR_DATA1 according to the first inversion flag DCWIF1. The data can be output as WR_DATA2.

In FIG. 5, it is illustrated that the first write data WR_DATA1 is output as it is or inverted according to the first inversion flag DCWIF1, but the present invention is not limited thereto.

Referring to FIG. 6, the second encoder 120 may implement, for example, a generator polynomial. The second encoder 120 may include a plurality of XOR gates 121 to 129. Each of the XOR gates 121 to 129 may receive some selected from among the second write data WR_DATA2 and the first inversion flag DCWIF1. The circuit diagram of the second encoder 120 shown in FIG. 6 is merely exemplary, and is not limited thereto.

The operations of the nonvolatile memory device 1 according to some embodiments of the present invention described with reference to FIGS. 1 to 6 are summarized as follows. By matching the first write data WR_DATA1 and the read data RD_DATA, a first inversion flag DCWIF1 for determining whether to inversion is generated and the first write data DCWIF1 is generated according to the first inversion flag DCWIF1. Inverting or non-inverting WR_DATA1 to generate second write data WR_DATA2, ECC coding the second write data WR_DATA2 and the first inversion flag DCWIF1 to generate a first parity bit ECCP1, The second write data WR_DATA2, the first inversion flag DCWIF1, and the first parity bit ECCP1 are stored in the memory core 190.

7 is a block diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention. In FIG. 7, the read operation of the nonvolatile memory device will be described. FIG. 8 is a block diagram illustrating the decoder shown in FIG. 7.

First, referring to FIG. 7, the nonvolatile memory device 1 according to some embodiments of the present invention may include a read circuit 210, a decoder 220, a data generator 230, and the like. Through such a configuration, the nonvolatile memory device 1 according to some embodiments of the present invention may read data written through a DCWIF operation and an error correction operation using ECC.

The memory core 190 stores the core data CORE_DATA, the second inversion flag DCWIF2, and the second parity bit ECCP2. Here, each of the core data CORE_DATA, the second inversion flag DCWIF2, and the second parity bit ECCP2 may be stored in the manner disclosed in FIGS. 1 to 6.

The decoder 220 detects and corrects an error of the core data CORE_DATA and the second inversion flag DCWIF2 by using the second parity bit ECCP2.

Here, referring to FIG. 8, the decoder 220 may include a syndrome generator 222, an error position detector 224, an error corrector 226, and the like.

The syndrome generator 222 generates a syndrome SDR using the second parity bit ECCP2. The error position detector 224 detects an error position of the core data CORE_DATA or the second inversion flag DCWIF2 using the syndrome SDR. For example, the error location detector 224 may use two or more syndromes (SDRs) to calculate the coefficients of the error location equation, and detect the error location based on the coefficients. The error corrector 226 corrects an error of the core data CORE_DATA or the second inversion flag DCWIF2 based on the detected error position. The corrected core data is called CORRECTED_DATA and the corrected second inversion flag is called CORRECTED_IF2.

Referring back to FIG. 7, the data generator 230 inverts or non-inverts the corrected core data CORRECTED_DATA according to the corrected second inversion flag CORRECTED_IF2 and outputs the read data RD_DATA. That is, when the corrected second inversion flag CORRECTED_IF2 means inversion, the corrected core data is output as read data RD_DATA. On the contrary, if the corrected second inversion flag CORRECTED_IF2 means non-inversion, the corrected core data is inverted and output as read data RD_DATA.

In summary, if inverted data is stored in the write operation, the inverted data is output again in the read operation. In addition, if data that is not inverted during the write operation is stored, the output is performed without inversion during the read operation.

9 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.

Referring to FIG. 9, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

The nonvolatile memory device 1100 may be configured and operate in the same manner as described with reference to FIGS. 1 to 8.

The controller 1200 is connected to a host and the nonvolatile memory device 1100. In response to a request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the nonvolatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1100.

In exemplary embodiments, the controller 1200 may further include well-known components, such as random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operating memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls the overall operation of the controller 1200.

The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 may include a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-express) protocol, an advanced technology attachment (ATA) protocol, External (host) through at least one of a variety of interface protocols, such as Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and Integrated Drive Electronics (IDE) protocol. Are configured to communicate with each other. The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be configured to additionally include an error correction block. The error correction block is configured to detect and correct an error of data read from the nonvolatile memory device 1100 using an error correction code (ECC). By way of example, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device such that a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, Memory cards such as SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), universal flash storage (UFS) and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to configure a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive SSD, an operation speed of a host connected to the memory system 1000 is significantly improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

In exemplary embodiments, the nonvolatile memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), and plastic dual in. Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer -Can be packaged and implemented in the same way as Level Processed Stack Package (WSP).

FIG. 10 is a block diagram illustrating an application example of the memory system of FIG. 9.

Referring to FIG. 10, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of non-volatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. For example, the plurality of nonvolatile memory chips are shown to communicate with the controller 2200 through the first through kth channels CH1 through CHk.

Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS. 1 to 8.

In FIG. 10, a plurality of nonvolatile memory chips are connected to one channel. However, it will be understood that the memory system 2000 can be modified such that one non-volatile memory chip is connected to one channel.

FIG. 11 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 10.

Referring to FIG. 11, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, and a memory system 2000. .

The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power source 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 11, the nonvolatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the nonvolatile memory device 2100 may be configured to be directly connected to the system bus 3500.

In FIG. 11, the memory system 2000 described with reference to FIG. 10 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 9.

In exemplary embodiments, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 9 and 10.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: nonvolatile memory device 110: first encoder
120: second encoder 180: light circuit
190: memory core 210: lead circuit
220: decoder 230: data generator

Claims (17)

Matching first write data and read data, and inverting or non-inverting the first write data according to the matching result to generate second write data, and setting a first inversion flag indicating whether the first write data is inverted. A first encoder for generating; And
And a second encoder for ECC coding the second write data and the first inverted flag to generate a first parity bit. The method of claim 1,
And the first encoder determines whether to invert according to the number of bits matched with each other of the first write data and the read data. The method of claim 2,
And if the matched number of bits is less than a reference, the first inversion flag indicates inversion. The method of claim 2,
And if the matched number of bits is greater than a reference, the first inversion flag indicates non-inversion. The method of claim 2, wherein the first encoder
A first counter for counting the number of bits matched with each other of the first write data and the read data;
A second counter for counting the inversion data of the first write data and the number of bits matched with each other of the read data;
And a flag generator configured to generate the first inverted flag by comparing the number counted in the first counter with the number counted in the second counter. The method of claim 1,
Further comprising a memory core storing core data, a second inversion flag and a second parity bit,
The read data is a signal generated using the core data, the second inversion flag, and the second parity bit. The method according to claim 6,
A decoder that detects and corrects an error of the core data and the second inversion flag by using the second parity bit;
And a data generator configured to invert or non-invert the corrected core data and output the read data as read data according to the corrected second inversion flag. The method of claim 7, wherein the decoder
A syndrome generator configured to generate a syndrome using the second parity bit;
And an error position detector for detecting an error position of the core data and the second inversion flag by using the syndrome. The method of claim 1,
And the memory core includes a plurality of phase change memory cells. A memory core including a plurality of nonvolatile memory cells; And
A program circuit for programming codewords in the plurality of nonvolatile memory cells,
The codeword is
Second light data,
A first inversion flag indicating inversion information associated with the second write data;
And a first parity bit generated by ECC coding the second write data and the first inversion flag. The method of claim 10,
A read circuit for reading core data, a second inversion flag, and a second parity bit from the plurality of nonvolatile memory cells;
A decoder that detects and corrects an error of the core data and the second inversion flag by using the second parity bit;
And a data generator configured to invert or non-invert the corrected core data and output the read data as read data according to the corrected second inversion flag. 12. The method of claim 11,
Matching the first write data with the read data, and inverting or non-inverting the first write data according to the matching result to generate the second write data, and the first write data indicating whether the first write data is inverted. A first encoder for generating an inversion flag,
And a second encoder for ECC coding the second write data and the first inverted flag to generate the first parity bit. 13. The method of claim 12,
And the first encoder determines whether to invert according to the number of bits matched with each other of the first write data and the read data. Matching the first write data with the read data to generate a first inversion flag for determining whether to inversion;
Generating second write data by inverting or non-inverting the first write data according to the first inversion flag;
ECC coding the second write data and the first inversion flag to generate a first parity bit,
And storing the second write data, the first inversion flag, and the first parity bit in a memory core. The method of claim 14,
The generating of the first inverted flag may be generated according to the number of bits matched with each other of the first write data and the read data. 16. The method of claim 15,
And when the number of bits matched is less than a reference, the first inversion flag indicates inversion. 16. The method of claim 15,
And if the matched number of bits is greater than a reference, the first inversion flag indicates non-inversion.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140113101A (en) * 2013-03-15 2014-09-24 삼성전자주식회사 Non-volatile memory device and data write method thereof
US9070467B2 (en) 2012-09-07 2015-06-30 Samsung Electronics Co., Ltd. Memory system including nonvolatile memory device and control method thereof
US10037816B2 (en) 2016-12-20 2018-07-31 SK Hynix Inc. Memory controller, memory system including the same and operating method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070467B2 (en) 2012-09-07 2015-06-30 Samsung Electronics Co., Ltd. Memory system including nonvolatile memory device and control method thereof
KR20140113101A (en) * 2013-03-15 2014-09-24 삼성전자주식회사 Non-volatile memory device and data write method thereof
US10037816B2 (en) 2016-12-20 2018-07-31 SK Hynix Inc. Memory controller, memory system including the same and operating method thereof

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