KR101816642B1 - Error correction circuit, nonvolatile memory device thereof and driving method thereof - Google Patents

Abstract

An error correction circuit, a nonvolatile memory device including the same, and a driving method thereof are provided. The error correction circuit includes an encoder for receiving the message data and generating a bit error correctable parity bit, and a decoder for receiving the message data and the parity bit and calculating the error position of the message data, (Where n is a natural number greater than 1) bit by bit into the encoder, and the message data is input to the decoder in parallel by n bits different from n (m is a natural number greater than 1).

Description

[0001] The present invention relates to an error correction circuit, a nonvolatile memory device including the same, and a driving method thereof.

The present invention relates to an error correction circuit, a nonvolatile memory device including the same, and a driving method thereof.

Non-volatile memory devices using resistance materials include phase change random access memories (PRAM), phase change memory (PCM), resistive random access memory (RRAM), magnetic random access memory (MRAM) ). Dynamic RAM (DRAM) or flash memory devices store data using charge, while non-volatile memory devices using resistors are used to store phase change material states such as chalcogenide alloys (PRAM), resistance change of variable resistance (RRAM), and resistance change (MRAM) of MTJ (Magnetic Tunnel Junction) thin film according to magnetization state of ferromagnetic material.

Here, the phase change memory device will be described by way of example. The phase change material changes into a crystalline state or an amorphous state while being cooled after heating. The crystalline state phase change material has a low resistance and the amorphous state phase change material has a high resistance . Therefore, the determination state can be defined as set data, and the amorphous state can be defined as reset data.

However, the write operation is very slow in the phase change memory device as compared with the read operation. Since the amount of current consumed for the write operation is also large, the number of bits that can be simultaneously written is limited.

On the other hand, as the memory capacity of the nonvolatile memory device increases, it is necessary to use an error correction circuit for correcting the error of the defective memory cell. The error correction circuit includes, for example, a method using a redundancy memory cell and an ECC (Error Correction Code) method.

Here, the ECC method uses an ECC encoder and an ECC decoder, and the sizes of the ECC encoder and the ECC decoder are considerably large. Therefore, it is difficult to reduce the chip size of the nonvolatile memory device using the ECC method.

An object of the present invention is to provide an error correction circuit capable of minimizing the size.

Another object of the present invention is to provide a nonvolatile memory device capable of minimizing the size.

A further object of the present invention is to provide a method of driving the error correction circuit.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an error correction circuit comprising an encoder for receiving a message data and generating a parity bit capable of bit error correction, and an error correction circuit for receiving the message data and the parity bit, , And the message data is input to the encoder in parallel by n bits (n is a natural number greater than 1), and the message data is input to the encoder in parallel with m bits different from n (m is a natural number greater than 1) Decoder.

According to another aspect of the present invention, there is provided a nonvolatile memory device including a memory core including a nonvolatile memory cell, an encoder for receiving the message data and generating a bit error correctable parity bit, And a decoder for receiving the message data and the parity bit from the read circuit and calculating the error position of the message data, , And the message data is input to the encoder in parallel by n bits (n is a natural number greater than 1), and the message data is input to the decoder in parallel by n bits different from n (m is a natural number greater than 1).

According to another aspect of the present invention, there is provided a method of driving an error correction circuit including an encoder and a decoder. The encoder receives message data and generates a bit error correctable parity bit And a decoder for receiving the message data and the parity bit and calculating an error position of the message data, wherein the message data is input to the encoder in parallel by n bits (n is a natural number greater than 1) The message data is input to the decoder in parallel by n bits different from n (m is a natural number greater than 1).

According to another aspect of the present invention, there is provided a method of driving an error correction circuit including an encoder and a decoder, the encoder including: And the decoder generates parity bits by performing ECC encoding every n bits of the message data, and the decoder receives n * k bits of parity bits and message data, And calculating the position.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a non-volatile memory device according to some embodiments of the invention.
2 is a diagram for illustrating an exemplary nonvolatile memory cell in the memory core shown in FIG.
3 is a block diagram for explaining the encoder shown in FIG.
4 is a circuit diagram for explaining the encoder shown in Fig.
5 is a timing chart for explaining the operation of the encoder shown in Fig.
6 is a block diagram for explaining the decoder shown in FIG.
7 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.
8 is a block diagram illustrating an application example of the memory system of FIG.
9 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described using a phase change random access memory (PRAM). However, it is apparent to those skilled in the art that the present invention can be applied to both nonvolatile memory devices using resistors such as resistive memory devices (RRAMs) and ferroelectric RAM devices (FRAMs).

1 is a block diagram illustrating a non-volatile memory device according to some embodiments of the invention. 2 is a diagram for illustrating an exemplary nonvolatile memory cell in the memory core shown in FIG.

1, a non-volatile memory device 1 according to some embodiments of the present invention includes an encoder 110, a write circuit 180, a memory core 190, a read circuit 210, a decoder 220, . Through such a configuration, the nonvolatile memory device 1 according to some embodiments of the present invention can perform an error correction operation using ECC.

The memory core 190 may include a plurality of non-volatile memory cells (see MC in FIG. 5). The nonvolatile memory cell MC can write or read data by using a resistor. The nonvolatile memory cell MC includes a variable resistance element RC having a phase change material whose resistance varies according to data to be stored and an access element AC for controlling a current flowing through the variable resistance element RC can do. Here, the access element AC may be a diode, a transistor, or the like coupled in series with the variable resistive element RC. In the drawing, a diode is shown as a variable resistance element (RC). The phase change material is GaSb, InSb, and InSe. Sb2Te3, GeTe, GeSbTe, GaSeTe, InSbTe, SnSb2Te4, InSbGe combined with four elements, AgInSbTe, GeSn, SbTe, GeSb (SeTe), Te81Ge15Sb2S2 and the like can be used. Of these, GeSbTe composed of germanium (Ge), antimony (Sb) and tellurium (Te) can be mainly used.

The encoder 110 receives the message data M_DATA and generates a bit error correctable parity bit (ECCP).

The write circuit 180 writes the message data M_DATA and the parity bit ECCP to the memory core 190. Here, the "message data (M_DATA) + parity bit (ECCP)" may be referred to as "codeword" (CW).

The read circuit 210 reads out the message data M_DATA and the parity bit ECCP which have been stored in the memory core 190. [

The decoder 220 receives the message data M_DATA and the parity bit (ECCP) from the read circuit 210 and calculates the error position of the message data M_DATA. Thereafter, the decoder 220 can correct the message data M_DATA and output the corrected message data CORRECTED_DATA.

In the nonvolatile memory device 1 according to some embodiments of the present invention, the number of message data M_DATA input in parallel to the encoder 110 and the number of message data M_DATA input in parallel to the decoder 220 The number may vary. In other words, the message data M_DATA is input to the encoder 110 in parallel by n bits (where n is a natural number greater than 1), and the message data M_DATA is m different from n (where m is larger than 1 Natural number) bits to the decoder 220 in parallel. For example, the number of message data M_DATA input to the encoder 110 in parallel can be made smaller than the number of message data M_DATA input to the decoder 220 in parallel.

The encoder 110 receives the message data M_DATA every n bits of k (k is a natural number larger than 1) and performs ECC encoding every n bits of the message data M_DATA to generate a parity bit ECCP). As a result, the encoder 110 receives the nxk bits to complete the parity bit (ECCP). However, the encoder 110 does not generate parity bits (ECCP) by simultaneously encoding nxk bits, but repeats k times of receiving "message data (M_DATA) in n bits and performing ECC encoding" Bit (ECCP).

In addition, the decoder 220 simultaneously encodes the m-bit message data M_DATA. Here, m may be a multiple of k (where k is a natural number greater than 1) times n.

As a result, the decoder 220 calculates the error position of the message data M_DATA using the m-bit message data M_DATA, and the encoder 110 calculates the error location of the message data M_DATA of m (= nxk) To generate a parity bit (ECCP).

However, the encoder 110 and the decoder 220 are configured asymmetric. That is, the encoder 110 is not configured to simultaneously encode nxk bits of message data M_DATA, but is configured to simultaneously encode n bits of message data M_DATA. The encoder 110 has a very small number of message data M_DATA to be simultaneously encoded. Thus, the size of the encoder 110 used in the non-volatile memory device 1 according to some embodiments of the present invention can be significantly reduced. Asymmetrically configuring the encoder 110 and the decoder 220 may result in a size reduction effect of about 88% compared to configuring the encoder 110 and the decoder 220 symmetrically.

The ECC encoding operation will be described later in detail with reference to FIGS. 3 to 5, and the ECC decoding operation will be described later in detail with reference to FIG.

On the other hand, in the case of a nonvolatile memory cell (for example, a phase change memory cell) using a resistor as described above, the write operation speed is very slow compared to the read operation speed. In addition, the level of the write current used in the write operation is much higher than the read current used in the read operation. Therefore, because of the current capacity, the number of nonvolatile memory cells MC that can be read at the same time is considerably larger than the number of nonvolatile memory cells MC that can be simultaneously written. For example, the write circuit 180 may include 32 write drivers so that it can simultaneously write to 32 nonvolatile memory cells MC. On the other hand, the read circuit 210 includes 256 sense amplifiers, and can read simultaneously from 256 nonvolatile memory cells MC.

Therefore, in the nonvolatile memory device 1 according to some embodiments of the present invention, the number of message data M_DATA that are simultaneously encoded by the encoder 110 to correspond to the write circuit 180 may be small. Also, the number of message data (M_DATA) to be simultaneously encoded by the decoder 220 to correspond to the read circuit 210 may be large.

To summarize, the write circuit 180 can write n-bit message data M_DATA simultaneously including n write drivers (not shown). The encoder 110 receives the message data M_DATA in parallel in units of n bits, and can simultaneously encode n bits at a time. Also, the read circuit 210 may include m sense amplifiers (not shown) to simultaneously read the m-bit message data M_DATA. The decoder 220 may receive and process the message data M_DATA in parallel by m bits at a time.

3 to 5, the ECC encoding process of the encoder 110 will be described in detail.

3 is a block diagram for explaining the encoder shown in FIG. 4 is a circuit diagram for explaining the encoder shown in Fig. 5 is a timing chart for explaining the operation of the encoder shown in Fig.

3, the encoder 110 may include an XOR gate array 112, a D flip flop array 114, and the like.

The XOR gate array 112 outputs the pre-parity bit PRE_ECCP. Referring to FIGS. 4 and 5, the pre-parity bit PRE_ECCP may mean k pre-parity bits (PRE_ECCP_1 to PRE_ECCP_k) sequentially output. Here, the last k th pre-parity bit PRE_ECCP_k may be a parity bit (ECCP). Further, each of the parity bits PRE_ECCP_q may be p (where q is a natural number greater than 1 and less than or equal to k). For example, PRE_ECCP_q includes PRE_ECCP_q [0] to PRE_ECCP_q [p-1].

The XOR gate array 112 may include a plurality of XOR gates 112_1 to 112_p. Some bits selected from the n-bit message data M_DATA are input to the XOR gates 112_1 to 112_p. Further, a pre-parity bit PRE_ECCP_q is fed back to each of the XOR gates 112_1 to 112_p. The pre-parity bit PRE_ECCP_q may be fed back to at least one of the XOR gates 112_1 to 112_p among the plurality of XOR gates 112_1 to 112_p. For example, PRE_ECCP_k [0] may be fed back to two XOR gates 112_1 and 112_2, and PRE_ECCP_k [1] may be fed back to two XOR gates 112_2 and 112_3.

The D flip flop array 114 may include a plurality of D flip flops 114_1 through 114_p. Each D flip-flop 114_1 to 114_p transfers the output of the XOR gate (i.e., the parity bit PRE_ECCP_q) in response to the load signal LOAD. Each D flip-flop 114_1 to 114_p is reset in response to a reset signal RST.

Hereinafter, the operation of the encoder 110 will be summarized below with reference to FIGS. 4 and 5. FIG. Hereinafter, for convenience of explanation, it is assumed that the message data is sequentially inputted eight times by 32 bits (i.e., n = 32, k = 8).

Referring to reference numeral a, when the CORE-Write Start signal is enabled, the CORE-Read signal is enabled.

Thereafter, the address WORDADDR and the message data M_DATA are sequentially input.

Referring to reference numerals b and c, the CORE-Write start signal is enabled, and the message data M_DATA is written to the memory core 190. When the write is complete, the CORE-Write done signal is enabled.

Referring to reference numerals d and e, the XOR gate array 112 of the encoder 110 generates a first pre-parity bit (PRE_ECCP_1) using the pre-parity bit and the message data M_DATA in the reset state. When the load signal LOAD is input, the D flip-flop array 114 feeds back the first pre-parity bit PRE_ECCP_1.

That is, the XOR gate array 112 uses the pre-parity bit PRE_ECCP_q-1 and the message data M_DATA of q-1 (where q is a natural number larger than 1 and smaller than or equal to k) and message data M_DATA, Bit PRE_ECCP_q. The (q-1) th parity bit PRE_ECCP is fed back from the D flip flop array 114.

The same operation as described above is repeated. As a result, a k th pre-parity bit PRE_ECCP_k is generated (see reference symbol f). The k th pre-parity bit PRE_ECCP_k is output as a parity bit ECCP.

When g is tapped, the D flip-flop array 114 is reset in response to the reset signal RST after outputting the parity bit ECCP.

6 is a block diagram for explaining the decoder shown in FIG.

Referring to FIG. 6, the decoder 220 may include a syndrome generator 222, an error location detector 224, an error corrector 226, and the like.

The syndrome generator 222 generates a syndrome (SDR) using the message data M_DATA and the parity bit ECCP. The error position detector 224 detects the error position of the message data M_DATA using the syndrome (SDR). For example, the error location detector 224 may use two or more syndromes (SDR) to calculate the coefficients of the error location equation and to detect the error location based on the coefficients. The error corrector 226 corrects the error of the message data M_DATA based on the detected error position. Corrected message data is called CORRECTED_DATA.

Here, the decoder 220 receives m bits of the message data M_DATA and can simultaneously decode the m bits of the message data M_DATA. Here, m may be n x k.

On the other hand, the description of ECC encoding / decoding using Figs. 2 to 6 mainly shows a case of error correction of 1 bit. This is merely an example, and the present invention is equally applicable to error correction of two or more bits.

7 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.

Referring to FIG. 7, memory system 1000 includes a non-volatile memory device 1100 and a controller 1200.

The non-volatile memory device 1100 may be configured and operated as described with reference to Figures 1-6.

The controller 1200 is connected to the host (Host) and the nonvolatile memory device 1100. In response to a request from the host (Host), the controller 1200 is configured to access the non-volatile memory device 1100. For example, the controller 1200 is configured to control the read, write, erase, and background operations of the non-volatile memory device 1100. The controller 1200 is configured to provide an interface between the non-volatile memory device 1100 and the host (Host). The controller 1200 is configured to drive firmware for controlling the non-volatile memory device 1100.

Illustratively, controller 1200 further includes well known components such as RAM (Random Access Memory), a processing unit, a host interface, and a memory interface. The RAM may be used as at least one of an operation memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls all operations of the controller 1200.

The host interface includes a protocol for performing data exchange between the host (Host) and the controller 1200. Illustratively, the controller 1200 may be implemented using any of a variety of communication protocols, such as a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- (Host) interface through at least one of various interface protocols such as a Serial-ATA protocol, a Parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, . The memory interface interfaces with the non-volatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be further configured to include error correction blocks. The error correction block is configured to detect and correct errors in the data read from non-volatile memory device 1100 using an error correction code (ECC). Illustratively, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the non-volatile memory device 1100.

Controller 1200 and non-volatile memory device 1100 may be integrated into a single semiconductor device. Illustratively, the controller 1200 and the non-volatile memory device 1100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1200 and the non-volatile memory device 1100 may be integrated into a single semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM) (SD), miniSD, microSD, SDHC), universal flash memory (UFS), and the like.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is drastically improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

Illustratively, non-volatile memory device 1100 or memory system 1000 may be implemented in various types of packages. For example, the non-volatile memory device 1100 or the memory system 1000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers Linear Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package -Level Processed Stack Package (WSP) or the like.

8 is a block diagram illustrating an application example of the memory system of FIG.

8, the memory system 2000 includes a non-volatile memory device 2100 and a controller 2200. The non- Non-volatile memory device 2100 includes a plurality of non-volatile memory chips. The plurality of non-volatile memory chips are divided into a plurality of groups. Each group of the plurality of non-volatile memory chips is configured to communicate with the controller 2200 over one common channel. For example, a plurality of non-volatile memory chips are shown as communicating with controller 2200 through first through k-th channels CH1-CHk.

Each non-volatile memory chip is configured similarly to the non-volatile memory device 100 described with reference to Figures 1-6.

In Fig. 8, it has been described that a plurality of nonvolatile memory chips are connected to one channel. However, it will be appreciated that the memory system 2000 can be modified such that one nonvolatile memory chip is connected to one channel.

9 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

9, the computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power source 3400, and a memory system 2000 .

The memory system 2000 is electrically coupled to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 9, non-volatile memory device 2100 is shown coupled to system bus 3500 via controller 2200. However, the non-volatile memory device 2100 may be configured to be coupled directly to the system bus 3500.

In FIG. 9, it is shown that the memory system 2000 described with reference to FIG. 8 is provided. However, the memory system 2000 may be replaced by the memory system 1000 described with reference to FIG.

Illustratively, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to FIGS.

On the other hand, the error correction circuit used in the nonvolatile memory device 1 according to some embodiments of the present invention is not limited to the memory device.

It can be applied to any device in which the encoder and the decoder are configured asymmetric. That is, the encoder is not configured to simultaneously encode nxk bits of message data, but is configured to simultaneously encode n bits of message data. In addition, the encoder performs an encoding operation every n bits of received message data, and finally outputs the parity bit. On the other hand, the decoder can simultaneously decode nxk bits of message data to find the error location of the message data. That is, it can be applied to any device if it has such a configuration.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: non-volatile memory device 110: encoder
112: XOR gate array 114: D flip flop array
180: write circuit 190: memory core
210: Read circuit 220: Decoder

Claims (10)

An encoder receiving the message data and generating a bit error correctable parity bit; And
And a decoder receiving the message data and the parity bit and calculating an error position of the message data,
Wherein the message data is input to the encoder in parallel by n bits (n is a natural number greater than 1), and the message data is m (where k is a natural number greater than 1) 1) bits in parallel to the decoder,
The encoder receives the message data k times in units of n bits and performs ECC (Error Correction Code) encoding every n bits of the message data to generate first through k-th pre-parity bits, Generating the parity bit by outputting the k < th > pre-parity bit as the parity bit,
The error correction circuit is generated by ECC encoding a q-th (n is a natural number greater than 1 and less than or equal to k) q-th pre-parity bit and the message data. The method according to claim 1,
Wherein the decoder is capable of 1-bit error correction of the message data. delete delete delete delete 2. The apparatus of claim 1, wherein the encoder
And a D flip flop array for transferring the q-th < th > pre-parity bit in response to a load signal,
Wherein the XOR gate array receives the q-1 pre-parity bits output from the D flip-flop array and receives the message data to generate a q pre-parity bit. A memory core including a non-volatile memory cell;
An encoder receiving the message data and generating a bit error correctable parity bit;
A write circuit for writing the message data and the parity bit to the memory core;
A read circuit for reading the message data and the parity bit stored in the memory core; And
And a decoder for receiving the message data and the parity bit from the read circuit and calculating an error position of the message data,
Wherein the message data is input to the encoder in parallel by n bits (n is a natural number greater than 1), and the message data is m (where k is a natural number greater than 1) 1) bits in parallel to the decoder,
The encoder receives the message data k times in units of n bits and performs ECC encoding every n bits of the message data to sequentially generate first to kth pre-parity bits And outputs the k-th parity bit as the parity bit to generate the parity bit,
The non-volatile memory device according to claim 1, wherein the q-th pre-parity bit is generated by ECC-encoding the q-1 pre-parity bit and the message data. 9. The method of claim 8,
Wherein the write circuit includes n write drivers, and is capable of simultaneously writing the n-bit message data. A method of driving an error correction circuit including an encoder and a decoder,
The encoder receives the message data k times n times (where n is a natural number greater than 1) and performs ECC encoding every n bits of the message data to generate first through kth pre-parity bits pre -parity bits), generating the parity bits by outputting the k < th > pre-parity bits as the parity bits,
Wherein the decoder receives n * k bits of the parity bit and the message data to calculate an error position of the message data,
The method of claim 1, wherein the q-th pre-parity bit is a natural number smaller than or equal to k, and wherein the q-th pre-parity bit and the message data are ECC-encoded.

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