KR20130007374A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve the operation property of the semiconductor device by reducing the coupling capacitance of a metal wire through a void between metal wires. CONSTITUTION: A device isolation layer(120) defining an active region(110) is formed on a semiconductor substrate(100). A first interlayer dielectric layer(130) is formed on the active region. A first etch stop layer(140) is formed on the first interlayer dielectric layer. A barrier metal pattern(150), a tungsten pattern(160), and a nitride pattern(170) are successively formed on the first etch stop layer. An insulation layer(220) is deposited on the surface including an oxide film pattern(210). A third interlayer dielectric layer(230) is formed on the insulation layer and the oxide film pattern.

Description

Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the coupling capacitance of a metal wiring in manufacturing a highly integrated semiconductor device.

In general, a metal wire is formed in the semiconductor device to electrically connect the device and the device or between the wiring and the wire, and a contact plug is formed for the connection between the upper metal wire and the lower metal wire.

As the integration of semiconductor devices proceeds, the spacing between metal wires is gradually reduced. However, a pair of adjacent metal wires and an interlayer insulating film interposed therebetween act as a capacitor, and as the spacing between the metal wires decreases, coupling capacitance between adjacent metal wires increases. As a result, a phenomenon in which the operating speed of the device decreases occurs. This means that the higher the integration of the device, the lower the operating speed may be.

On the other hand, the easiest way to implement a high-speed device is to increase the thickness and width of the metal wiring to reduce the resistance of the metal wiring itself.

However, the method of increasing the thickness encounters a problem that the reliability of the metal film etching process is not secured, and the method of increasing the width reduces the spacing between the metal wires, thereby increasing the coupling capacitance. I run into a problem.

In addition, the coupling capacitance between adjacent metal lines may be reduced by applying a material having a low dielectric constant? As an interlayer insulating film. Therefore, in recent years, development of a low dielectric material having a lower dielectric constant than a silicon oxide film (SiO 2) as an interlayer insulating film has been actively made. However, since the material to replace the silicon oxide film is in the development stage and has not been commercialized yet, the problem of a decrease in the operation speed of the device due to the increase in the coupling capacitance between the metal wires has not been practically solved.

In order to solve the above-mentioned conventional problem, the present invention provides a coupling generated in the metal wiring by forming a void between the metal wiring in the peripheral circuit region in order to improve the coupling capacitance of the metal wiring. The present invention provides a method of manufacturing a semiconductor device capable of improving operating characteristics of a semiconductor device such as a sand amplifier and a sub word line of a high integration peripheral circuit area by reducing capacitance.

The present invention provides a method of forming a hard mask layer including a wiring and a poly on a semiconductor substrate, oxidizing the poly to form a polymer pattern and an oxide film pattern, and filling a first insulating film on the entire surface including the wiring, Forming a void between the wirings, forming a void between the wirings, etching back the first insulating film until the poly pattern is exposed, and exposing the poly pattern And forming a second insulating film on the oxide film pattern and the first insulating film.

Preferably, the wiring is formed by including a barrier metal and tungsten.

The method may further include forming a nitride film between the wiring and the poly.

The method may further include forming an etch stop layer between the semiconductor substrate and the wiring.

Preferably, the step of oxidizing the poly to form a poly pattern and an oxide film pattern is characterized in that the poly is oxidized using a heat and oxygen process.

Preferably, the first insulating film is characterized in that it comprises a HDP (High Density Plasma) film.

Preferably, upon removal of the poly pattern, the etching solution is characterized in that it comprises hydrofluoric acid, nitric acid and acetic acid.

The present invention reduces the coupling capacitance generated in the metal wiring by forming a void between the metal wirings in the peripheral circuit region to improve the coupling capacitance of the metal wiring, thereby reducing the integration capacitance. There is an advantage that can improve the operating characteristics of the semiconductor device, such as the sand amplifier and sub word line of the peripheral circuit area.

1A to 1K are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1A to 1K are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

Referring to FIG. 1A, an isolation layer 120 defining an active region 110 is formed on a semiconductor substrate 100.

Next, the gate pattern 125 is formed on the active region 110. Here, the gate pattern 125 is formed of a stacked structure of poly (111, Poly), barrier metal 112 (barrier metal), tungsten (113, W) and nitride film 114 (Nitride), and the gate pattern 125 It is preferable to form spacers 115 on the sidewalls.

 Next, the first interlayer insulating layer 130 is formed on the entire surface including the gate pattern 125, and then planarized etching is performed using a chemical mechanical polishing method. In this case, the first interlayer insulating layer 130 may be formed of an oxide film. Thereafter, a first etch stop layer 140 is formed on the first interlayer insulating layer 130. In this case, the first etch stop layer 140 is formed of a nitride film (Nitride), it is preferable to form a thickness of 50 ~ 100 ~. The first etch stop layer 140 serves as a protective layer when the first interlayer insulating layer 130 is removed in a subsequent process.

Referring to FIG. 1B, a barrier metal, tungsten (W), nitride, and poly are sequentially stacked on the first etch stop layer 140.

Then, after the photosensitive film is formed on the poly, a photosensitive film pattern (not shown) is formed by an exposure and development process using a wiring forming mask. The barrier metal pattern 150, tungsten pattern 160, nitride film pattern 170 and poly The pattern 180 is formed. Here, the barrier metal pattern 150, the tungsten pattern 160, the nitride film pattern 170, and the poly pattern 180 are defined as wirings.

Referring to FIG. 1C, a second interlayer insulating layer 190 is formed on the first etch stop layer 140, the barrier metal pattern 150, the tungsten pattern 160, the nitride layer pattern 170, and the poly pattern 180. After forming, an etchback process is performed until the poly pattern 180 is exposed. In this case, the second interlayer insulating layer 190 is preferably formed of a TEOS (Tetra Ethyl Ortho Silicate) film, and preferably, a chemical vapor deposition (CVD) process is used.

1D and 1E, a second etch stop layer 200 is formed on the poly pattern 180 and the second interlayer insulating layer 190. In this case, the second etch stop layer 200 preferably includes a nitride layer, and the plate is a process for forming a capacitor in the cell region due to the second etch stop layer 200. It protects the peripheral circuit area during the process and the dip out process.

Thereafter, the second etch stop layer 200 is removed using a dip out process using a phosphoric acid or a nitride film etching process.

Referring to FIG. 1F, the second interlayer insulating layer 190 is removed using a dip out process. In this case, damage to the lower layer may be prevented due to the first etch stop layer 140.

Referring to FIG. 1G, the poly pattern 180 is oxidized through a thermal treatment and an oxidation process. In this case, the poly pattern 180 is oxidized to form an oxide film pattern 210 around the poly pattern 180. That is, the thickness of the poly pattern 180 is reduced, and the thickness of the oxide film pattern 210 formed by oxidizing the poly pattern 180 is increased.

Referring to FIG. 1H, an insulating layer 220 is deposited on the entire surface including the oxide layer pattern 210. At this time, the insulating film 220 is preferably formed of an oxide (Oxide), in particular, the insulating film 220 is formed in the form of connecting the oxide film pattern 210 to each other using a high density plasma (HDP) film. That is, since the HDP film has a poor gapfill property, the HDP film is not deposited on the surface of the wiring including patterns such as the barrier metal pattern 150, the tungsten pattern 160, the nitride film pattern 170, and the poly pattern 180. Since they are formed around the oxide film pattern 210 and connected to each other, an empty space or a void is formed between the wires. By forming such an empty space or void, a coupling capacitance generated between the wirings in the peripheral circuit region is reduced.

Referring to FIG. 1I, the oxide layer pattern 210 is etched back until the poly pattern 180 is exposed, or planarized etching is performed using a method such as chemical mechanical polishing (CMP).

Referring to FIG. 1J, the poly pattern 180 is removed using a poly etching solution. At this time, the poly etching solution preferably includes hydrofluoric acid, nitric acid and acetic acid.

Referring to FIG. 1K, a third interlayer insulating film 230 is formed on the insulating film 220 and the oxide film pattern 210. In this case, the third interlayer insulating film 230 may be formed of a TEOS (Tetra Ethyl Ortho Silicate) film.

2 is a block diagram illustrating a configuration of a cell array according to the present invention.

Referring to FIG. 2, a cell array includes a plurality of memory cells, and each memory cell includes one transistor and one capacitor. These memory cells are located at the intersection of the bit lines BL1,... BLn and the word lines WL1..., WLm. The memory cells store or output data based on voltages applied to the bit lines BL1,... BLn and the word lines WL1, .. WLm selected by the column decoder and the row decoder.

As shown, in the cell array, the bit lines BL1,... BLn are formed in the first direction (ie, the bit line direction) in the longitudinal direction, and the word lines WL1... The word line direction) is formed in the longitudinal direction and arranged in a cross shape with each other. The first terminal (eg, drain terminal) of the transistor is connected to the bit lines BL1,..., BLn, the second terminal (eg, source terminal) is connected to the capacitor, and the third terminal ( For example, the gate terminal is connected to the word lines WL1, ..., WLm. A plurality of memory cells including these bit lines BL1 to BLn and word lines WL1 to WLm are positioned in the semiconductor cell array.

3 is a block diagram illustrating a configuration of a semiconductor device according to the present invention.

Referring to FIG. 3, a semiconductor device may include a cell array, a row decoder, a column decoder, and a sense amplifier (SA). The row decoder selects a word line corresponding to a memory cell to perform a read operation or a write operation among word lines of the semiconductor cell array, and outputs a word line selection signal RS to the semiconductor cell array. The column decoder selects a bit line corresponding to a memory cell to perform a read operation or a write operation among the bit lines of the semiconductor cell array, and outputs a bit line selection signal CS to the semiconductor cell array. In addition, the sense amplifiers sense data BDS stored in memory cells selected by the row decoder and the column decoder.

In addition, the semiconductor device may be connected to a microprocessor or a memory controller, and the semiconductor device receives control signals such as WE *, RAS *, and CAS * from the microprocessor, and receives input / output circuits. Receive and store data. The semiconductor device may be applied to DRAM (Random Access Memory), Piram (Random Access Memory), MRAM (Random Access Memory), NAND flash, CMOS Image Sensor (CIS), and the like. In particular, DRAM can be used for desktops, laptops, servers, graphics memory and mobile memory, and NAND flash can be used for portable storage devices such as memory sticks, MMC, SD, CF, xD Picture Card, USB Flash Drive, It can be applied to various digital applications such as MP3, PMP, digital cameras, camcorders, memory cards, USB, game consoles, navigation, laptops, desktop computers and mobile phones.CIS is an imaging device that acts as a kind of electronic film in digital devices. Applicable to camera phones, web cameras, medical medical imaging equipment.

4 is a block diagram illustrating a configuration of a semiconductor module according to the present invention.

Referring to FIG. 4, a semiconductor module includes a plurality of semiconductor devices mounted on a module substrate, and a semiconductor device includes control signals (address signal ADDR, command signal CMD, and clock signal) from an external controller (not shown). CLK)) includes a command link for receiving the data and a data link connected with the semiconductor device to transmit data.

In this case, for example, the semiconductor devices illustrated in the description of FIG. 3 may be used. In addition, the command link and the data link may be formed in the same or similar to those used in a conventional semiconductor module.

In FIG. 4, eight semiconductor devices are mounted on the front surface of the module substrate, but semiconductor devices may be mounted on the rear surface of the module substrate. That is, the semiconductor devices may be mounted on one or both sides of the module substrate, and the number of semiconductor devices to be mounted is not limited to FIG. 4. In addition, the material and structure of the module substrate are not particularly limited.

5 is a block diagram illustrating a configuration of a semiconductor system according to the present invention.

Referring to FIG. 5, a semiconductor system includes a controller for controlling an operation of a semiconductor module by providing a bidirectional interface between at least one semiconductor module having a plurality of semiconductor devices and a semiconductor module and an external system (not shown). It includes. Such a controller may be formed identically or similarly to a controller for controlling the operation of a plurality of semiconductor modules in a conventional data processing system. Therefore, detailed description thereof will be omitted in the present embodiment. In this case, the semiconductor module illustrated in FIG. 4 may be used as the semiconductor module.

6 is a block diagram illustrating the configuration of an electronic unit and an electronic system according to the present invention.

Referring to the left side of FIG. 6, an electronic unit according to the present invention includes a processor electrically connected to a semiconductor system. In this case, the semiconductor system is the same as the semiconductor system of FIG. 5. Here, the processor includes a central processing unit (CPU), a micro processor unit (MPU), a micro controller unit (MCU), a graphics processing unit (GPU), and a digital signal processor (DSP).

Here, the CPU or MPU is a combination of an Arithmetic Logic Unit (ALU), which is an arithmetic and logical operation unit, and a control unit (CU) that controls each unit by reading and interpreting an instruction. When the processor is a CPU or MPU, the electronic unit preferably includes a computer device or a mobile device. Also, the GPU is a CPU for graphics, which is used to calculate numbers with decimal points, and is a process for drawing graphics on a real-time screen. If the processor is a GPU, the electronic unit preferably includes a graphics device. In addition, DSP refers to a process of converting an analog signal (for example, voice) into a digital signal after high-speed conversion, using the result, or converting it back to analog. DSP mainly calculates digital values. When the processor is a DSP, the electronic unit preferably includes audio and video equipment.

In addition, the processor includes an accelerator processor unit (APU), which integrates the CPU into the GPU and includes the role of a graphics card.

Referring to the right diagram of FIG. 6, an electronic system includes one or more interfaces electrically connected to an electronic unit. At this time, the electronic unit is the same as the electronic unit of FIG. 6. Here, the interface includes a monitor, keyboard, printer, pointing device (mouse), USB, switch, card reader, keypad, dispenser, telephone, display or speaker. However, the present invention is not limited thereto and may be changed.

As described above, the present invention provides a coupling capacitance generated in the metal wiring by forming a void between the metal wirings in the peripheral circuit region in order to improve the coupling capacitance of the metal wiring. It is possible to improve the operating characteristics of the semiconductor device, such as the sand amplifier and the sub word line of the highly integrated peripheral circuit area by reducing the.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (7)

Forming a hard mask layer including wiring and poly on a semiconductor substrate;
Oxidizing the poly to form a poly pattern and an oxide film pattern;
Embedding a first insulating film on the entire surface including the wiring, wherein the first insulating film is formed to connect the oxide film patterns, and a void is formed between the wirings;
Etching back the first insulating layer until the poly pattern is exposed;
Removing the exposed poly pattern; And
Forming a second insulating film on the oxide film pattern and the first insulating film
And forming a second insulating film on the semiconductor substrate. The method according to claim 1,
The wiring is a method of manufacturing a semiconductor device, characterized in that it comprises a barrier metal and tungsten. The method according to claim 1,
And forming a nitride film between the wiring and the poly. The method according to claim 1,
And forming an etch stop layer between the semiconductor substrate and the wiring. The method according to claim 1,
Oxidizing the poly to form a poly pattern and an oxide film pattern
A method of manufacturing a semiconductor device, characterized in that the poly is oxidized using a heat and oxygen process. The method according to claim 1,
The first insulating film includes a high density plasma film (HDP) film manufacturing method, characterized in that the. The method according to claim 1,
When the poly pattern is removed, the etching solution includes a hydrofluoric acid, nitric acid and acetic acid.

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