KR20130107491A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- KR20130107491A KR20130107491A KR1020120029322A KR20120029322A KR20130107491A KR 20130107491 A KR20130107491 A KR 20130107491A KR 1020120029322 A KR1020120029322 A KR 1020120029322A KR 20120029322 A KR20120029322 A KR 20120029322A KR 20130107491 A KR20130107491 A KR 20130107491A
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- Prior art keywords
- gate electrode
- recess
- insulating film
- forming
- gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 79
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 22
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 10
- 239000007769 metal material Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000007792 addition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002059 diagnostic imaging Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same that improve short channel effect characteristics and operating current characteristics.
When a typical transistor is made on a semiconductor substrate, a gate is formed on the semiconductor substrate and doping impurities on both sides of the gate form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has gradually decreased, resulting in short channel effects and drain induced barrier lower (DIBL). The reliability of the operation was lowered. The phenomenon that occurs when the channel length is reduced can be overcome if the threshold voltage is maintained so that the cell transistor can perform a normal operation. Typically, the shorter the channel of the transistor, the greater the doping concentration of the impurity in the region where the channel is formed.
However, as the design rule decreases to less than 100 nm, the increase in doping concentration in the channel region further increases the electric field at the storage node (SN) junction, thereby degrading the refresh characteristics of the semiconductor memory device. Cause. In order to overcome this problem, a cell transistor having a three-dimensional channel structure in which a channel is long in a vertical direction is used so that the channel length of the cell transistor can be maintained even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating.
In addition, as the degree of integration of the semiconductor device increases, the distance between the word line and the bit line connected to the cell transistor is closer. As the parasitic capacitance increases, the operating margin of the sense amplifier, which amplifies the data transmitted through the bit line, is deteriorated, which adversely affects the operation reliability of the semiconductor device. In order to overcome this problem, a buried word line structure has been proposed in which word lines are formed only in recesses, not on top of a semiconductor substrate, in order to reduce parasitic capacitance between bit lines and word lines. The buried word line structure is formed with a bit line formed on a semiconductor substrate on which a source / drain is formed by forming a conductive material in a recess formed in the semiconductor substrate and covering the upper portion of the conductive material with an insulating film so that the word line is buried in the semiconductor substrate. Electrical isolation can be clarified.
However, the structure of the buried word line (buried gate) increases the leakage current due to the gate induced drain leakage (GIDL) of the semiconductor device between the conductive material (gate electrode) and the N-type junction or storage node contact of the active region. In addition, there is a problem in that the refresh characteristics of the entire semiconductor device are degraded due to deterioration of the GIDL characteristics. In order to prevent an increase in leakage current due to the GIDL characteristic, the conductive material (gate electrode) of the buried word line (buried gate) may be etched to minimize the overlap area between the storage node contact and the conductive material (gate electrode). Can be. However, if the conductive material (gate electrode) of the buried word line (buried gate) is etched a lot, the increase of the leakage current due to the gate induced drain leakage (GIDL) characteristic can be prevented, but the buried word line (buried gate) resistance increases. Therefore, there is a problem of causing a decrease in speed of the semiconductor device.
1 is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to the prior art. Referring to FIG. 1, a
Next, the
In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device and a method of manufacturing the same, which can prevent short channel effects and obtain excellent operating current characteristics by further forming a gate under the channel region. do.
The present invention provides a method of manufacturing a semiconductor device, the method comprising: etching a semiconductor substrate to form a first recess, embedding a first insulating film in the first recess, etching the first insulating film, and forming a second recess; Forming a first gate electrode in a recess, etching back the first gate electrode, embedding a second insulating film in an etched region, and etching the second insulating film and the first gate electrode to form a third gate electrode Forming a recess, forming a silicon layer on a surface of the third recess, forming a second gate electrode on the silicon layer to be buried in the third recess, and forming the second gate electrode After etching back, the method of manufacturing a semiconductor device comprising the step of embedding a third insulating film in the etched back region.
And forming a first gate insulating film between the forming of the third recess and the forming of the silicon layer.
And forming a second gate insulating film between the forming of the silicon layer and the forming of the second gate electrode.
The method may further include forming a device isolation region defining an active region in the semiconductor substrate before forming the first recess.
The forming of the second recess may include etching the first insulating layer, wherein the etched region is surrounded by the first insulating layer.
The forming of the third recess may include etching the second insulating layer and the first gate electrode, wherein the etched region is surrounded by the second insulating layer and the first gate electrode.
The first, second and third insulating layers may include a nitride or an oxide.
In addition, a first recess provided in the semiconductor substrate, a first insulating film formed along the surface of the first recess, a first gate electrode formed along the surface of the first insulating film in the first recess, and the first recess A second insulating film provided on the gate electrode, a silicon layer formed along the surface of the first gate electrode, a second gate electrode formed on the silicon layer, and a third insulating film provided on the second gate electrode. It provides a semiconductor device comprising a.
And a first gate insulating film provided between the first gate electrode and the silicon layer.
And a second gate insulating film provided between the silicon layer and the second gate electrode.
The first, second and third insulating films may include a nitride film or an oxide film.
According to the present invention, an additional gate is formed below the channel region to prevent short channel effects and to obtain excellent operating current characteristics.
1 is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to the prior art.
2A to 2F are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.
3 is a cross-sectional view showing a semiconductor device and a method of manufacturing the same according to another embodiment of the present invention.
4 is a block diagram illustrating a configuration of a cell array according to the present invention.
5 is a block diagram for explaining the configuration of a semiconductor device (Semiconductor Device) according to the present invention.
6 is a block diagram illustrating the configuration of a semiconductor module according to the present invention.
7 is a block diagram illustrating a configuration of a semiconductor system according to the present invention.
8 is a block diagram for explaining the configuration of an electronic unit and an electronic system according to the present invention;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .
2A to 2F are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.
Referring to FIG. 2A, an
Referring to FIG. 2B, the
Referring to FIG. 2C, the buried
Next, a
Referring to FIG. 2D, after the
Referring to FIG. 2E, the
Next, a first
The
Next, the second
Referring to FIG. 2F, a
Then, a
3 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present invention.
Referring to FIG. 3, an
Next, the
Next, a
The second buried
Next, a
Here, the first and second buried
4 is a block diagram illustrating a configuration of a cell array according to the present invention.
Referring to FIG. 4, a cell array includes a plurality of memory cells, and each memory cell includes one transistor and one capacitor. These memory cells are located at the intersection of the bit lines BL1,... BLn and the word lines WL1..., WLm. The memory cells store or output data based on voltages applied to the bit lines BL1,... BLn and the word lines WL1, .. WLm selected by the column decoder and the row decoder.
As shown, in the cell array, the bit lines BL1,... BLn are formed in the first direction (ie, the bit line direction) in the longitudinal direction, and the word lines WL1... The word line direction) is formed in the longitudinal direction and arranged in a cross shape with each other. The first terminal (eg, drain terminal) of the transistor is connected to the bit lines BL1,..., BLn, the second terminal (eg, source terminal) is connected to the capacitor, and the third terminal ( For example, the gate terminal is connected to the word lines WL1, ..., WLm. A plurality of memory cells including these bit lines BL1 to BLn and word lines WL1 to WLm are positioned in the semiconductor cell array.
5 is a block diagram illustrating a configuration of a semiconductor device according to the present invention.
Referring to FIG. 5, a semiconductor device may include a cell array, a row decoder, a column decoder, and a sense amplifier (SA). The row decoder selects a word line corresponding to a memory cell to perform a read operation or a write operation among word lines of the semiconductor cell array, and outputs a word line selection signal RS to the semiconductor cell array. The column decoder selects a bit line corresponding to a memory cell to perform a read operation or a write operation among the bit lines of the semiconductor cell array, and outputs a bit line selection signal CS to the semiconductor cell array. In addition, the sense amplifiers sense data BDS stored in memory cells selected by the row decoder and the column decoder.
In addition, the semiconductor device may be connected to a microprocessor or a memory controller, and the semiconductor device receives control signals such as WE *, RAS *, and CAS * from the microprocessor, and receives input / output circuits. Receive and store data. The semiconductor device may be applied to DRAM (Random Access Memory), Piram (Random Access Memory), MRAM (Random Access Memory), NAND flash, CMOS Image Sensor (CIS), and the like. In particular, DRAM can be used for desktops, laptops, servers, graphics memory and mobile memory, and NAND flash can be used for portable storage devices such as memory sticks, MMC, SD, CF, xD Picture Card, USB Flash Drive, It can be applied to various digital applications such as MP3, PMP, digital cameras, camcorders, memory cards, USB, game consoles, navigation, laptops, desktop computers and mobile phones.CIS is an imaging device that acts as a kind of electronic film in digital devices. Applicable to camera phones, web cameras, medical medical imaging equipment.
6 is a block diagram illustrating a configuration of a semiconductor module according to the present invention.
Referring to FIG. 6, a semiconductor module includes a plurality of semiconductor devices mounted on a module substrate, and the semiconductor device includes a control signal (address signal ADDR, command signal CMD, clock signal) from an external controller (not shown). CLK)) includes a command link for receiving the data and a data link connected with the semiconductor device to transmit data.
In this case, for example, the semiconductor devices illustrated in the description of FIG. 5 may be used. In addition, the command link and the data link may be formed in the same or similar to those used in a conventional semiconductor module.
In FIG. 6, eight semiconductor devices are mounted on the front surface of the module substrate, but semiconductor devices may be mounted on the rear surface of the module substrate. That is, semiconductor devices may be mounted on one side or both sides of the module substrate, and the number of semiconductor devices mounted is not limited to FIG. 6. In addition, the material and structure of the module substrate are not particularly limited.
7 is a block diagram illustrating a configuration of a semiconductor system according to the present invention.
Referring to FIG. 7, a semiconductor system may include a controller configured to control an operation of a semiconductor module by providing a bidirectional interface between at least one semiconductor module having a plurality of semiconductor devices and a semiconductor module and an external system (not shown). It includes. Such a controller may be formed identically or similarly to a controller for controlling the operation of a plurality of semiconductor modules in a conventional data processing system. Therefore, detailed description thereof will be omitted in the present embodiment. In this case, the semiconductor module illustrated in FIG. 6 may be used as the semiconductor module.
8 is a block diagram illustrating the configuration of an electronic unit and an electronic system according to the present invention.
Referring to the left figure of FIG. 8, an electronic unit according to the present invention includes a processor electrically connected to a semiconductor system. In this case, the semiconductor system is the same as the semiconductor system of FIG. 6. Here, the processor includes a central processing unit (CPU), a micro processor unit (MPU), a micro controller unit (MCU), a graphics processing unit (GPU), and a digital signal processor (DSP).
Here, the CPU or MPU is a combination of an Arithmetic Logic Unit (ALU), which is an arithmetic and logical operation unit, and a control unit (CU) that controls each unit by reading and interpreting an instruction. When the processor is a CPU or MPU, the electronic unit preferably includes a computer device or a mobile device. Also, the GPU is a CPU for graphics, which is used to calculate numbers with decimal points, and is a process for drawing graphics on a real-time screen. If the processor is a GPU, the electronic unit preferably includes a graphics device. In addition, DSP refers to a process of converting an analog signal (for example, voice) into a digital signal after high-speed conversion, using the result, or converting it back to analog. DSP mainly calculates digital values. When the processor is a DSP, the electronic unit preferably includes audio and video equipment.
In addition, the processor includes an accelerator processor unit (APU), which integrates the CPU into the GPU and includes the role of a graphics card.
Referring to the right drawing of FIG. 8, an electronic system includes one or more interfaces electrically connected to an electronic unit. At this time, the electronic unit is the same as the electronic unit of FIG. 8. Here, the interface includes a monitor, keyboard, printer, pointing device (mouse), USB, switch, card reader, keypad, dispenser, telephone, display or speaker. However, the present invention is not limited thereto and may be changed.
As described above, the present invention has an advantage in that the gate is additionally formed under the channel region to increase the gate controllability, prevent the short channel effect, and obtain excellent operating current characteristics.
It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
Claims (11)
Filling a first insulating film in the first recess;
Etching the first insulating film to form a second recess;
Forming a first gate electrode in the second recess;
Embedding a second insulating layer in the etched back region after the first gate electrode is etched back;
Etching the second insulating film and the first gate electrode to form a third recess;
Forming a silicon layer on a surface of the third recess;
Forming a second gate electrode on the silicon layer to be buried in the third recess; And
After the second gate electrode is etched back, a third insulating film is buried in the etched back region
And forming a second insulating film on the semiconductor substrate.
And forming a first gate insulating film between the step of forming the third recess and the step of forming the silicon layer.
And forming a second gate insulating film between the step of forming the silicon layer and the step of forming the second gate electrode.
Before forming the first recess,
Forming a device isolation region defining an active region on the semiconductor substrate.
Forming the second recess is
And etching the first insulating film so that the etched region is surrounded by the first insulating film.
Forming the third recess is
And etching the second insulating film and the first gate electrode, wherein the etched region is surrounded by the second insulating film and the first gate electrode.
The first, second, and third insulating films may include a nitride film or an oxide film.
A first insulating film formed along a surface of the first recess;
A first gate electrode formed along a surface of the first insulating film in the first recess;
A second insulating film provided on the first gate electrode;
A silicon layer formed along a surface of the first gate electrode;
A second gate electrode formed on the silicon layer; And
A third insulating film provided on the second gate electrode
And a semiconductor layer formed on the semiconductor substrate.
And a first gate insulating film provided between the first gate electrode and the silicon layer.
And a second gate insulating film provided between the silicon layer and the second gate electrode.
And the first, second and third insulating films comprise a nitride film or an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120029322A KR20130107491A (en) | 2012-03-22 | 2012-03-22 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120029322A KR20130107491A (en) | 2012-03-22 | 2012-03-22 | Semiconductor device and method for manufacturing the same |
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| Publication Number | Publication Date |
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| KR20130107491A true KR20130107491A (en) | 2013-10-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020120029322A KR20130107491A (en) | 2012-03-22 | 2012-03-22 | Semiconductor device and method for manufacturing the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310982A (en) * | 2019-04-03 | 2019-10-08 | 杭州士兰微电子股份有限公司 | Bilateral power devices and its manufacturing method |
-
2012
- 2012-03-22 KR KR1020120029322A patent/KR20130107491A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310982A (en) * | 2019-04-03 | 2019-10-08 | 杭州士兰微电子股份有限公司 | Bilateral power devices and its manufacturing method |
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