KR20130125135A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof and provides a semiconductor device and a manufacturing method thereof to prevent bridge failure between contact plugs by forming a barrier pattern (nitride layer) between the storage node contact plugs and reduce contact resistance with an active region.

Description

Technical Field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for manufacturing a semiconductor device capable of preventing short defects between contact plugs.

A semiconductor memory device is a device for storing information such as data and instructions of a program. The semiconductor memory device is largely divided into a DRAM and an SRAM. A DRAM is an abbreviation of Dynamic Random Access Memory, which is a memory capable of reading stored information and storing other information. It can read and write information, but it can be periodically Is a memory in which the stored contents disappear unless the information is rewritten. As such, the DRAM needs to keep refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the degree of integration can be increased.

A semiconductor memory device is a device for storing information such as data and instructions of a program. The semiconductor memory device is largely divided into a DRAM and an SRAM. A DRAM is an abbreviation of Dynamic Random Access Memory, which is a memory capable of reading stored information and storing other information. It can read and write information, but it can be periodically Is a memory in which the stored contents disappear unless the information is rewritten. As such, the DRAM needs to keep refreshing, but it is widely used as a large-capacity memory because the price per memory cell is low and the degree of integration can be increased.

As semiconductor devices have been increasingly integrated, semiconductor chip sizes have been reduced, thereby reducing the size of semiconductor devices formed in chips. Particularly, the reduction in the size of the active area and the gate is affecting the process of forming a semiconductor device such as a capacitor and a bit line. Particularly, the area of the storage node and the bit line contact formed in the active region between the gates is gradually reduced to cause a difficulty in forming a contact and a problem of deteriorating electrical characteristics.

In the general memory device, a cell transistor region includes a storage node contact plug connecting a bit line to which a data signal is transferred and a lower electrode of a capacitor that stores data. Here, it is more advantageous to secure the contact area in the wet etching method than the dry etching method used to form the storage node contact plug. However, as the spacing between the storage node contact plugs becomes narrow due to the high integration of semiconductor devices, when the storage node contact plug is formed by using the wet etching method, there is a high probability of a bridge failure between the storage node contact plugs and the wet etching time. If the short adjustment is applied, the area of the storage node contact plug decreases, thereby increasing resistance.

In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device capable of forming a barrier pattern (nitride layer) between storage node contact plugs, preventing bridge failure between contact plugs, and improving contact resistance with active regions. The manufacturing method is provided.

The present invention provides a method of forming an isolation region defining an active region on a semiconductor substrate, forming a first insulating layer over the active region and the isolation region, and etching the first insulating layer and the isolation region. Forming a hole exposing top and side surfaces of the active region, forming a second insulating layer along surfaces of the hole, the first insulating layer, and the device isolation region; etching the second insulating layer to etch the active region Forming a barrier pattern therebetween, forming a bit line contact plug on the active region, forming a bit line on the bit line contact plug and the barrier pattern, and being connected to an upper portion of the active region; Fabricating a semiconductor device comprising forming a storage node contact plug between bit lines Provide a method.

Preferably, the first insulating film may include an oxide film or a nitride film.

Preferably, the barrier pattern is characterized in that it comprises a nitride (Nitride).

Preferably, after the forming of the second insulating layer, a portion of the upper surface and the side surface of the active region is exposed.

Preferably, the barrier pattern is formed at a position higher than the active region.

Preferably, the step of forming the barrier pattern by etching the second insulating film is characterized by using dry etching.

Preferably, the forming of the storage node contact plug may include forming an insulating film on the entire surface including the active region and the bit line, and performing a dip out process to remove the insulating layer and to form the active region. Forming a storage node contact hole exposing the storage node contact hole; and filling a polysilicon or metal material in the storage node contact hole.

Preferably, after the bit line contact plug is formed, the thickness of the barrier pattern may be adjusted by an additional deposition or etching process on the barrier pattern.

The present invention has the advantage of forming a barrier pattern (nitride layer) between the storage node contact plugs to prevent bridge failure between the contact plugs and to improve contact resistance with the active region. In addition, when forming the bit line contact plug, a barrier pattern is formed by a self-aligning method by depositing or etching an insulating layer to further reduce process cost and simplify the process, and wet dip out due to the barrier pattern. It has the advantage of preventing the bridge failure by the process.

1A to 1D are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.
2 is a block diagram illustrating a configuration of a cell array according to the present invention.
3 is a block diagram illustrating a configuration of a semiconductor device according to the present invention.
4 is a block diagram illustrating a configuration of a semiconductor module according to the present invention.
5 is a block diagram illustrating a configuration of a semiconductor system according to the present invention.
6 is a block diagram for explaining the configuration of an electronic unit and an electronic system according to the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

1A to 1D are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 1A, an isolation region 120 defining an active region 110 is formed on a semiconductor substrate 100. The method of forming the device isolation region 120 defining the active region 110 is similar to a general process, and thus description thereof will be omitted.

Next, first insulating layers 130 and 140 are formed on the active region 110 and the device isolation region 120. In this case, the first insulating layers 130 and 140 preferably include an oxide layer or a nitride layer.

Next, the first insulating layers 130 and 140 and the device isolation region 120 are sequentially etched to form holes 150 exposing the top and side surfaces of the active region 110.

Referring to FIG. 1B, a second insulating layer 160 is deposited along the surfaces of the holes 150, the first insulating layers 130 and 140, and the device isolation region 120. Here, the second insulating film 160 preferably includes a nitride film. In addition, even when the second insulating layer 160 is deposited, the top and side surfaces of the active region 110 may still be partially exposed.

Referring to FIG. 1C, a barrier pattern 165 is formed by removing a portion of the second insulating layer 160 provided along the surfaces of the first insulating layers 130 and 140. In this case, the removal process of the second insulating layer 160 is dry etching, and the barrier pattern 165 formed by etching the second insulating layer 160 is preferably formed at a position higher than the active region. Do.

Next, after forming the bit line contact plug 170 connected to the active region 110, the bit line 180 connected to the bit line contact plug 170 is formed. In this case, the manufacturing method of the bit line contact plug 170 and the bit line 180 is similar to the conventional method and will be omitted. Here, after the bit line contact plug is formed, the thickness of the barrier pattern 165 may be freely adjusted by an additional deposition or etching process on the barrier pattern 165. In addition, the bit line 180 may have a line shape, and the bit line 180 may have a structure in which the bit line conductive layer 175 and the hard mask layer 176 are sequentially stacked.

Referring to FIG. 1D, bit line spacers 190 are formed on sidewalls of the bit lines 180. In this case, the bit line spacer 190 preferably includes a nitride film (Nitirde).

Next, an insulating film (not shown) is deposited on the entire surface including the exposed nitride layer 160, the active region 110, the bit line contact plug 170, and the bit line 180, and then the storage node contact plug is formed. After forming a storage node contact hole (not shown) that exposes the active region 110 by performing a dip out process, a polysilicon or metal material is embedded in the storage node contact hole, thereby storing the storage node contact plug 200. To complete).

Here, when the storage node contact plug 200 is formed, the bridge pattern 165 provided between the storage node contact plugs 200 prevents a bridge failure between the storage node contact plugs 200 and the active region 110. The contact resistance with and can be improved.

2 is a block diagram illustrating a configuration of a cell array according to the present invention.

Referring to FIG. 2, a cell array includes a plurality of memory cells, and each memory cell includes one transistor and one capacitor. These memory cells are located at the intersection of the bit lines BL1,... BLn and the word lines WL1..., WLm. The memory cells store or output data based on voltages applied to the bit lines BL1,... BLn and the word lines WL1, .. WLm selected by the column decoder and the row decoder.

As shown, in the cell array, the bit lines BL1,... BLn are formed in the first direction (ie, the bit line direction) in the longitudinal direction, and the word lines WL1... The word line direction) is formed in the longitudinal direction and arranged in a cross shape with each other. The first terminal (eg, drain terminal) of the transistor is connected to the bit lines BL1,..., BLn, the second terminal (eg, source terminal) is connected to the capacitor, and the third terminal ( For example, the gate terminal is connected to the word lines WL1, ..., WLm. A plurality of memory cells including these bit lines BL1 to BLn and word lines WL1 to WLm are positioned in the semiconductor cell array.

3 is a block diagram illustrating a configuration of a semiconductor device according to the present invention.

Referring to FIG. 3, a semiconductor device may include a cell array, a row decoder, a column decoder, and a sense amplifier (SA). The row decoder selects a word line corresponding to a memory cell to perform a read operation or a write operation among word lines of the semiconductor cell array, and outputs a word line selection signal RS to the semiconductor cell array. The column decoder selects a bit line corresponding to a memory cell to perform a read operation or a write operation among the bit lines of the semiconductor cell array, and outputs a bit line selection signal CS to the semiconductor cell array. In addition, the sense amplifiers sense data BDS stored in memory cells selected by the row decoder and the column decoder.

In addition, the semiconductor device may be connected to a microprocessor or a memory controller, and the semiconductor device receives control signals such as WE *, RAS *, and CAS * from the microprocessor, and receives input / output circuits. Receive and store data. The semiconductor device may be applied to DRAM (Random Access Memory), Piram (Random Access Memory), MRAM (Random Access Memory), NAND flash, CMOS Image Sensor (CIS), and the like. In particular, DRAM can be used for desktops, laptops, servers, graphics memory and mobile memory, and NAND flash can be used for portable storage devices such as memory sticks, MMC, SD, CF, xD Picture Card, USB Flash Drive, It can be applied to various digital applications such as MP3, PMP, digital cameras, camcorders, memory cards, USB, game consoles, navigation, laptops, desktop computers and mobile phones.CIS is an imaging device that acts as a kind of electronic film in digital devices. Applicable to camera phones, web cameras, medical medical imaging equipment.

4 is a block diagram illustrating a configuration of a semiconductor module according to the present invention.

Referring to FIG. 4, a semiconductor module includes a plurality of semiconductor devices mounted on a module substrate, and a semiconductor device includes control signals (address signal ADDR, command signal CMD, and clock signal) from an external controller (not shown). CLK)) includes a command link for receiving the data and a data link connected with the semiconductor device to transmit data.

In this case, for example, the semiconductor devices illustrated in the description of FIG. 3 may be used. In addition, the command link and the data link may be formed in the same or similar to those used in a conventional semiconductor module.

In FIG. 4, eight semiconductor devices are mounted on the front surface of the module substrate, but semiconductor devices may be mounted on the rear surface of the module substrate. That is, the semiconductor devices may be mounted on one or both sides of the module substrate, and the number of semiconductor devices to be mounted is not limited to FIG. 4. In addition, the material and structure of the module substrate are not particularly limited.

5 is a block diagram illustrating a configuration of a semiconductor system according to the present invention.

Referring to FIG. 5, a semiconductor system includes a controller for controlling an operation of a semiconductor module by providing a bidirectional interface between at least one semiconductor module having a plurality of semiconductor devices and a semiconductor module and an external system (not shown). It includes. Such a controller may be formed identically or similarly to a controller for controlling the operation of a plurality of semiconductor modules in a conventional data processing system. Therefore, detailed description thereof will be omitted in the present embodiment. In this case, the semiconductor module illustrated in FIG. 4 may be used as the semiconductor module.

6 is a block diagram illustrating the configuration of an electronic unit and an electronic system according to the present invention.

Referring to the left side of FIG. 6, an electronic unit according to the present invention includes a processor electrically connected to a semiconductor system. In this case, the semiconductor system is the same as the semiconductor system of FIG. 5. Here, the processor includes a central processing unit (CPU), a micro processor unit (MPU), a micro controller unit (MCU), a graphics processing unit (GPU), and a digital signal processor (DSP).

Here, the CPU or MPU is a combination of an Arithmetic Logic Unit (ALU), which is an arithmetic and logical operation unit, and a control unit (CU) that controls each unit by reading and interpreting an instruction. When the processor is a CPU or MPU, the electronic unit preferably includes a computer device or a mobile device. Also, the GPU is a CPU for graphics, which is used to calculate numbers with decimal points, and is a process for drawing graphics on a real-time screen. If the processor is a GPU, the electronic unit preferably includes a graphics device. In addition, DSP refers to a process of converting an analog signal (for example, voice) into a digital signal after high-speed conversion, using the result, or converting it back to analog. DSP mainly calculates digital values. When the processor is a DSP, the electronic unit preferably includes audio and video equipment.

In addition, the processor includes an accelerator processor unit (APU), which integrates the CPU into the GPU and includes the role of a graphics card.

Referring to the right diagram of FIG. 6, an electronic system includes one or more interfaces electrically connected to an electronic unit. At this time, the electronic unit is the same as the electronic unit of FIG. 6. Here, the interface includes a monitor, keyboard, printer, pointing device (mouse), USB, switch, card reader, keypad, dispenser, telephone, display or speaker. However, the present invention is not limited thereto and may be changed.

As described above, the present invention has the advantage of forming a barrier pattern (nitride layer) between the storage node contact plugs to prevent bridge failure between the contact plugs and to improve contact resistance with the active region. In addition, when forming the bit line contact plug, a barrier pattern is formed by a self-aligning method by depositing or etching an insulating layer to further reduce process cost and simplify the process, and wet dip out due to the barrier pattern. It has the advantage of preventing the bridge failure by the process.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (8)

Forming an isolation region defining an active region in the semiconductor substrate;
Forming a first insulating layer on the active region and the device isolation region;
Etching the first insulating layer and the device isolation region to form holes exposing top and side surfaces of the active region;
Forming a second insulating film along surfaces of the hole, the first insulating film, and the device isolation region;
Etching the second insulating layer to form a barrier pattern between the active regions;
Forming a bit line contact plug on the active region;
Forming a bit line on the bit line contact plug and the barrier pattern; And
Forming a storage node contact plug connected to an upper portion of the active region and between the bit lines;
And forming a second insulating film on the semiconductor substrate. The method according to claim 1,
And the first insulating film includes an oxide film or a nitride film. The method according to claim 1,
The barrier pattern includes a nitride film (Nitride). The method according to claim 1,
After the forming of the second insulating film,
A part of the upper surface and the side surface of the active region is exposed, characterized in that the manufacturing method. The method according to claim 1,
The barrier pattern is a method of manufacturing a semiconductor device, characterized in that formed in a higher position than the active region. The method according to claim 1,
And etching the second insulating film to form the barrier pattern using dry etching. The method according to claim 1,
Forming the storage node contact plug
Forming an insulating film on an entire surface including between the active region and the bit line;
Performing a dip out process to remove the insulating layer and form a storage node contact hole exposing the active region; And
And embedding polysilicon or a metal material in the storage node contact hole. The method according to claim 1,
After the bit line contact plug is formed,
The method of manufacturing a semiconductor device, characterized in that the thickness of the barrier pattern can be adjusted by an additional deposition or etching process to the barrier pattern.

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