KR20120048283A - Organic light emitting display device - Google Patents

Abstract

PURPOSE: An organic electroluminescent display device is provided to improve display quality by forming an insulating layer of a spacer shape on a bank layer formed between a data line and a cathode electrode and reducing electrostatic capacity of the data line. CONSTITUTION: Sub-pixels are formed on a substrate(110). A data line is formed between the sub-pixels. A line capacitor is composed of a cathode electrode(122) included in the data line and the sub-pixels. A protective film(116) is formed on the data line. A bank layer(120) is formed on the protective film. An insulating layer(125) is formed on the bank layer. The cathode electrode is formed on the insulating layer. The cathode electrode is formed into a spacer type in order to be projected on a region in which the data line is formed.

Description

Organic Light Emitting Display Device

Embodiments of the present invention relate to an organic light emitting display device.

The organic light emitting display device used in the organic light emitting display device is a self-light emitting device having a light emitting layer formed between two electrodes positioned on a substrate. The organic light emitting display includes a top emission type, a bottom emission type, or a dual emission type according to a direction in which light is emitted. In addition, depending on the driving method, it is divided into a passive matrix type and an active matrix type.

The subpixels disposed in the display panel of the organic light emitting display device may include a transistor unit including a switching transistor, a driving transistor, and a capacitor, and an organic light emitting diode including an anode electrode, an organic light emitting layer, and a cathode electrode connected to the driving transistor included in the transistor unit. It includes.

When the scan signal, the data signal, and the power are supplied to the plurality of subpixels arranged in a matrix form, the organic light emitting display device may display an image by emitting light of the selected subpixel.

In the organic light emitting display device, a parasitic capacitor exists between a cathode electrode, a signal line (scan line, a data line), and a power line. Parasitic capacitors cause delays in charging the data voltage between the data line and the cathode and adversely affect display quality. This problem is intensified toward the high-speed driving and large area display panel of the organic light emitting display device. Therefore, improvement of the display quality is required.

Embodiment of the present invention for solving the above problems of the background technology, it is possible to improve the display quality as it is possible to secure the data signal charging time in the high-speed drive and large area display panel by reducing the capacitance of the data line An organic light emitting display device capable of reducing heat generation of a data driver by reducing dynamic power consumption is provided.

Embodiments of the present invention as a means for solving the above problems, the substrate; Subpixels formed on the substrate; A data line formed between the sub pixels; And a line capacitor comprising a cathode electrode included in the data line and the subpixels, wherein the line capacitor includes a data line, a passivation layer formed on the data line, a bank layer formed on the passivation layer, and an insulating layer formed on the bank layer. And a cathode electrode formed on the insulating film, and the thickness of the insulating film is 3 μm to 7 μm.

The insulating layer may be formed in the form of a spacer so that the cathode electrode protrudes on the region where the data line is formed.

The insulating layer may be formed in a barrier rib shape so that the cathode electrode is separated on the region where the data line is formed.

The insulating film may be formed of an organic material or an inorganic material.

The line capacitor may form capacitance in which two capacitors are connected in series by two data lines and a cathode electrode formed under the passivation layer.

The line capacitor may form a capacitance in which two capacitors and one capacitor connected in parallel by one power line and a cathode electrode formed between two data lines and two data lines formed under the passivation layer are connected in series. have.

The data line may include a first data line connected to a first sub pixel positioned at one side and a second data line connected to a second sub pixel positioned at the other side.

The apparatus may further include a power line formed between the first data line and the second data line.

The data line may include a first data line connected to a first sub pixel positioned at one side.

The line capacitor may be formed only in an area corresponding to the circuit part included in the non-emission area of the subpixels.

According to an embodiment of the present invention, it is possible to achieve high-speed driving and secure charging time of a data signal in a large-area display panel by reducing the capacitance of the data line, thereby improving display quality as well as heat generation of the data driver by reducing the dynamic power consumption. There is an effect of providing an organic light emitting display device that can reduce the.

1 is a schematic block diagram of an organic light emitting display device.
FIG. 2 is an exemplary circuit diagram of a subpixel illustrated in FIG. 1. FIG.
3 is a schematic configuration example of a display panel.
4 is an exemplary cross-sectional view of a subpixel.
5 is a cross-sectional view of a line capacitor according to a first embodiment of the present invention.
6 is a photo of an insulating film in the form of a spacer included in a line capacitor.
7 is a cross-sectional view of a line capacitor according to a second embodiment of the present invention.
8 is a cross-sectional view of a line capacitor according to a third embodiment of the present invention.
9 is a cross-sectional view of a line capacitor according to a fourth embodiment of the present invention.
10 is a cross-sectional view of a line capacitor according to a fifth embodiment of the present invention.
11 is a graph showing a change in time constant 5τ according to a change in thickness of an insulating film.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is an exemplary circuit configuration diagram of a subpixel shown in FIG. 1, FIG. 3 is an exemplary configuration diagram of a display panel, and FIG. Is also an example of a cross section.

As shown in FIG. 1, the organic light emitting display device includes a timing driver TCN, a display panel PNL, a power supply unit PWR, a scan driver SDRV, and a data driver DVB.

The timing driver TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, a clock signal CLK, and a data signal RGB from the outside. The timing driver TCN scans the data driver DDRV using timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, and the clock signal CLK. The operation timing of the driver SDRV is controlled. Since the timing driver TCN may determine the frame period by counting the data enable signal DE of one horizontal period, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside may be omitted. The control signals generated by the timing driver TCN include a gate timing control signal GDC for controlling the operation timing of the scan driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDR. ) May be included. The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is supplied to the scan driver SDRV where the first scan signal is generated. The gate shift clock GSC is a clock signal commonly input to the scan driver SDRV, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the scan driver SDRV. The data timing control signal DDC includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), and the like. The source start pulse SSP controls the data sampling start time of the data driver DDRV. The source sampling clock SSC is a clock signal that controls the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV. Meanwhile, the source start pulse SSP supplied to the data driver DVV may be omitted according to the data transmission method.

The scan driver SDRV is a swing width of the gate driving voltage at which the transistors of the subpixels SP included in the display panel PNL can operate in response to the gate timing control signal GDC supplied from the timing driver TCN. Scan signals are sequentially generated while shifting the level of the signals. The scan driver SDRV supplies the scan signals generated through the scan lines SL1 to SLm to the subpixels SP included in the display panel PNL.

The data driver DDRV samples and latches the digital data signal RGB supplied from the timing driver TCN in response to the data timing control signal DDC supplied from the timing driver TCN. Convert to The data driver DVV converts the digital data signal RGB into a gamma reference voltage and converts the data into an analog data signal. The data driver DDRV supplies the data signal converted through the data lines DL1 to DLn to the subpixels SP included in the display panel PNL.

The power supply unit PWR generates a voltage capable of driving the scan driver SDRV, the data driver DDRV, and the subpixel SP, and supplies the generated power through the power lines PL1 to PLk. The power lines PL1 to PLk include a high potential power source and a low potential power source.

The display panel PNL includes a display unit having subpixels SP arranged in a matrix. The subpixels SP may be formed in a passive matrix type or an active matrix type. When the subpixels SP are formed in an active matrix type, they are composed of a 2T (Capacitor) structure including a switching transistor, a driving transistor, a capacitor, and an organic light emitting diode, or a transistor such as 3T1C, 4T1C, 5T2C, or the like. It may also be of a structure in which a capacitor is further added.

The subpixels SP having the above configuration may be formed in a top-emission method, a bottom-emission method, or a dual-emission method according to a structure.

Meanwhile, the subpixels SP having the 2T1C structure may have a structure as illustrated in FIG. 2, which will be described below. In the switching transistor S, a gate electrode is connected to the scan line SL1 to which the scan signal is supplied, one end is connected to the data line DL1 to which the data signal is supplied, and the other end is connected to the first node n1. The driving transistor T has one end connected to the second node n2 connected to the first power line VDD to which the gate electrode is connected to the first node n1 and the high potential power is supplied, and the third node n3 is connected to the first node n1. The other end is connected. One end of the capacitor Cst is connected to the first node n1 and the other end thereof is connected to the third node n3. In the organic light emitting diode D, an anode electrode is connected to the third node n3, and a cathode electrode is connected to the second power line VSS to which a low potential power is supplied.

In the above description, the transistors S and T included in the light emitting part SP are configured as N-types as an example, but embodiments of the present invention are not limited thereto. In addition, the high potential power supplied through the first power line VDD may be higher than the low potential power supplied through the second power line VSS, and the first power line VDD and the second power line V The level of power supplied through VSS) can be switched according to the driving method.

The light emitting unit SP described above may operate as follows. When the scan signal is supplied through the scan line SL1, the switching transistor S is turned on. Next, when the data signal supplied through the data line DL1 is supplied to the first node n1 through the turned-on switching transistor S, the data signal is stored as a data voltage in the capacitor Cst. Next, when the scan signal is blocked and the switching transistor S is turned off, the driving transistor T is driven corresponding to the data voltage stored in the capacitor Cst. Next, when the high potential power supplied through the first power line VDD flows through the second power line VSS, the organic light emitting diode D emits light. However, this is only an example of the driving method, the embodiment of the present invention is not limited thereto.

Some of the devices described above may be formed on the display panel PNL as follows.

As shown in FIGS. 1 and 3, the display panel PNL includes a substrate 110, a pad part PAD, a data driver DDRV, a scan driver SDRV, and a subpixel SP.

The pad part PAD is formed on one outer side of the substrate 110. The pad part PAD is an area connected to the timing driving part TCN and the power supply part PWR positioned outside the substrate 110. The pad part PAD is connected to a printed circuit board on which a timing driver TCN, a power supply part PWR, and the like are formed by a flexible circuit board.

The data driver DDRV is connected to the pad part PAD and mounted on the substrate 110 adjacent to the pad part PAD. The data driver DDRV supplies a data signal through the data lines DL1 to DLn connected to the subpixel SP.

The scan driving units SDRV1 and SDRV2 are connected to the pad unit PAD and are divided on the left and right sides of the substrate 110 to form a GIP (Gate In Panel). The scan drivers SDRV1 and SDRV2 supply scan signals through scan lines SL1 to SLm connected to the subpixel SP.

Sub-pixel SP is formed as shown in FIG.

The buffer layer 111 is formed on the substrate 110. The buffer layer 111 may be formed to protect the thin film transistor formed in a subsequent process from impurities such as alkali ions flowing out of the substrate 110. The buffer layer 111 may use SiOx, SiNx, or the like. The gate electrode 112 is formed on the buffer layer 111.

The gate electrode 112 is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be formed of a single layer or multiple layers of any one or alloys thereof.

The first insulating layer 113 is formed on the gate electrode 112. The first insulating layer 113 may be SiOx, SiNx, or multiple layers thereof, but is not limited thereto.

The active layer 114 is formed on the first insulating layer 113. The active layer 114 may include amorphous silicon or polycrystalline silicon crystallized therefrom. Although not illustrated, the active layer 114 may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with P-type or N-type impurities. In addition, the active layer 114 may include an ohmic contact layer to lower the contact resistance.

The source electrode 115a and the drain electrode 115b are formed on the active layer 114. The source electrode 115a and the drain electrode 115b may be formed of a single layer or multiple layers, and the source electrode 115a and the drain electrode 115b may be formed of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu. It may be made of any one or an alloy thereof selected from the group consisting of.

The second insulating layer 116 is formed on the source electrode 115a and the drain electrode 115b. The second insulating layer 116 may be SiOx, SiNx, or multiple layers thereof, but is not limited thereto. The second insulating film 116 is a protective film.

The third insulating layer 117 is formed on the second insulating layer 116. The third insulating layer 117 may be SiOx, SiNx, or multiple layers thereof, but is not limited thereto. The third insulating film 117 is a planarization film. The above is a description of the transistor unit including the batam gate type driving transistor located on the substrate 110. Hereinafter, the organic light emitting diode on the driving transistor will be described.

An anode electrode 119 is formed on the third insulating film 117. The anode electrode 119 may be made of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

The bank layer 120 having an opening exposing a part of the anode electrode 119 is formed on the anode 119. The bank layer 120 may include organic materials such as benzocyclobutene (BCB) resin, acrylic resin, or polyimide resin, but is not limited thereto.

The organic emission layer 121 is formed in the opening of the bank layer 120. The organic light emitting layer 121 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer. The organic emission layer 121 may further include a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer, as well as other functional layers.

The cathode electrode 122 is formed on the organic emission layer 121. The cathode electrode 122 may be Al, AlNd, or the like, but is not limited thereto.

On the other hand, a line capacitor is formed on the data line formed on the display panel PNL to prevent charge delay of the data signal. The line capacitor is formed on the data line and variously formed as follows.

First Embodiment

FIG. 5 is a cross-sectional view of a line capacitor according to a first embodiment of the present invention, and FIG. 6 is a photo of an insulating film in the form of a spacer included in the line capacitor.

As shown in FIG. 5, the line capacitor Csc according to the first embodiment includes first and second data lines DL1 passing between the neighboring first subpixel SP1 and the second subpixel SP2. , On the entire regions AA and NA of the DL2. Here, the first data line DL1 is a line for supplying a data signal to the first sub pixel SP1 located on the left side, and the second data line DL2 is connected to the second sub pixel SP2 located on the right side. It is a line supplying a data signal. The first power line VDD is formed between the first and second data lines DL1 and DL2.

As such, the display panel PNL has two first and second data lines DL1 and DL2 and one first power line VDD between the first subpixel SP1 and the second subpixel SP2. The formed structure can be taken. Here, the light emitting area AA is a region where the organic light emitting diode is located, and emits light, and the non-light emitting area NA is a region where the circuit portion, such as a driving element, is located.

The line capacitor Csc according to the first embodiment includes a passivation layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the passivation layer 116. ), An insulating film 125 formed on the bank layer 120, and a cathode electrode 122 formed on the insulating film 125. The passivation layer 116 corresponds to the second insulating layer illustrated in FIG. 3, and the flattening layer 117 corresponds to the third insulating layer. Here, the insulating film 125 is formed of an organic or inorganic material.

The line capacitor Csc according to the first embodiment is formed by forming an insulating layer 125 in the form of a spacer on the bank layer 120 formed between the two data lines DL1 and DL2 and the cathode electrode 122 as described above ( The insulating film of 125 increases the thickness of the insulator of the capacitor. It serves to reduce the capacitance formed in the corresponding area. The cathode electrode 122 has a shape protruding from the region where the two data lines DL1 and DL2 are formed by the spacer insulating layer 125. The insulating layer 125 in the form of a spacer refers to the photograph of FIG. 6.

Second Embodiment

7 is a cross-sectional view of a line capacitor according to a second embodiment of the present invention.

As shown in FIG. 7, the line capacitor Csc according to the second embodiment includes the first and second data lines DL1 passing between the neighboring first subpixel SP1 and the second subpixel SP2. , On the entire regions AA and NA of the DL2. Here, the first data line DL1 is a line for supplying a data signal to the first sub pixel SP1 located on the left side, and the second data line DL2 is connected to the second sub pixel SP2 located on the right side. It is a line supplying a data signal. The first power line VDD is formed between the first and second data lines DL1 and DL2.

As such, the display panel PNL has two first and second data lines DL1 and DL2 and one first power line VDD between the first subpixel SP1 and the second subpixel SP2. The formed structure can be taken. Here, the light emitting area AA is a region where the organic light emitting diode is located, and emits light, and the non-light emitting area NA is a region where the circuit portion, such as a driving element, is located.

The line capacitor Csc according to the second embodiment includes a passivation layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the passivation layer 116. ), An insulating film 125 formed on the bank layer 120, and a cathode electrode 122 formed on the insulating film 125. The passivation layer 116 corresponds to the second insulating layer illustrated in FIG. 3, and the flattening layer 117 corresponds to the third insulating layer. Here, the insulating layer 125 may be formed of benzocyclobutene (BCB), acrylic photoresist, phenolic photoresist, imidic photoresist, but is not limited thereto.

The line capacitor Csc according to the second embodiment is partitioned on the bank layer 120 formed between the two data lines DL1 and DL2 and one first power line VDD and the cathode electrode 122 as described above. The formation of the insulating film 125 (the insulating film of 125 increases the thickness of the insulator of the capacitor) serves to reduce the capacitance formed in the corresponding area.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where the two data lines DL1 and DL2 are formed by the barrier layer insulating layer 125. Accordingly, the second cathode electrode 122b is in an electrically floating state with two data lines DL1 and DL2 and one first power line VDD. As a result, the line capacitor Csc is formed by two data lines DL1 and DL2 and one first power line VDD formed under the passivation layer 116 and the second cathode electrode 122b formed thereon. Two capacitors a2 [F] and a3 [F] connected in parallel and one capacitor a1 [F] may form a capacitance connected in series. When two data lines DL1 and DL2 and one first power line VDD are formed below the second cathode electrode 122b as in the second embodiment, the capacitance is 2 / Decreases to 3.

Third Embodiment

8 is a cross-sectional view of a line capacitor according to a third embodiment of the present invention.

As shown in FIG. 8, the line capacitor Csc according to the third embodiment includes first and second data lines DL1 passing between the neighboring first subpixel SP1 and the second subpixel SP2. , On the entire regions AA and NA of the DL2. Here, the first data line DL1 is a line for supplying a data signal to the first sub pixel SP1 located on the left side, and the second data line DL2 is connected to the second sub pixel SP2 located on the right side. It is a line supplying a data signal.

As such, the display panel PNL may have a structure in which two first and second data lines DL1 and DL2 are formed between the first subpixel SP1 and the second subpixel SP2. Here, the light emitting area AA is a region where the organic light emitting diode is located, and emits light, and the non-light emitting area NA is a region where the circuit portion, such as a driving element, is located.

The line capacitor Csc according to the third embodiment includes a passivation layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the passivation layer 116. ), An insulating film 125 formed on the bank layer 120, and a cathode electrode 122 formed on the insulating film 125. The passivation layer 116 corresponds to the second insulating layer illustrated in FIG. 3, and the flattening layer 117 corresponds to the third insulating layer.

The line capacitor Csc according to the third embodiment is formed by forming an insulating film 125 having a barrier rib shape on the bank layer 120 formed between the two data lines DL1 and DL2 and the cathode electrode 122 as described above ( The insulating film of 125 increases the thickness of the insulator of the capacitor. It serves to reduce the capacitance formed in the corresponding area.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where the two data lines DL1 and DL2 are formed by the barrier layer insulating layer 125. As a result, the second cathode electrode 122b is electrically floating with the two data lines DL1 and DL2. As a result, the line capacitor Csc is formed by the two cathodes 122b formed on the two data lines DL1 and DL2 and the two data lines DL1 and DL2 formed under the passivation layer 116. Capacitors a1 [F] and a2 [F] may form capacitance connected in series. When two data lines DL1 and DL2 are formed under the second cathode electrode 122b as in the third embodiment, the capacitance is reduced to 1/2 compared to the first embodiment.

Fourth Embodiment

9 is a cross-sectional view of a line capacitor according to a fourth embodiment of the present invention.

As shown in FIG. 9, the line capacitor Csc according to the fourth embodiment is a part of the first data line DL1 passing between the neighboring first subpixel SP1 and the second subpixel SP2. It is formed only on the circuit portion area NA. Here, the first data line DL1 is a line for supplying a data signal to the first sub pixel SP1 positioned on the left or right side.

As such, the display panel PNL may have a structure in which one first data line DL1 is formed between the first subpixel SP1 and the second subpixel SP2. Here, the light emitting area AA is a region where the organic light emitting diode is located, and emits light, and the non-light emitting area NA is a region where the circuit portion, such as a driving element, is located.

The line capacitor Csc according to the third embodiment includes a passivation layer 116 formed on one first data line DL1 and one first data line DL1 and a bank layer formed on the passivation layer 116. 120, an insulating film 125 formed on the bank layer 120, and a cathode electrode 122 formed on the insulating film 125. The passivation layer 116 corresponds to the second insulating layer illustrated in FIG. 3, and the flattening layer 117 corresponds to the third insulating layer.

The line capacitor Csc according to the third embodiment is formed by forming an insulating film 125 having a barrier rib shape on the bank layer 120 formed between the first data line DL1 and the cathode electrode 122 as described above ( The insulating film of 125 increases the thickness of the insulator of the capacitor. It serves to reduce the capacitance formed in the corresponding area.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region in which one first data line DL1 is formed by the barrier layer insulating layer 125. Accordingly, the second cathode electrode 122b is in an electrically floating state with one first data line DL1. As a result, the line capacitor Csc has a capacitance composed of one capacitor a1 [F] by one first data line DL1 and the second cathode electrode 122b formed under the passivation layer 116. Can be formed. When one first data line DL1 is formed under the second cathode electrode 122b as in the fourth embodiment, the line capacitor Csc does not affect the charging of the data signal.

<Fifth Embodiment>

10 is a cross-sectional view of a line capacitor according to a fifth embodiment of the present invention.

As shown in FIG. 10, the line capacitor Csc according to the fifth embodiment includes the first and second data lines DL1 passing between the neighboring first subpixel SP1 and the second subpixel SP2. , On the entire regions AA and NA of the DL2. Here, the first data line DL1 is a line for supplying a data signal to the first sub pixel SP1 located on the left side, and the second data line DL2 is connected to the second sub pixel SP2 located on the right side. It is a line supplying a data signal. The first power line VDD is formed between the first and second data lines DL1 and DL2.

As such, the display panel PNL has two first and second data lines DL1 and DL2 and one first power line VDD between the first subpixel SP1 and the second subpixel SP2. The formed structure can be taken. Here, the light emitting area AA is a region where the organic light emitting diode is located, and emits light, and the non-light emitting area NA is a region where the circuit portion, such as a driving element, is located.

The line capacitor Csc according to the fifth embodiment includes a passivation layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the passivation layer 116. ), An insulating film 125 formed on the bank layer 120, and a cathode electrode 122 formed on the insulating film 125. The passivation layer 116 corresponds to the second insulating layer illustrated in FIG. 3, and the flattening layer 117 corresponds to the third insulating layer.

The line capacitor Csc according to the fifth embodiment is partitioned on the bank layer 120 formed between the two data lines DL1 and DL2 and one first power line VDD and the cathode electrode 122 as described above. The formation of the insulating film 125 (the insulating film of 125 increases the thickness of the insulator of the capacitor) serves to reduce the capacitance formed in the corresponding area.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where the two data lines DL1 and DL2 are formed by the barrier layer insulating layer 125. Accordingly, the second cathode electrode 122b is in an electrically floating state with two data lines DL1 and DL2 and one first power line VDD. As a result, the line capacitor Csc is formed by two data lines DL1 and DL2 and one first power line VDD formed under the passivation layer 116 and the second cathode electrode 122b formed thereon. As in the second embodiment, two capacitors connected in parallel and one capacitor may form a capacitance connected in series.

In the above-described first to fifth embodiments, the charging time of the data signal varies depending on the capacitance of the line capacitor Csc according to the thickness of the insulating layer 125 formed on the bank layer 120.

Table 1 is a table showing the change of time constant (5τ) according to the thickness change of the insulating film, Figure 11 is a graph showing the change of time constant (5τ) according to the thickness change of the insulating film.

As shown in Table 1 and FIG. 11, when the thickness of the insulating film 125 constituting the line capacitor Csc is 2.3 μm or more, the data load satisfies 3.8 μs, which is 1HT (Horizontal Time) of 55 inch FHD 240Hz ( Data Load). When the thickness of the insulating film 125 is 2.3 占 퐉, the thickness of the insulating film 125 satisfies 3.8 ㎲, but it is preferable to set the charging time of the data signal to 3.5 ㎲ or more in consideration of the process margin and the capacitor charging time margin. Although the insulating film 125 constituting the line capacitor Csc has an advantage that the capacity thereof decreases as the thickness thereof becomes larger, when the thickness thereof becomes 7 μm or more, the shadow of the insulating film 125 by the thick insulating film in the organic material deposition process included in the organic light emitting layer is reduced. ) May cause undeposition. Therefore, the thickness of the insulating film 125 according to the embodiment is preferably formed in the range of 3㎛ ~ 7㎛.

Meanwhile, the present invention compares the simulation results of the structures of the first and third embodiments and the conventional structures of the first to fifth embodiments described above to examine the time constant change due to the reduction of the data line capacitance as follows. do.

Table 2 is a simulation result table showing the change in time constant (5?) Obtained in the conventional structure, the structures of the first and third embodiments under the driving conditions of Full High Definition (FHD) 240 Hz.

As can be seen from Table 2, the conventional structure has a resistance, capacitance, and time constant τ of the data line in the 31-inch FHD and 55-inch FHD conditions, where 5τ is 1.336. ㎲ and 6.339㎲. In Example 1 (structure of FIG. 4), 5τ was 0.830 μs and 3.549 μs as the spacer-type insulating film was formed to a thickness of 3 μm on the 31-inch FHD and 55-inch FHD conditions. In Example 3 (the structure of FIG. 7), 5τ was 0.413 ㎲ and 1.841 따라 as the barrier rib insulating film was formed to a thickness of 3 μm on the data line under the conditions of 31 inch FHD and 55 inch FHD.

According to the above Table 2, it can be seen that Embodiment 1 and Example 3 are advantageous for high-speed driving because 5τ (time constant) is reduced compared to the conventional structure according to the reduction of the capacitance of the data line. Accordingly, the present invention can reduce the capacitance of the data line as described above, thereby enabling high-speed driving and securing the charging time of the data signal in the large-area display panel, thereby improving display quality and reducing dynamic power consumption. Therefore, there is an effect of providing an organic light emitting display device capable of reducing heat generation of the data driver.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

TCN: Timing driver PNL: Display panel
PWR: Power Supply SDRV: Scan Driver
DDRV: Data Drive Csc: Line Capacitor
DL1: first data line DL2: second data line
116: protective film 120: bank layer
125: insulating film 122: cathode electrode

Claims (10)

Board;
Subpixels formed on the substrate;
A data line formed between the sub pixels; And
A line capacitor including the data line and a cathode electrode included in the sub-pixels,
The line capacitor,
The data line, a protective film formed on the data line, a bank layer formed on the protective film, an insulating film formed on the bank layer, and the cathode electrode formed on the insulating film,
The thickness of the insulating film is an organic light emitting display device, characterized in that 3㎛ ~ 7㎛. The method of claim 1,
The insulating film,
And the cathode is formed in the shape of a spacer so as to protrude from the area where the data line is formed. The method of claim 1,
The insulating film,
And the cathode is formed in a barrier rib shape so as to be separated on a region where the data line is formed. The method of claim 1,
The insulating film,
An organic light emitting display device, characterized in that formed of organic or inorganic material. The method according to claim 2 or 3,
The line capacitor,
And a capacitance connected in series by two data lines formed below the passivation layer and the cathode electrode. 2. The method of claim 3,
The line capacitor,
Two capacitors connected in parallel by two power lines and one power line formed between the two data lines and the cathode electrode and one capacitor formed in parallel with each other to form a capacitance connected in series. An organic light emitting display device. The method of claim 1,
The data line,
An organic light emitting display device comprising: a first data line connected to a first sub pixel located at one side and a second data line connected to a second sub pixel located at the other side. The method of claim 7, wherein
And a power line formed between the first data line and the second data line. The method of claim 1,
The data line,
An organic light emitting display device comprising a first data line connected to a first sub pixel positioned at one side. The method of claim 1,
The line capacitor,
An organic light emitting display device, characterized in that formed only in a region corresponding to a circuit unit included in the non-emitting region of the sub-pixels.

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