KR101800885B1 - Organic Light Emitting Display Device - Google Patents

Abstract

An embodiment of the present invention is a substrate processing apparatus comprising: a substrate; Subpixels formed on a substrate; A data line formed between the subpixels; And a line capacitor including a data line and a cathode electrode included in the subpixels, wherein the line capacitor includes a data line, a protective film formed on the data line, a bank layer formed on the protective film, And a cathode electrode formed on the insulating film, and the thickness of the insulating film is 3 占 퐉 to 7 占 퐉.

Description

[0001] The present invention relates to an organic light emitting display device,

An embodiment of the present invention relates to an organic light emitting display.

An organic electroluminescent device used in an organic electroluminescent display device is a self-luminous device in which a light emitting layer is formed between two electrodes located on a substrate. The organic light emitting display device may be a top emission type, a bottom emission type or a dual emission type depending on a direction in which light is emitted. The passive matrix type and the active matrix type are classified according to the driving method.

A subpixel disposed on a display panel of an organic light emitting display device includes a transistor portion including a switching transistor, a driving transistor and a capacitor, an anode electrode connected to a driving transistor included in the transistor portion, an organic light emitting diode .

In the organic light emitting display, when a scan signal, a data signal, a power supply, and the like are supplied to a plurality of subpixels arranged in a matrix form, the selected subpixel emits light, thereby displaying an image.

In the organic electroluminescent display device, a parasitic capacitor exists between a cathode electrode, a signal line (scan line, data line), and a power source line. The parasitic capacitor causes a data voltage charge delay between the data line and the cathode electrode and adversely affects the display quality. Such problems are exacerbated as the organic light emitting display device is driven to a high-speed driving and a large-area display panel, and improvement of the display quality is required to improve the display quality.

The embodiments of the present invention for solving the problems of the background art described above can improve the display quality by enabling high-speed driving by securing the capacitance of the data line and securing the charging time of the data signal in the large-area display panel And an organic light emitting display device capable of reducing heat generation of a data driver by reducing dynamic power consumption.

According to an embodiment of the present invention, there is provided a semiconductor device comprising: a substrate; Subpixels formed on a substrate; A data line formed between the subpixels; And a line capacitor including a data line and a cathode electrode included in the subpixels, wherein the line capacitor includes a data line, a protective film formed on the data line, a bank layer formed on the protective film, And a cathode electrode formed on the insulating film, and the thickness of the insulating film is 3 占 퐉 to 7 占 퐉.

The insulating film may be formed in a spacer shape so that the cathode electrode protrudes from the region where the data line is formed.

The insulating film may be formed in the shape of a barrier so that the cathode electrode is separated on the region where the data line is formed.

The insulating film may be formed of an organic material or an inorganic material.

The line capacitor can form a capacitance in which two capacitors are connected in series by two data lines and a cathode electrode formed at the lower part of the protective film.

The line capacitor can form a capacitance connected in series with two capacitors connected in parallel by a cathode line and a power supply line formed between two data lines and a pair of data lines formed under the protection layer, have.

The data line may include a first data line connected to the first sub pixel located on one side and a second data line connected to the second sub pixel located on the other side.

And a power supply line formed between the first data line and the second data line.

The data line may include a first data line coupled to a first sub-pixel located on one side.

The line capacitor may be formed only in the region corresponding to the circuit portion included in the non-emission region of the subpixels.

The embodiment of the present invention is capable of high-speed driving by securing the capacitance of the data line and securing the charging time of the data signal in the large-area display panel, thereby improving the display quality and reducing the dynamic power consumption, The organic electroluminescent display device according to the present invention can reduce an organic electroluminescent display device.

1 is a schematic block diagram of an organic light emitting display device.
FIG. 2 is a diagram illustrating an exemplary circuit configuration of the subpixel shown in FIG. 1; FIG.
Fig. 3 is a schematic configuration example of a display panel; Fig.
4 is a cross-sectional exemplary view of a subpixel;
5 is a cross-sectional view of a line capacitor according to a first embodiment of the present invention;
6 is a photograph of an insulating film in the form of a spacer included in the line capacitor.
7 is a cross-sectional view of a line capacitor according to a second embodiment of the present invention;
8 is a cross-sectional view of a line capacitor according to a third embodiment of the present invention;
9 is a cross-sectional view of a line capacitor according to a fourth embodiment of the present invention.
10 is a cross-sectional view of a line capacitor according to a fifth embodiment of the present invention;
11 is a graph showing the change of the time constant 5τ according to the change of the thickness of the insulating film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of an organic light emitting display device, FIG. 2 is a diagram illustrating a circuit configuration of the subpixel shown in FIG. 1, FIG. 3 is a schematic configuration diagram of a display panel, Fig.

As shown in FIG. 1, the organic light emitting display includes a timing driver TCN, a display panel PNL, a power supply PWR, a scan driver SDRV, and a data driver DDRV.

The timing driver TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK and a data signal RGB from the outside. The timing driver TCN is connected to the data driver DDRV and the data driver DDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. And controls the operation timing of the driving unit SDRV. The timing driver TCN can count the data enable signal DE in one horizontal period to determine the frame period so that the externally supplied vertical sync signal Vsync and horizontal sync signal Hsync can be omitted. The control signals generated in the timing driver TCN include a gate timing control signal GDC for controlling the operation timing of the scan driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDRV. ) May be included. The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse GSP is supplied to the scan driver SDRV where the first scan signal is generated. The gate shift clock GSC is a clock signal commonly input to the scan driver SDRV, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the scan driver SDRV. The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driver DDRV. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV. On the other hand, the source start pulse SSP supplied to the data driver DDRV may be omitted depending on the data transfer method.

The scan driver SDRV is responsive to the gate timing control signal GDC supplied from the timing driver TCN to turn on the swing width of the gate drive voltage at which the transistors of the subpixels SP included in the display panel PNL are operable And sequentially generates a scan signal while shifting the level of the signal. The scan driver SDRV supplies the scan signals generated through the scan lines SL1 to SLm to the subpixels SP included in the display panel PNL.

The data driver DDRV samples and latches the digital data signal RGB supplied from the timing driver TCN in response to the data timing control signal DDC supplied from the timing driver TCN, . The data driver DDRV converts a digital data signal RGB into a gamma reference voltage and converts the digital data signal into an analog data signal. The data driver DDRV supplies the data signals converted through the data lines DL1 to DLn to the subpixels SP included in the display panel PNL.

The power supply unit PWR generates voltages capable of driving the scan driving unit SDRV, the data driving unit DDRV and the sub pixels SP and supplies power generated through the power supply lines PL1 through PLk. The power supply lines PL1 to PLk include a high potential power supply and a low potential power supply.

The display panel PNL includes a display unit having sub-pixels SP arranged in a matrix form. The subpixels SP may be formed as a passive matrix or an active matrix. When the subpixels SP are formed in an active matrix type, the subpixels SP may be formed of a 2T (Transistor) 1C (Capacitor) structure including a switching transistor, a driving transistor, a capacitor, and an organic light emitting diode, Or a structure in which a capacitor is further added.

The subpixels SP having the above structure may be formed by a top emission method, a bottom emission method, or a dual emission method depending on the structure.

On the other hand, in the case of the sub-pixels SP having the 2T1C structure, the sub-pixels SP may have the structure shown in FIG. The switching transistor S has a gate electrode connected to a scan line SL1 to which a scan signal is supplied, one end connected to a data line DL1 to which a data signal is supplied, and the other end connected to the first node n1. The driving transistor T is connected at one end to a second node n2 connected to a first power supply line VDD to which a gate electrode is connected and a high potential power is supplied to the first node n1, The other end is connected. One end of the capacitor Cst is connected to the first node n1 and the other end is connected to the third node n3. In the organic light emitting diode D, a cathode electrode is connected to the second power supply line VSS to which the anode electrode is connected to the third node n3 and the low potential power is supplied.

In the above description, the transistors S and T included in the light emitting unit SP are N-type, but the embodiment of the present invention is not limited thereto. The high potential power supplied through the first power line VDD may be higher than the low potential power supplied through the second power line VSS and may be higher than the first power line VDD and the second power line VSS) can be switched according to the driving method.

The above-described light emitting unit SP can operate as follows. When the scan signal is supplied through the scan line SL1, the switching transistor S is turned on. Next, when the data signal supplied through the data line DL1 is supplied to the first node n1 through the turned-on switching transistor S, the data signal is stored as a data voltage in the capacitor Cst. Next, when the scan signal is cut off and the switching transistor S is turned off, the driving transistor T is driven in response to the data voltage stored in the capacitor Cst. Next, when the high potential power supplied through the first power line VDD flows through the second power line VSS, the organic light emitting diode D emits light. However, this is only an example of the driving method, and the embodiment of the present invention is not limited thereto.

Some of the above-described devices may be formed on the display panel PNL as follows.

As shown in FIGS. 1 and 3, the display panel PNL includes a substrate 110, a pad portion PAD, a data driver DDRV, a scan driver SDRV, and a subpixel SP.

The pad portion PAD is formed on one side of the substrate 110. The pad portion PAD is an area connected to the timing driving portion TCN and the power supply portion PWR located outside the substrate 110. The pad unit PAD is connected to a printed circuit board on which a timing driving unit TCN and a power supply unit PWR are formed by a flexible circuit board or the like.

The data driver DDRV is connected to the pad unit PAD and mounted on the substrate 110 adjacent to the pad unit PAD. The data driver DDRV supplies the data signals through the data lines DL1 to DLn connected to the sub-pixels SP.

The scan drivers SDRV1 and SDRV2 are connected to the pad unit PAD and are formed on the left and right sides of the substrate 110 in a GIP (Gate In Panel) form. The scan drivers SDRV1 and SDRV2 supply the scan signals through the scan lines SL1 to SLm connected to the sub-pixels SP.

The subpixel SP is formed as shown in FIG.

A buffer layer 111 is formed on the substrate 110. The buffer layer 111 may be formed to protect a thin film transistor formed in a subsequent process from an impurity such as an alkali ion or the like flowing out from the substrate 110. The buffer layer 111 may be made of SiOx, SiNx, or the like. A gate electrode 112 is formed on the buffer layer 111.

The gate electrode 112 is formed of a material selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper And may be formed of a single layer or a multilayer composed of any one or an alloy thereof.

A first insulating layer 113 is formed on the gate electrode 112. The first insulating layer 113 may be SiOx, SiNx, or a multilayer thereof, but is not limited thereto.

An active layer 114 is formed on the first insulating film 113. The active layer 114 may comprise amorphous silicon or polycrystalline silicon crystallized therefrom. Although not shown here, the active layer 114 may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with P-type or N-type impurities. In addition, the active layer 114 may include an ohmic contact layer for lowering the contact resistance.

On the active layer 114, a source electrode 115a and a drain electrode 115b are formed. The source electrode 115a and the drain electrode 115b may be formed of a single layer or multiple layers and the source electrode 115a and the drain electrode 115b may be formed of Mo, Al, Cr, Au, Ti, Ni, Or an alloy thereof.

A second insulating film 116 is formed on the source electrode 115a and the drain electrode 115b. The second insulating layer 116 may be SiOx, SiNx, or a multilayer thereof, but is not limited thereto. The second insulating film 116 is a protective film.

A third insulating film 117 is formed on the second insulating film 116. The third insulating film 117 may be SiOx, SiNx, or a multilayer thereof, but is not limited thereto. The third insulating film 117 is a planarizing film. The above is a description of a transistor portion including a totem gate type driving transistor located on the substrate 110. [ Hereinafter, the organic light emitting diode positioned on the driving transistor will be described.

An anode electrode 119 is formed on the third insulating film 117. The anode electrode 119 may be formed of a transparent material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

On the anode electrode 119, a bank layer 120 having an opening exposing a part of the anode electrode 119 is formed. The bank layer 120 may include organic materials such as benzocyclobutene (BCB) resin, acrylic resin or polyimide resin, but is not limited thereto.

An organic light emitting layer 121 is formed in the opening of the bank layer 120. The organic light emitting layer 121 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. The organic light emitting layer 121 may further include a hole injecting layer, a hole transporting layer, an electron transporting layer, and an electron injecting layer, as well as other functional layers.

A cathode electrode 122 is formed on the organic light emitting layer 121. The cathode electrode 122 may be made of Al, AlNd, or the like, but is not limited thereto.

On the other hand, a line capacitor is formed on the data line formed on the display panel PNL to prevent a delay in charging the data signal. The line capacitors are formed on the data lines and formed in various ways as follows.

≪ Embodiment 1 >

FIG. 5 is a cross-sectional view of a line capacitor according to the first embodiment of the present invention, and FIG. 6 is a photograph of an insulating film in the form of a spacer included in the line capacitor.

5, the line capacitor Csc according to the first embodiment includes first and second data lines DL1 and DL2 passing between neighboring first and second subpixels SP1 and SP2, , DL2 of the first and second regions A, Here, the first data line DL1 is a line for supplying a data signal to the first sub-pixel SP1 positioned on the left and the second data line DL2 is a line for supplying a data signal to the second sub- And is a line for supplying a data signal. A first power supply line VDD is formed between the first and second data lines DL1 and DL2.

The display panel PNL thus has two first and second data lines DL1 and DL2 and one first power line VDD between the first and second subpixels SP1 and SP2 The formed structure can be obtained. Here, the light emitting area AA is a region where light is emitted as an area where the organic light emitting diode is located, and the non-light emitting area NA is a region where a circuit part such as a driving element is located.

The line capacitor Csc according to the first embodiment includes the protective layer 116 formed on the two data lines DL1 and DL2 and the two data lines DL1 and DL2 and the bank layer 120 An insulating film 125 formed on the bank layer 120 and a cathode electrode 122 formed on the insulating film 125. [ The protective film 116 corresponds to the second insulating film shown in Fig. 3, and the flat film 117 corresponds to the third insulating film. Here, the insulating film 125 is formed of an organic material or an inorganic material.

The line capacitor Csc according to the first embodiment is formed by forming the insulating film 125 in the form of a spacer on the bank layer 120 formed between the two data lines DL1 and DL2 and the cathode electrode 122 125 insulating film increases the thickness of the insulator of the capacitor) and serves to reduce the capacitance formed in the area. The cathode electrode 122 has a protruding shape on an area where the two data lines DL1 and DL2 are formed by the insulating film 125 of the spacer type. The spacer-type insulating film 125 refers to the picture of FIG.

≪ Embodiment 2 >

7 is a cross-sectional view of a line capacitor according to a second embodiment of the present invention.

7, the line capacitor Csc according to the second embodiment includes first and second data lines DL1 and DL2 passing between neighboring first and second subpixels SP1 and SP2, , DL2 of the first and second regions A, Here, the first data line DL1 is a line for supplying a data signal to the first sub-pixel SP1 positioned on the left and the second data line DL2 is a line for supplying a data signal to the second sub- And is a line for supplying a data signal. A first power supply line VDD is formed between the first and second data lines DL1 and DL2.

The display panel PNL thus has two first and second data lines DL1 and DL2 and one first power line VDD between the first and second subpixels SP1 and SP2 The formed structure can be obtained. Here, the light emitting area AA is a region where light is emitted as an area where the organic light emitting diode is located, and the non-light emitting area NA is a region where a circuit part such as a driving element is located.

The line capacitor Csc according to the second embodiment includes a protective layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the protective layer 116 An insulating film 125 formed on the bank layer 120 and a cathode electrode 122 formed on the insulating film 125. [ The protective film 116 corresponds to the second insulating film shown in Fig. 3, and the flat film 117 corresponds to the third insulating film. Here, the insulating layer 125 may be formed of benzocyclobutene (BCB), acrylic photoresist, phenolic photoresist, imidic photoresist, or the like, but is not limited thereto.

The line capacitor Csc according to the second embodiment is formed on the bank layer 120 formed between the two data lines DL1 and DL2 and one first power line VDD and the cathode electrode 122, Type insulating layer 125 (the insulating layer 125 increases the thickness of the insulating layer of the capacitor), thereby reducing the capacitance formed in the corresponding region.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where the two data lines DL1 and DL2 are formed. Accordingly, the second cathode electrode 122b is electrically floating with the two data lines DL1 and DL2 and one first power line VDD. The line capacitor Csc is formed by the two data lines DL1 and DL2 and the first power source line VDD formed below the protective film 116 and the second cathode electrode 122b formed thereon Two capacitors a2 [F] and a3 [F] connected in parallel and one capacitor a1 [F] can form a capacitance connected in series. When two data lines DL1 and DL2 and one first power source line VDD are formed under the second cathode electrode 122b as in the second embodiment, 3.

≪ Third Embodiment >

8 is a cross-sectional view of a line capacitor according to a third embodiment of the present invention.

8, the line capacitor Csc according to the third embodiment includes first and second data lines DL1 and DL2 passing between neighboring first and second subpixels SP1 and SP2, , DL2 of the first and second regions A, Here, the first data line DL1 is a line for supplying a data signal to the first sub-pixel SP1 positioned on the left and the second data line DL2 is a line for supplying a data signal to the second sub- And is a line for supplying a data signal.

The display panel PNL may have a structure in which two first and second data lines DL1 and DL2 are formed between the first subpixel SP1 and the second subpixel SP2. Here, the light emitting area AA is a region where light is emitted as an area where the organic light emitting diode is located, and the non-light emitting area NA is a region where a circuit part such as a driving element is located.

The line capacitor Csc according to the third embodiment includes a protective layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the protective layer 116 An insulating film 125 formed on the bank layer 120 and a cathode electrode 122 formed on the insulating film 125. [ The protective film 116 corresponds to the second insulating film shown in Fig. 3, and the flat film 117 corresponds to the third insulating film.

The line capacitor Csc according to the third embodiment is formed by forming the insulating layer 125 in the form of a barrier rib on the bank layer 120 formed between the two data lines DL1 and DL2 and the cathode electrode 122 125 insulating film increases the thickness of the insulator of the capacitor) and serves to reduce the capacitance formed in the area.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where the two data lines DL1 and DL2 are formed. Accordingly, the second cathode electrode 122b is electrically floating with the two data lines DL1 and DL2. The line capacitor Csc is formed by two data lines DL1 and DL2 formed under the protective film 116 and a second cathode electrode 122b formed on the two data lines DL1 and DL2, Capacitors a1 [F], a2 [F] can form a capacitance connected in series. When the two data lines DL1 and DL2 are formed under the second cathode electrode 122b as in the third embodiment, the electrostatic capacitance is reduced to 1/2 of that of the first embodiment.

<Fourth Embodiment>

9 is a cross-sectional view of a line capacitor according to a fourth embodiment of the present invention.

9, the line capacitor Csc according to the fourth embodiment is a part of the first data line DL1 passing between neighboring first and second subpixels SP1 and SP2 And is formed only on the circuit portion area NA. Here, the first data line DL1 is a line for supplying a data signal to the first sub-pixel SP1 located on the left or right side.

The display panel PNL may have a structure in which one first data line DL1 is formed between the first sub-pixel SP1 and the second sub-pixel SP2. Here, the light emitting area AA is a region where light is emitted as an area where the organic light emitting diode is located, and the non-light emitting area NA is a region where a circuit part such as a driving element is located.

The line capacitor Csc according to the fourth embodiment includes a protective film 116 formed on one first data line DL1 and one first data line DL1 and a bank layer An insulating film 125 formed on the bank layer 120 and a cathode electrode 122 formed on the insulating film 125. The insulating layer 125 is formed on the insulating layer 125, The protective film 116 corresponds to the second insulating film shown in Fig. 3, and the flat film 117 corresponds to the third insulating film.

The line capacitor Csc according to the fourth embodiment is formed by forming the insulating layer 125 in the form of a barrier rib on the bank layer 120 formed between one first data line DL1 and the cathode electrode 122 125 insulating film increases the thickness of the insulator of the capacitor) and serves to reduce the capacitance formed in the area.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where one first data line DL1 is formed. Thus, the second cathode electrode 122b is electrically floating with one of the first data lines DL1. The line capacitor Csc has a capacitance composed of one capacitor a1 [F] by one first data line DL1 and a second cathode electrode 122b formed under the protective film 116 . When one first data line DL1 is formed below the second cathode electrode 122b as in the fourth embodiment, the line capacitor Csc does not affect the charging of the data signal.

<Fifth Embodiment>

10 is a cross-sectional view of a line capacitor according to a fifth embodiment of the present invention.

10, the line capacitor Csc according to the fifth embodiment includes first and second data lines DL1 and DL2 passing between neighboring first and second subpixels SP1 and SP2, , DL2, which are part of the circuit portion area NA. Here, the first data line DL1 is a line for supplying a data signal to the first sub-pixel SP1 positioned on the left and the second data line DL2 is a line for supplying a data signal to the second sub- And is a line for supplying a data signal. A first power supply line VDD is formed between the first and second data lines DL1 and DL2.

The display panel PNL thus has two first and second data lines DL1 and DL2 and one first power line VDD between the first and second subpixels SP1 and SP2 The formed structure can be obtained. Here, the light emitting area AA is a region where light is emitted as an area where the organic light emitting diode is located, and the non-light emitting area NA is a region where a circuit part such as a driving element is located.

The line capacitor Csc according to the fifth embodiment includes a protective layer 116 formed on two data lines DL1 and DL2 and two data lines DL1 and DL2 and a bank layer 120 formed on the protective layer 116 An insulating film 125 formed on the bank layer 120 and a cathode electrode 122 formed on the insulating film 125. [ The protective film 116 corresponds to the second insulating film shown in Fig. 3, and the flat film 117 corresponds to the third insulating film.

The line capacitor Csc according to the fifth embodiment is formed on the bank layer 120 formed between the two data lines DL1 and DL2 and one first power line VDD and the cathode electrode 122, Type insulating layer 125 (the insulating layer 125 increases the thickness of the insulating layer of the capacitor), thereby reducing the capacitance formed in the corresponding region.

The cathode electrode 122 is separated into the first to third cathode electrodes 122a to 122c on the region where the two data lines DL1 and DL2 are formed. Thus, the second cathode electrode 122b is electrically floating with the two data lines DL1 and DL2 and one first power source line VDD. The line capacitor Csc is formed by the two data lines DL1 and DL2 and the first power source line VDD formed below the protective film 116 and the second cathode electrode 122b formed thereon Two capacitors connected in parallel and one capacitor may be connected in series to form a capacitance, as in the second embodiment.

In the first to fifth embodiments described above, the charging time of the data signal varies depending on the capacitance of the line capacitor Csc depending on the thickness of the insulating film 125 formed on the bank layer 120. [

Table 1 shows the change of the time constant 5τ according to the thickness change of the insulating film, and FIG. 11 is a graph showing the change of the time constant 5τ according to the change of the thickness of the insulating film.

As shown in Table 1 and FIG. 11, when the thickness of the insulating film 125 constituting the line capacitor Csc becomes 2.3 탆 or more, the data load satisfying 3.8 占 퐏, which is 1HT (Horizontal Time) of 55 inches FHD 240 Hz Data Load). When the thickness of the insulating film 125 is 2.3 占 퐉, it is preferable that the charging time of the data signal is set to 3.5 占 퐏 or more in consideration of the process margin and the capacitor charging time margin. The thickness of the insulating film 125 constituting the line capacitor Csc is advantageously reduced as the thickness thereof increases. However, when the thickness of the insulating film 125 is 7 mu m or more, a shadow caused by a thick insulating film ) Phenomenon may result in non-deposition. Therefore, it is preferable that the thickness of the insulating film 125 according to the embodiment is formed in the range of 3 탆 to 7 탆.

In order to examine the change of the time constant due to the decrease of the capacitance of the data line in the present invention, the simulation results of the structures of the first and third embodiments and the conventional structure of the first to fifth embodiments described above are compared do.

Table 2 is a simulation result table showing the change of the time constant (5?) Obtained in the conventional structure, the structures of the first and third embodiments under the driving condition of FHD (Full High Definition) 240 Hz.

As can be seen from the above Table 2, when the resistance, capacitance, and time constant (τ) of the data line in the 31-inch FHD and 55-inch FHD conditions are as shown above, 5τ is 1.336 Mu s and 6.339 mu s. The structure of Example 1 (the structure of FIG. 4) showed 5τ of 0.830 μs and 3.549 μs, respectively, as the insulating film in the form of a spacer was formed to a thickness of 3 μm on the data lines under the conditions of 31 inches FHD and 55 inches FHD. In Example 3 (the structure of FIG. 7), 5τ was 0.413 μs and 1.841 μs, respectively, as the insulating film in the form of a partition wall was formed to a thickness of 3 μm on the data line under the conditions of 31 inches FHD and 55 inches FHD.

According to the above Table 2, it can be seen that Embodiment 1 and Embodiment 3 are advantageous for high-speed driving because 5τ (time constant) is reduced as compared with the conventional structure in accordance with the decrease in capacitance of the data line. Therefore, since the capacitance of the data line can be reduced as described above, it is possible to secure the data signal charging time in the high-speed driving and the large area display panel, thereby improving the display quality and reducing the dynamic power consumption An organic electroluminescent display device capable of reducing the heat generation of the data driver.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: timing driver PNL: display panel
PWR: power supply unit SDRV: scan driver
DDRV: Data driver Csc: Line capacitor
DL1: first data line DL2: second data line
116: protective film 120: bank layer
125: insulating film 122: cathode electrode

Claims (10)

delete delete delete delete delete Board;
Subpixels formed on the substrate;
A data line formed between the subpixels; And
And a line capacitor including a data line, a protective film formed on the data line, a bank layer formed on the protective film, an insulating film formed on the bank layer, and a cathode electrode on the insulating film,
The insulating film is formed in the form of a spacer projecting on the data line region,
The line capacitor includes:
Two data lines, one power supply line formed between the two data lines, two capacitors connected in parallel by the cathode electrode and one capacitor are connected in series to form a capacitance,
Wherein the insulating film has a thickness of 3 占 퐉 to 7 占 퐉. The method according to claim 6,
Wherein the data line includes:
And a second data line connected to a first sub-pixel connected to the first sub-pixel located at one side and a second sub-pixel located at the other side. delete delete The method according to claim 6,
The line capacitor includes:
Emitting regions of the sub-pixels.

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