KR20120008863A - Mathod of manufacturing in thin film transistor array substrate - Google Patents

Abstract

PURPOSE: A manufacturing method of a thin film transistor is provided to reduce manufacturing costs by simplifying a manufacturing process. CONSTITUTION: A manufacturing method of a thin film transistor performs a first mask process for forming a gate electrode(12a), a gate line, and a gate pad(12c). A gate insulating layer(14) is formed on the substrate. A source and drain electrodes, a semiconductor pattern, a data line, and a data pad are formed on the substrate in a second mask process. A pixel electrode is formed on the substrate in a third mask process. The protective film is formed on the substrate. A contact hole for gate pad is formed on the substrate in a fourth mask process.

Description

Manufacturing method of thin film transistor array substrate

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor array substrate used in a liquid crystal display device.

Recently, transverse electric field type liquid crystal displays have been developed in which electrodes are alternately disposed on one of upper and lower substrates, and liquid crystals are disposed between the substrates to display an image.

In general, a transverse electric field type liquid crystal display device displays an image by adjusting a light transmittance of a liquid crystal having dielectric anisotropy using an electric field, and a color filter substrate on which a color filter array is formed and a thin film transistor substrate on which a thin film transistor array is formed are used. It is formed by being put together in between.

The thin film transistor array substrate includes a thin film transistor, a pixel electrode, and a common electrode formed in each cell region defined by an intersection of a gate line and a data line on the substrate. A thin film transistor (hereinafter referred to as TFT) supplies a data signal from the data line to the pixel electrode in response to the gate signal from the gate line. The pixel electrode supplies a data signal from the TFT to drive the liquid crystal, and the common electrode is supplied with a common voltage which is a reference for driving the liquid crystal. The liquid crystal is rotated according to the electric field formed by the data signal of the pixel electrode and the common voltage of the common electrode, thereby adjusting grayscale.

The thin film transistor array substrate of the transverse electric field liquid crystal display device is formed through a plurality of mask processes. One mask process includes a plurality of processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a strip process, an inspection process, and the like.

However, as a number of mask processes are required, the manufacturing process is complicated, which is a major reason for the increase in manufacturing cost of the liquid crystal panel. As a result, a six-mask process for reducing the mask process by using a diffraction exposure mask is on the thin film transistor array substrate of the transverse electric field liquid crystal display device.

However, the six mask process also has a limitation in cost reduction because the manufacturing process is complicated, there is a need for a method to further simplify the manufacturing process to further reduce the manufacturing cost.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor array substrate, which can further simplify the manufacturing process and further reduce manufacturing costs.

A method of manufacturing a thin film transistor substrate according to the present invention for achieving the above object comprises the steps of forming a gate electrode, a gate line and a gate pad by performing a first mask process, forming a gate insulating film on the substrate; Performing a second mask process to form source and drain electrodes, semiconductor patterns, data lines, and data pads on the substrate; and performing a third mask process to form pixel electrodes and buffer films on the substrate. And forming a passivation layer on the substrate, performing a fourth mask process to form a gate pad contact hole and a data pad contact hole on the substrate, and performing a fifth mask process. Forming an electrode, an electrode for a data pad, and an electrode for a gate pad.

The method of claim 1, wherein the forming of the pixel electrode and the buffer film on the substrate by performing the third mask process comprises forming a transparent metal film on the substrate on which the source and drain electrodes, the semiconductor pattern, the data line, and the data pad are formed. And forming a photoresist pattern through the photolithography process using the third mask after forming the photoresist on the transparent metal film, and etching the transparent metal film using the photoresist pattern as an etching mask. Forming a pixel electrode and a buffer layer, and removing the photoresist pattern through a strip process using an O ₂ plasma.

The buffer layer is the O ₂ It is an anti-oxidation film of the data pad during the strip process using plasma.

The second mask uses a mask having three different transmittances.

According to the present invention, by manufacturing a thin film transistor array substrate using five masks, it is possible to obtain an effect of reducing process steps.

In the method for manufacturing a thin film transistor substrate according to the present invention, a buffer layer is formed on the data pad during the pixel electrode forming process, and thus the data pad is oxidized due to the O ₂ plasma used during the stripping process of the photoresist pattern for forming the pixel electrode. There is an effect that can be prevented, and to prevent a bad contact with the data pad electrode to be formed later.

1A and 1B to 5A and 5B are process flowcharts illustrating a method of manufacturing a thin film transistor array substrate of a liquid crystal display according to the present invention.
6A through 6C are process flowcharts for describing a third mask process of the present invention.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1A and 1B to 5A and 5B are flowcharts illustrating a method of manufacturing a thin film transistor array substrate of a liquid crystal display according to the present invention.

First, as shown in FIGS. 1A and 1B, a gate electrode 12a, a gate line 12b, and a gate pad 12c are formed on a substrate 10 by performing a first mask process.

The gate electrode 12a, the gate line 12b, and the gate pad 12c sequentially form a first metal layer and a photoresist on the substrate 10, and perform a photo process using the first mask on the photoresist. To form a first photoresist pattern (not shown), which is then etched into the metal film using an etching mask.

Subsequently, as illustrated in FIGS. 2A and 2B, a gate insulating layer 14 is formed on the substrate 10 on which the gate electrode 12a, the gate line 12b, and the gate pad 12c are formed, and a second mask is formed. The process may be performed to form source / drain electrodes 18g and 18f, semiconductor patterns 16f, data lines 18d and 16d, and data pads 18e and 16e on the gate insulating layer 14.

At this time, each of the data lines 18d and 16d and the data pads 18e and 16e is formed by stacking a metal for a source / drain electrode and a metal for a semiconductor pattern.

Next, a process of forming the source / drain electrodes 18g and 18f, the semiconductor pattern 16f, the data lines 18d and 16d, and the data pads 18e and 16e using the photo process using the second mask will be described in detail. .

First, a semiconductor layer and a second metal layer are sequentially formed on the substrate 10 on which the gate insulating layer 14 is formed, and then a second photoresist pattern is formed.

The second photoresist pattern is formed by a photoresist using a second mask after forming a photoresist on the second metal layer. In this case, the mask uses a mask having three different transmittances, including a transmissive region for transmitting light, a transflective region for transmitting a portion of light and blocking a portion of the light, and a blocking region for blocking light.

Subsequently, the semiconductor layer and the second metal layer are etched using the second photoresist pattern as an etching mask, and the TFT pattern, the data lines 18d and 16d and the data pads 18e and 16e are respectively formed on the gate insulating layer 14. Form.

Next, a third photoresist pattern is formed on the substrate 10 on which the TFT pattern, the data lines 18d and 16d, and the data pads 18e and 16e are formed.

The third photoresist pattern is formed by performing an ashing process on the second photoresist pattern to remove a part of the thickness of the second photoresist pattern, and in the region where the channel of the thin film transistor is formed by forming the third photoresist pattern. All photoresist of is removed, exposing the uppermost layer of this area, ie, the second metal layer.

Subsequently, the third photoresist pattern is etched using an etching mask to remove portions of the second metal layer and the semiconductor layer corresponding to the region where the channel of the thin film transistor is formed in the TFT pattern, thereby removing the source / drain electrodes 18g and 18f, and The semiconductor pattern 16f is formed.

In this case, the semiconductor layer is formed of an amorphous silicon layer and an n + amorphous silicon layer. In the process of patterning a part of the semiconductor layer, only the n + amorphous silicon layer is removed and the amorphous silicon layer remains.

Subsequently, the third photoresist pattern is removed through the stripping process to form the source / drain electrodes 18g and 18f, the semiconductor pattern 16f, the data lines 18d and 16d, and the data pads 18e and 16e. To complete.

3A and 3B, the substrate 10 on which the source / drain electrodes 18g and 18f, the semiconductor pattern 16f, the data lines 18d and 16d, and the data pads 18e and 16e are formed. The pixel electrode 20a and the buffer films 20b and 20c are formed by performing a third mask process on the substrate.

At this time, the buffer film 20c is formed to prevent the exposed data pad 18e from being oxidized due to the O ₂ plasma of the strip process to cause a poor contact with the data pad electrode 26b to be formed later. to be.

Next, a process of forming the pixel electrode 20a and the buffer films 20b and 20c using the photo process using the third mask will be described in more detail with reference to FIGS. 6A to 6C.

As shown in FIG. 6A, a third metal layer on the substrate 10 on which the source / drain electrodes 18g and 18f, the semiconductor pattern 16f, the data lines 18d and 16d, and the data pads 18e and 16e are formed. Next, the photoresist is formed on the third metal layer 20, and then the fourth photoresist pattern 100 is formed through a photolithography process using a third mask. Meanwhile, the third metal film 20 is formed of a transparent metal film such as ITO, IZO, or the like.

As illustrated in FIG. 6B, the third metal layer 20 is wet etched using the fourth photoresist pattern 100 as an etch mask to form the pixel electrodes 20a and the buffer layers 20b and 20c.

As illustrated in FIG. 6C, the fourth photoresist pattern 100 is removed through the strip process, thereby completing the process of forming the pixel electrodes 20a and the buffer films 20b and 20c.

The strip process is performed using an O 2 plasma.

At this time, the buffer film 20c is used to prevent poor contact with the data pad electrode (26b of FIGS. 5A and 5B) to be formed after the exposed data pad 18e is oxidized due to the O ₂ plasma of the strip process. It is a film formed. The buffer film 20c formed of a transparent metal film such as ITO, IZO, or the like does not react well to an oxidation process generated by the O ₂ plasma of the strip process, thereby preventing the data pad from being oxidized and then forming. Contact failure with the data pad electrode to be prevented can be prevented.

As described above, in the pixel electrode 20a forming process, the buffer film 20c is formed on the data pad 18e, thereby forming the O ₂ used during the stripping process of the photoresist pattern for forming the pixel electrode. It is possible to prevent the data pad from being oxidized by the plasma and to prevent a bad contact with the data pad electrode formed thereafter.

Next, as shown in FIGS. 4A and 4B, the passivation layer 22 is formed on the substrate 10 on which the pixel electrodes 20a and the buffer layers 20b and 20c are formed, and a fourth mask process is performed to perform a gate. A pad contact hole 24a and a data pad contact hole 24b are formed.

The gate pad contact hole 24a is formed by removing the passivation layer 22 and the gate insulating layer 14 to expose the gate pad 12c, and the data pad contact hole 24b is in contact with the data pad 12c. The protective film 22 is removed to expose the buffer film 20c.

The gate pad contact hole 24a and the data pad contact hole 24b form a photoresist on the substrate 10 on which the passivation layer 22 is formed, and then the fifth photoresist through a photo process using a fourth mask. A pattern (not shown) is formed, and the protective film 22 is etched using the fifth photoresist pattern (not shown) as an etching mask.

Next, as illustrated in FIGS. 5A and 5B, a common mask 26a is performed by performing a fifth mask process on the substrate 10 on which the gate pad contact hole 24a and the data pad contact hole 24b are formed. ), The data pad electrode 26b and the gate pad electrode 26c are formed, thereby completing this step.

The common electrode 26a, the data pad electrode 26b, and the gate pad electrode 26c form a fourth metal layer on the substrate 10, a photoresist on the fourth metal layer, and then use a third mask. The fourth photoresist pattern is formed through the photolithography, and the fourth metal film is etched using the sixth photoresist pattern as an etching mask.

As described above, in the process of forming the pixel electrode 20a, the buffer film 20c is formed on the data pad 18e, thereby oxidizing the data pad due to the O 2 plasma used in the strip process of the photoresist pattern for forming the pixel electrode. It is possible to prevent the contact failure with the electrode for the data pad to be formed later.

Claims (4)

Performing a first mask process to form a gate electrode, a gate line, and a gate pad;
Forming a gate insulating film on the substrate;
Performing a second mask process to form source and drain electrodes, semiconductor patterns, data lines, and data pads on the substrate;
Forming a pixel electrode and a buffer film on the substrate by performing a third mask process;
Forming a protective film on the substrate;
Forming a gate pad contact hole and a data pad contact hole on the substrate by performing a fourth mask process;
And forming a common electrode, a data pad electrode, and a gate pad electrode by performing a fifth mask process. The method of claim 1, wherein the forming of the pixel electrode and the buffer film on the substrate by performing the third mask process is performed.
Forming a transparent metal film on the substrate on which the source and drain electrodes, the semiconductor pattern, the data line, and the data pad are formed;
Forming a photoresist pattern through a photo process using the third mask after forming the photoresist on the transparent metal film;
Etching the transparent metal layer using the photoresist pattern as an etching mask to form the pixel electrode and the buffer layer;
And removing the photoresist pattern through a strip process using an O ₂ plasma. The method of claim 2, wherein the buffer film
O ₂ above The method of manufacturing a thin film transistor array substrate, characterized in that the anti-oxidation film of the data pad during the strip process using plasma. The method of claim 1, wherein the second mask is
A method of manufacturing a thin film transistor array substrate, characterized by using three different transmittance masks.

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